PTAB

IPR2017-01864

Toshiba Corp v. Macronix Intl Co Ltd

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1. Case Identification

2. Patent Overview

  • Title: Memory Device and Operation Thereof
  • Brief Description: The ’602 patent is directed to a semiconductor memory device that seeks to solve a problem of current leakage in prior art devices. The patent asserts that conventional memory arrays with dummy cells and dummy word lines at the edge suffer from over-erasure of the dummy cells, leading to leakage. The purported invention is a memory device and method where a positive bias is supplied to the dummy word line during an erase operation, causing the dummy cells to be weakly programmed instead of over-erased, thereby reducing or preventing bit line leakage.

3. Grounds for Unpatentability

Ground 1: Claims 1-12 and 16 are anticipated under 35 U.S.C. §102 by Kurata.

  • Prior Art Relied Upon: Kurata (Japanese Published Patent Application H10-275484).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kurata discloses every element of the challenged claims. Kurata describes a non-volatile semiconductor memory device comprising an array of memory cells (e.g., M11, M21) and a row of dummy memory cells (MTR1, MTR2) arranged at the bottom edge of the array. A dummy word line (labeled "SV") is explicitly shown arranged at the edge of the array and coupled to these dummy cells. Furthermore, Kurata discloses a control circuit that supplies a positive bias (a 5V potential) to the dummy word line SV during an erase operation, and also shows bit lines (D1, D2) coupled to the memory cells, including the dummy cells. Petitioner asserted that these disclosures map directly onto the limitations of independent claims 1, 7, and 11.
    • Key Aspects: Petitioner contended that Kurata's second embodiment, which uses dummy memory cells (MTR1, MTR2) having the same configuration as the main memory cells, operates under the same voltage conditions as its first embodiment. This includes applying the positive 5V bias to the dummy word line SV during an erase, thus anticipating the core inventive concept of the ’602 patent.

Ground 2: Claims 1-12 and 16 are obvious under 35 U.S.C. §103 over Maruyama in view of Lee.

  • Prior Art Relied Upon: Maruyama (Patent 6,272,049) and Lee (Patent 6,258,668).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Maruyama discloses most elements of the challenged claims. Maruyama teaches a flash memory device with two memory cell arrays, each containing both normal memory cells and dummy cells (D0-D7). Crucially, Maruyama discloses dummy word lines (TDWL, BDWL) arranged at the edge of each respective array. Maruyama explains that during an erase cycle, "a predetermined potential" is supplied to the dummy word lines to release electrons from the floating gates. However, Petitioner argued Maruyama is ambiguous as to whether the required higher positive potential is applied to the dummy word line or the dummy source line, leaving a design choice.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA), faced with Maruyama’s ambiguity, would combine its teachings with Lee. A POSITA would combine Maruyama's dummy cell architecture with Lee's explicit teaching of a conventional erase method for flash memory. Lee teaches performing an erase operation by applying a high positive voltage directly to the word lines to induce Fowler-Nordheim tunneling between the floating gate and the control gate. Petitioner argued a POSITA would be motivated to apply Lee's well-understood and specific erase mechanism to resolve Maruyama's ambiguity, thereby arriving at the claimed invention. This combination would not only provide a predictable erase method but also balance insulation degradation by using different layers for programming and erasing.
    • Expectation of Success: A POSITA would have a reasonable expectation of success in this combination. Applying Lee's conventional erase technique (a high positive voltage on the word line) to Maruyama's dummy cells would predictably cause erasure via the well-known physical mechanism of Fowler-Nordheim tunneling. The result is not an unexpected outcome but a predictable application of known principles to a known device structure.

4. Key Claim Construction Positions

  • "dummy word line" (claims 1, 6, 7, 11): Petitioner proposed this term be construed as "a conductive line coupled to the gates of dummy cells, which are memory cells that are not used to store data." This construction was argued to be consistent with the ’602 patent's specification, which distinguishes dummy cells based on their function (not used for data storage) rather than their structure. This interpretation is critical to the invalidity arguments, as it allows prior art references like Kurata, which describe dummy cells as being structurally similar to normal memory cells but used for non-storage purposes, to meet the claim limitation.

5. Relief Requested

  • Petitioner requests the institution of an inter partes review and the cancellation of claims 1-12 and 16 of Patent 6,788,602 as unpatentable.
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