Redstone Logics LLC v. Qualcomm Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Redstone Logics LLC (Texas)
  • Defendant: Qualcomm Inc. (Delaware); Qualcomm Technologies, Inc. (Delaware)
  • Plaintiff's Counsel: Russ August & Kabat
• Case Identification: 7:26-cv-00221, W.D. Tex., 06/05/2026
• Venue Allegations: Venue is alleged to be proper based on Defendants having transacted business in the district, committed acts of infringement in the district, and maintained a regular and established place of business in the district.
• Core Dispute: Plaintiff alleges that Defendant's System-on-Chips (SoCs) featuring the Oryon CPU architecture infringe a patent related to power and clock management for communication between different core clusters in a multi-core processor.
• Technical Context: The technology concerns methods for enabling different groups of processor cores on a single chip to operate at independent voltages and clock speeds to improve power efficiency, a critical feature in modern mobile and computing devices.
• Key Procedural History: The complaint references two prior lawsuits involving the same patent-in-suit: Redstone Logics LLC v. Samsung (involving Qualcomm components) and another filed directly against Qualcomm concerning different accused products (based on ARM's big.LITTLE and DynamIQ architectures). Plaintiff leverages these prior cases to assert pre-suit knowledge and willfulness.

Case Timeline

Date	Event
2010-02-26	'339 Patent Priority Date
2013-10-01	'339 Patent Issue Date
2023-10-17	Plaintiff files suit against Samsung asserting the '339 Patent
2024-09-20	Plaintiff files first suit against Qualcomm asserting the '339 Patent
2026-06-05	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,549,339 - "Processor core communication in multi-core processor"

Issued: October 1, 2013

The Invention Explained

• Problem Addressed: The patent's background explains that conventional multi-core processors often require all cores to share the same supply voltage and clock signal to simplify inter-core communication ʼ339 Patent, col. 1:5-9 This architecture is inefficient for power management, as it prevents some cores from running at a lower power state while others operate at high performance ʼ339 Patent, col. 1:10-15
• The Patented Solution: The invention proposes a multi-core processor architecture divided into distinct "regions" or "stripes" of processor cores ʼ339 Patent, col. 2:20-25 Each stripe can be associated with an independent power profile, receiving its own supply voltage from a power control block and its own clock signal from a clock control block ʼ339 Patent, col. 2:26-31 To manage communication across these different voltage and clock domains, the patent discloses an "interface block" positioned between the stripes ʼ339 Patent, abstract '339 Patent, col. 8:1-6 This block is responsible for facilitating communication, which can involve synchronizing different clock signals or translating different voltage levels ʼ339 Patent, col. 3:45-55 '339 Patent, col. 4:5-9
• Technical Importance: This design enables heterogeneous power and performance domains on a single chip, allowing for a more sophisticated balance of performance and power efficiency, a concept fundamental to modern SoC designs.

Key Claims at a Glance

• The complaint asserts independent claim 1 and reserves the right to assert other claims Compl. ¶9 Compl. ¶13
• The essential elements of independent claim 1 are:
  • A first set of processor cores configured to dynamically receive a first supply voltage and a first output clock signal from a first phase lock loop (PLL).
  • A second set of processor cores configured to dynamically receive a second supply voltage and a second output clock signal from a second PLL.
  • The first supply voltage is "independent" from the second supply voltage, and the first clock signal is "independent" from the second clock signal.
  • An "interface block" coupled to both sets of cores and configured to "facilitate communication" between them.

III. The Accused Instrumentality

Product Identification

The complaint identifies SoCs implementing or based on Qualcomm's Oryon architecture, including but not limited to the Snapdragon X, X Elite, X Plus, and other related product lines Compl. ¶9

Functionality and Market Context

• The accused products are SoCs that feature multiple "CPU Clusters," with each cluster containing a set of processor cores Compl. Ex. 2, p. 3 The complaint alleges, based on technical documentation, that each of these clusters has its own PLL and can be "individually clocked and powered on," establishing independent power and clock domains Compl. Ex. 2, p. 5
• Communication between these distinct clusters is allegedly managed by a "fabric" that connects the clusters to each other, a System Level Cache (SLC), and other resources Compl. Ex. 2, p. 7 A diagram from an architectural overview shows CPU clusters connected via a Bus Interface Unit to a shared "Fabric" and "System Level Cache (6MB)". Compl. Ex. 2, p. 8
• The complaint notes that Qualcomm has publicly positioned the Oryon architecture as a custom design that is distinct from previous ARM-based architectures that were the subject of prior litigation Compl. ¶10

IV. Analysis of Infringement Allegations

'339 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a first set of processor cores of the multi-core processor, wherein each processor core from the first set of processor cores is configured to dynamically receive a first supply voltage and a first output clock signal of a first phase lock loop (PLL) having a first clock signal as input;	The accused SoCs, such as the Snapdragon X, contain multiple "CPU Clusters." Each cluster is alleged to be a set of processor cores and to have its own PLL.	¶13	col. 8:51-54
a second set of processor cores of the multi-core processor, wherein each processor core from the second set of processor cores is configured to dynamically receive a second supply voltage and a second output clock signal of a second PLL having a second clock signal as input, wherein the first supply voltage is independent from the second supply voltage, and the first clock signal is independent from the second clock signal; and	The complaint alleges that the accused SoCs include at least a second CPU cluster. Based on technical documents, it is alleged each cluster can be "individually clocked and powered on," meaning its voltage and clock are independent of other clusters. A marketing diagram shows multiple distinct "CPU Cluster" blocks. Compl. Ex. 2, p. 5	¶13	col. 8:56-64
an interface block coupled to the first set of processor cores and also coupled to the second set of processor cores, wherein the interface block is configured to facilitate communication between the first set of processor cores and the second set of processor cores.	The complaint alleges that a "fabric" and/or System Level Cache (SLC) in the accused SoCs is coupled to the CPU clusters and "facilitates communications between the clusters themselves, the system level cache, and other resources." An architectural diagram shows this "Fabric" connecting the clusters. Compl. Ex. 2, p. 8	¶13	col. 8:1-6

Identified Points of Contention

• Scope Questions: A central question may be whether the accused product's "fabric" and "System Level Cache" meet the definition of the claimed "interface block." While the claim language "facilitate communication" is broad, the patent specification describes embodiments with specific functions like clock synchronization and voltage level shifting ʼ339 Patent, figs. 2-3 The dispute may turn on whether the accused "fabric" performs these or equivalent functions.
• Technical Questions: The meaning of "independent" supply voltage and clock signals may be contested. The complaint alleges the clusters can be "individually clocked and powered on" Compl. Ex. 2, p. 5, which supports independence. However, the patent specification also discusses maintaining a "differential relationship" between the supply voltages of adjacent stripes ʼ339 Patent, col. 2:61-col. 3:7 This raises the question of whether the accused products' power management scheme, which may involve co-regulation of voltages across clusters, falls within the scope of "independent" as claimed.

V. Key Claim Terms for Construction

"interface block"

• Context and Importance: This term is the structural and functional hub of the claimed invention, connecting the otherwise independent sets of cores. The infringement case depends on mapping this term to the accused SoCs' "fabric" and/or cache architecture. Practitioners may focus on this term because its construction will determine the level of functional proof required from the plaintiff.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim itself defines the term by its function: a block "configured to facilitate communication" ʼ339 Patent, col. 8:3-6 This broad functional language could support an interpretation that covers any hardware bus, fabric, or cache that enables data transfer between the core sets.
  • Evidence for a Narrower Interpretation: The specification discloses specific embodiments of the interface block containing "level shifters" to translate voltage levels and "synchronizers" to manage different clock domains (ʼ339 Patent, col. 3:26-30; ʼ339 Patent, col. 4:5-9). Dependent claims 2 and 4 explicitly recite these components. A defendant may argue these embodiments limit the term to a block that actively manages domain crossings, rather than a more general-purpose communication fabric.

"independent"

• Context and Importance: The claim requires that both the supply voltage and the clock signal for the first set of cores be "independent" from those of the second set. This term is critical because modern SoCs employ complex power management schemes where different domains might be co-regulated. The validity of the infringement allegation rests on whether the accused architecture exhibits the requisite level of independence.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The plain meaning of "independent" suggests the voltages and clocks can be set and changed without regard to one another. The complaint points to evidence that clusters can be individually powered on or put to sleep, supporting this view Compl. Ex. 2, p. 5
  • Evidence for a Narrower Interpretation: The specification discusses a constraint where control blocks "select the first supply voltage and the second supply voltage to maintain a differential relationship between the first supply voltage and the second supply voltage" ʼ339 Patent, col. 7:35-39 This suggests that the voltages, while different, may not be truly independent but rather are managed in a coordinated fashion. A defendant could use this language to argue that the term "independent" in the claims should be read in light of this disclosed relationship.

VI. Other Allegations

Indirect Infringement

The complaint alleges inducement of infringement, stating that Defendants "actively encourage and instruct" customers and end users to use the accused SoCs in an infringing manner through "engineering documents," "user manuals," and "online instruction materials" Compl. ¶12 It is also alleged that the products are configured to infringe "out of the box" Compl. ¶12

Willful Infringement

Willfulness is alleged based on both pre-suit and post-suit knowledge of the '339 Patent. The complaint alleges pre-suit knowledge stemming from two prior infringement actions: Redstone Logics LLC v. Samsung (filed Oct. 17, 2023, concerning products with Qualcomm components), and a prior direct action against Qualcomm (filed Sep. 20, 2024) Compl. ¶11 Compl. ¶15 Compl. ¶16 Continued infringement after these notices is alleged to be willful Compl. ¶16

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of claim construction: Will the term "interface block" be interpreted broadly to cover any communication fabric, as the claim language suggests, or will its scope be narrowed by the specification's examples of specific level-shifting and synchronization hardware, placing a higher evidentiary burden on the plaintiff?
• A second key question will be one of definitional scope: Can the term "independent," as applied to supply voltages and clock signals, encompass a system where power domains are co-regulated to maintain a "differential relationship," as described in the patent's own specification? The answer will determine if the accused products' sophisticated power management schemes fall inside or outside the claim's scope.
• Finally, a central question for damages will be timing of notice: Did Qualcomm have notice of the alleged infringement from the earlier lawsuit involving its customer, Samsung, or did notice only begin with the first direct lawsuit filed against it? The court's finding on this point will significantly influence the potential for enhanced damages and the start date for any royalty calculations.