Monolithic 3D Inc v. NVIDIA Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: MonolithIC 3D™ Inc. (Texas)
  • Defendant: NVIDIA Corp (Delaware)
  • Plaintiff's Counsel: Fabricant, Rubino & Lambrianakos LLP
• Case Identification: 7:26-cv-00190, W.D. Tex., 05/11/2026
• Venue Allegations: Venue is based on Defendant Nvidia's alleged regular and established place of business, transaction of business, and commission of infringing acts within the Western District of Texas.
• Core Dispute: Plaintiff alleges that Defendant's high-performance graphical processing units (GPUs) and System-on-Chips (SoCs), which incorporate High Bandwidth Memory (HBM), infringe four patents related to 3D semiconductor device structures and fabrication methods.
• Technical Context: The lawsuit concerns monolithic 3D integrated circuits (3D-ICs), a semiconductor technology essential for creating high-density, high-performance memory like HBM, which is critical for the artificial intelligence (AI) and high-performance computing (HPC) markets.
• Key Procedural History: The complaint alleges that Nvidia had knowledge of the patents-in-suit from prior litigations filed by Monolithic against SK hynix, the manufacturer of the HBM components used in Nvidia's accused products. This alleged pre-suit knowledge forms the basis of the willfulness allegations.

Case Timeline

Date	Event
2014-08-26	Earliest Priority Date for '330 Patent and '961 Patent
2015-09-21	Earliest Priority Date for '830 Patent
2020-03-01	Alleged Infringement Start Date (Nvidia GH100/GH200 Launch)
2025-03-11	'830 Patent Issued
2025-07-15	'330 Patent Issued
2025-08-26	'961 Patent Issued
2025-11-26	Alleged Date of Nvidia's Knowledge from Prior Litigation
2026-02-24	'006 Patent Issued
2026-05-11	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

The complaint did not include a copy of the '006 patent as an exhibit. The following analysis is based on the claim language and technical allegations provided in the complaint.

U.S. Patent No. 12,564,006 - 3D Semiconductor Device and Structure with Memory Cells and Multiple Metal Layers (Issued Feb. 24, 2026)

The Invention Explained

• Problem Addressed: The complaint alleges that the patents-in-suit address the need for advanced semiconductor memory devices and fabrication methods to create high-density, high-performance integrated circuits Compl. ¶14
• The Patented Solution: The patent describes a 3D semiconductor device constructed from multiple vertically stacked levels of transistors and memory cells Compl. ¶25 This structure allows for building integrated circuits in three dimensions, which can increase component density and performance. The claimed device comprises at least four distinct levels of transistors built atop a base level containing memory control circuits on a single crystal layer, with vertical connections provided by vias Compl. ¶25
• Technical Importance: This monolithic 3D stacking approach enables the creation of high-density memory, such as HBM, within a smaller footprint than traditional 2D manufacturing would allow Compl. ¶12 Compl. ¶14

Key Claims at a Glance

• Independent Claim 1 is asserted Compl. ¶25
• The essential elements of Claim 1 include:
  • A 3D semiconductor device.
  • A first level comprising a first single crystal layer with first transistors and memory control circuits.
  • First and second metal layers.
  • Second, third, and fourth levels, each comprising a plurality of transistors and overlaying the level below it.
  • The second level comprises a plurality of first memory cells, and the fourth level comprises a plurality of second memory cells.
  • The second memory cells comprise at least four independently controlled memory arrays.
  • Dielectric electrical isolation layers and vias for vertical connection between the levels.
  • At least one of the second transistors comprises a metal gate.
• The complaint reserves the right to assert other claims Compl. ¶24

U.S. Patent No. 12,362,330 - 3D Semiconductor Device and Structure with Connection Paths (Issued Jul. 15, 2025)

The Invention Explained

• Problem Addressed: The patent background discusses the need to improve performance and functionality in integrated circuits, which is increasingly limited by the performance of the wires (interconnects) that connect transistors US12362330B2, col. 1:40-47 3D stacking is presented as a way to shorten these wire lengths US 12,362,330 B2, col. 1:48-54
• The Patented Solution: The patent describes a 3D semiconductor device with multiple stacked levels of transistors connected by "a plurality of connection paths" US 12,362,330 B2, abstract This architecture allows for dense vertical integration of different circuit layers. For example, the detailed description explains forming a multi-layer structure where transistors on an upper level can be electrically connected to transistors on a lower level through these paths US 12,362,330 B2, col. 6:1-12
• Technical Importance: This technology facilitates the creation of complex, multi-layered systems, such as combining logic and memory dice, by providing a defined structure for vertical interconnection, which is essential for HBM technology Compl. ¶14

Key Claims at a Glance

• Independent Claim 8 is asserted Compl. ¶46
• The essential elements of Claim 8 include:
  • A 3D semiconductor device.
  • A first level comprising a first layer (with first transistors) and a second layer (with first interconnections).
  • A second level overlaying the first, comprising second transistors and a third layer with first conductive lines.
  • A third level overlaying the second, comprising third transistors and a fourth layer with second conductive lines.
  • A plurality of connection paths providing electrical connections from the first transistors to the third transistors.
  • The first level comprises at least one Phase-Locked Loop (PLL) circuit.
• The complaint reserves the right to assert other claims (Compl. ¶45).
  Multi-Patent Capsules

U.S. Patent No. 12,250,830: 3D Semiconductor Memory Devices and Structures (Issued Mar. 11, 2025)

• Technology Synopsis: The patent describes a 3D semiconductor device featuring a first level with a memory control circuit built on a single crystal layer, overlaid by multiple metal layers and additional levels of transistors US12250830B2, abstract The invention aims to provide a specific structure for 3D memory devices, including elements like a Look Up Table (LUT) circuit in the memory controller, to enable complex memory functionality in a stacked configuration US 12,250,830 B2, col. 2:50-55
• Asserted Claims: At least independent Claim 4 is asserted Compl. ¶61
• Accused Features: The complaint alleges that the logic die in the accused HBM products contains the claimed memory control circuit, including the required LUT, and that the overall stacked structure meets the claim limitations Compl. ¶¶62-70

U.S. Patent No. 12,400,961: 3D Semiconductor Device and Structure with Metal Layers (Issued Aug. 26, 2025)

• Technology Synopsis: This patent discloses a 3D semiconductor device built on multiple stacked levels of transistors, featuring several distinct metal layers connected to the transistors US12400961B2, abstract Key aspects include the presence of a temperature sensor and a manufacturing method wherein at least one element in one transistor layer is processed independently from an element in another transistor layer, which is characteristic of die-stacking technologies (US 12,400,961 B2, abstract).
• Asserted Claims: At least independent Claim 1 is asserted Compl. ¶80
• Accused Features: The complaint alleges the accused HBM products contain a temperature sensor as required by the JEDEC HBM3 standard, and that the DRAM dies in the HBM stack are manufactured separately and independently before stacking, thereby meeting the independent processing limitation Compl. ¶¶88-89

III. The Accused Instrumentality

• Product Identification: The complaint identifies the "Accused Products" as Nvidia's graphical processing units, SoCs, and processors that include HBM products Compl. ¶15 Specific examples cited are the Nvidia GH100 and GH200 Grace Hopper Superchips Compl. ¶15
• Functionality and Market Context: The Accused Products are high-performance processors used in AI and HPC applications Compl. ¶20 The complaint focuses on the HBM memory component within these products, specifically identifying the SK Hynix HBM3 product (part number H5UG7HMD83X020R) as the infringing instrumentality Compl. ¶16 Compl. ¶18 The complaint includes an image of the Nvidia GH100 chip, identifying the GPU die and six surrounding SK Hynix HBM packages, to illustrate the integration of the accused memory into Nvidia's larger system Compl. ¶18 The complaint alleges that this HBM technology is a key feature, citing Nvidia marketing that the GH200 is the "world's first processor to include HBM3e memory" Compl. ¶16

IV. Analysis of Infringement Allegations

'006 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel	The Accused Product is a 3D semiconductor device. The HBM logic die at the bottom of the stack constitutes the first level and is formed on a single crystal silicon substrate, containing the first transistors.	¶26	Not Provided
a first metal layer, said first metal layer is disposed above or below said first level; a second metal layer overlaying said first metal layer	The HBM logic die contains multiple metal layers, which are identified as the first and second metal layers. A micrograph in the complaint shows these layers in cross-section.	¶27	Not Provided
a second level comprising a plurality of second transistors, said second level overlaying said first level	The first HBM DRAM die stacked on top of the logic die constitutes the second level, which contains a plurality of second transistors.	¶28	Not Provided
a third level comprising a plurality of third transistors, said third level overlaying said second level	The second HBM DRAM die stacked on top of the first DRAM die constitutes the third level, containing a plurality of third transistors.	¶29	Not Provided
a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level	The third HBM DRAM die stacked on top of the second DRAM die constitutes the fourth level, containing a plurality of fourth transistors.	¶30	Not Provided
wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors	The second level (the first HBM DRAM die) contains a plurality of memory cells, which include the DRAM cell access transistors.	¶31	Not Provided
wherein said first level comprises memory control circuits	The first level (the HBM logic die) contains the memory control circuits that manage addressing and data flow for the entire HBM stack. A delayered optical image of the HBM Logic Die is provided as evidence.	¶33	Not Provided
wherein second memory cells comprise at least four memory arrays, wherein each of said four memory arrays are independently controlled	The complaint alleges that each HBM DRAM die is designed with at least four memory arrays that must be independently controlled to function as random access memory, citing a JEDEC standard document.	¶34	Not Provided
wherein said first level, said second level, said third level, and said fourth level each comprise a dielectric electrical isolation layer disposed in-between and comprise vias and/or thru-layer vias for vertical connection	The accused HBM stack uses through-silicon vias (TSVs) for vertical connection between the stacked dies, and these structures include a dielectric liner for electrical isolation.	¶35	Not Provided
and wherein at least one of said second transistors comprises a metal gate.	The wordlines of the memory cells, which form the gates of the second transistors, are alleged to be made of tungsten, a metal.	¶36	Not Provided

'330 Infringement Allegations

Claim Element (from Independent Claim 8)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a 3D semiconductor device, the device comprising: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer, said second layer comprising first interconnections	The HBM logic die constitutes the first level, which comprises a first layer of transistors and a second layer of metal interconnects.	¶47	col. 5:58-62
a second level overlaying said first level, wherein said second level comprises a plurality of second transistors, wherein said second level comprises a third layer, said third layer comprising first conductive lines	The first HBM DRAM die constitutes the second level, containing second transistors. This level includes a layer of conductive lines (a "third layer").	¶48	col. 6:1-5
a third level overlaying said second level, wherein said third level comprises a plurality of third transistors, wherein said third level comprises a fourth layer, said fourth layer comprising second conductive lines	The second HBM DRAM die constitutes the third level, containing third transistors and a layer of conductive lines (a "fourth layer").	¶49	col. 6:6-10
and a plurality of connection paths, wherein said plurality of connection paths provides electrical connections from a plurality of said first transistors to said plurality of third transistors	Through-silicon vias (TSVs) are alleged to form the connection paths that electrically connect the first transistors (in the logic die) to the third transistors (in the second DRAM die). The complaint provides an illustrative diagram of this vertical connection.	¶50	col. 6:23-28
and wherein said first level comprises at least one PLL circuit.	The HBM logic die (first level) is alleged to include at least one PLL circuit, which the complaint asserts is required to meet HBM3 specifications for clocking. The complaint points to a block diagram from the JEDEC HBM3 standard.	¶51	col. 6:29-31

• Identified Points of Contention:
  • Scope Questions: The case may raise questions about whether the structural terms used in the patents, such as "level," "layer," and "overlaying," can be definitively mapped to the physical structures of the accused HBM3 products as alleged by the Plaintiff. For example, for the '006 patent, the court will need to determine if the logic die and successive DRAM dies constitute the claimed "first," "second," "third," and "fourth" levels.
  • Technical Questions: A key technical question for the '330 patent will be whether the Through-Silicon Vias (TSVs) in the accused device, which provide vertical connectivity through the entire stack, perform the specific function of the claimed "plurality of connection paths" that provide electrical connections "from a plurality of said first transistors to said plurality of third transistors." The defense may argue that the function of the physical TSVs does not precisely match the claimed function. Similarly, for the '830 patent, a question is whether the accused product's circuitry for "interconnect redundancy mapping" Compl. ¶69, alleged to meet a JEDEC standard, constitutes the claimed "Look Up Table circuit."

V. Key Claim Terms for Construction

For U.S. Patent No. 12,564,006:
The complaint does not provide the patent specification for analysis. The following is based on the claim language as quoted in the complaint.

• The Term: "overlaying"
• Context and Importance: This term is used repeatedly in Claim 1 to define the vertical relationship between the different "levels" of the device (e.g., "second level... overlaying said first level") Compl. ¶25 Its construction will be critical to determining if the vertically stacked dies in the accused HBM product meet the structural requirements of the claim. Practitioners may focus on this term because the physical interface between stacked dies in an HBM product (connected by microbumps and TSVs) may differ from what is contemplated by the patent's use of "overlaying."
• Intrinsic Evidence for Interpretation: The complaint does not provide sufficient detail for analysis of this term.

For U.S. Patent No. 12,362,330:

• The Term: "connection paths"
• Context and Importance: Claim 8 requires "a plurality of connection paths, wherein said plurality of connection paths provides electrical connections from a plurality of said first transistors to said plurality of third transistors" Compl. ¶46 The complaint alleges these are the TSVs Compl. ¶50 The definition of "connection paths" is central to the infringement analysis, as it must link specific transistors across multiple die layers.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent specification describes the connection paths in general terms, stating they "provide electrical connections from a plurality of the first transistors to the plurality of third transistors" US 12,362,330 B2, col. 6:25-28 This broad functional language could support an interpretation covering any vertical interconnect structure that achieves this purpose, such as TSVs.
  • Evidence for a Narrower Interpretation: The patent does not appear to provide an explicit, limiting definition or a specific embodiment that would substantially narrow the term beyond its functional description. However, a defendant may argue that the context of the invention, which focuses on monolithic integration, implies a type of connection path different from the TSVs used in stacked, separately manufactured dies.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement against Nvidia, stating that Nvidia's "affirmative acts of manufacturing, selling, distributing, and/or otherwise making available the Accused Products, and providing instructions, documentation, and other information to customers and end-users" encourage direct infringement by those customers Compl. ¶38 Compl. ¶53 The complaint also alleges contributory infringement, stating the accused components are not staple articles of commerce and have no substantial non-infringing uses Compl. ¶39 Compl. ¶54
• Willful Infringement: Willfulness is alleged based on Nvidia's purported knowledge of the patents-in-suit "from prior litigations at least as of November 26, 2025" Compl. ¶21 These prior litigations were against SK hynix, the supplier of the accused HBM components. The complaint asserts that because these litigations accused the specific SK hynix parts that Nvidia incorporates, Nvidia was on notice of its own infringement Compl. ¶40 Compl. ¶55

VII. Analyst's Conclusion: Key Questions for the Case

This case will likely center on three key questions for the court:

1. A core issue will be one of claim construction and technical correspondence: Can the specific, multi-level structures described in the patents, such as a "fourth level comprising a plurality of fourth transistors," be proven to read on the physical architecture of the accused HBM3 memory stacks? The dispute will likely involve extensive expert testimony on the construction and operation of 3D-ICs.

2. A significant legal question will be one of willfulness and knowledge: Can Monolithic establish that Nvidia's knowledge of prior lawsuits against its component supplier, SK hynix, is sufficient to meet the standard for willful infringement? This will test the boundaries of how knowledge is imputed to a downstream customer that integrates an allegedly infringing component.

3. An evidentiary question will be one of functional vs. structural infringement: The complaint often alleges the presence of claimed structures (e.g., a "PLL circuit," a "temperature sensor," a "LUT circuit") by pointing to industry standards (JEDEC) that the accused products must comply with. The court will need to determine if compliance with a standard that requires a certain function is sufficient evidence to prove the existence of the specific structure as claimed in the patents.