Speednic LLC v. NVIDIA Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: SpeedNIC LLC (Texas)
  • Defendant: NVIDIA Corp (Delaware); Dell Technologies Inc. (Delaware)
  • Plaintiff's Counsel: Reichman Jorgensen Lehman & Feldberg LLP; Cherry Johnson Siegmund James PC
• Case Identification: 7:26-cv-00148, W.D. Tex., 07/10/2026
• Venue Allegations: Venue is alleged to be proper based on Defendants each having committed acts of infringement and maintaining a regular and established place of business within the Western District of Texas.
• Core Dispute: Plaintiff alleges that Defendants' Data Processing Units (DPUs), network interface controllers (NICs), and server products that incorporate them infringe five patents related to offloading network processing, filtering, and data placement tasks from a host computer's central processing unit (CPU).
• Technical Context: The technology concerns high-performance networking hardware, specifically DPUs and SmartNICs, designed to accelerate data center and artificial intelligence infrastructure by handling network-related tasks directly on the NIC, thereby freeing up CPU resources.
• Key Procedural History: This is a First Amended Complaint, following an original complaint filed on April 16, 2026. The complaint alleges that the asserted patents were previously developed and owned by Chelsio Communications, Inc. It further alleges Defendants' pre-suit knowledge based on NVIDIA's acquisition of Mellanox (which had cited the asserted patents during its own patent prosecution) and Dell's prior collaborations with Chelsio.

Case Timeline

Date	Event
2005-10-13	U.S. Patent No. 7,760,733 Priority Date
2007-05-11	U.S. Patent No. 7,826,350 Priority Date
2007-05-11	U.S. Patent No. 8,589,587 Priority Date
2007-05-11	U.S. Patent No. 8,060,644 Priority Date
2010-02-12	U.S. Patent No. 8,621,627 Priority Date
2010-07-20	U.S. Patent No. 7,760,733 Issued
2010-11-02	U.S. Patent No. 7,826,350 Issued
2011-11-15	U.S. Patent No. 8,060,644 Issued
2013-11-19	U.S. Patent No. 8,589,587 Issued
2013-12-31	U.S. Patent No. 8,621,627 Issued
2026-04-16	Original Complaint Filed and Served
2026-07-10	First Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,760,733 - "Filtering ingress packets in network interface circuitry"

The Invention Explained

• Problem Addressed: The patent addresses the inefficiency of performing network data filtering on a host computer, which consumes significant CPU resources and may not scale well in high-speed networks ʼ733 Patent, col. 1:21-28 Conventional network offload solutions were typically tied to processing for specific, established connections rather than providing a flexible filtering mechanism for all ingress traffic ʼ733 Patent, col. 2:4-21
• The Patented Solution: The invention describes a network interface circuitry (NIC) that can offload the filtering of incoming data packets. This NIC uses specialized lookup circuitry (e.g., a TCAM) to automatically apply filtering rules to packets based on their characteristics ʼ733 Patent, abstract The rules are organized with a priority system, allowing the NIC to determine a single highest-priority action (such as protocol processing for an offloaded connection, or a specific filtering action) from a plurality of potential actions ʼ733 Patent, col. 5:1-30 This allows for complex firewall or load-balancing logic to be executed directly on the NIC before the data reaches the host CPU ʼ733 Patent, col. 2:42-56
• Technical Importance: This approach allows for line-rate, hardware-based filtering and policy enforcement on a per-packet basis, independent of host CPU availability, which is critical for security and traffic management in high-throughput data centers.

Key Claims at a Glance

• The complaint asserts independent claim 12 Compl. ¶51
• Claim 12 Elements:
  • Network interface circuitry configured to couple a host computer to a network.
  • Circuitry configured to receive data from the network.
  • Circuitry configured to process the received data to determine an indication of a highest priority one of a plurality of actions, wherein the processing includes presenting data to lookup circuitry that automatically provides the indication based on matching and on an order of the indications relative to each other in the lookup circuitry.
  • The actions include protocol processing for an offloaded connection or filtering for data not belonging to an offloaded connection.
  • Circuitry configured to provide the received data to the host computer with the highest priority action applied.
  • The providing circuitry is configured to selectively block the received data from the host based on the action being a filtering rule.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 8,621,627 - "Intrusion detection and prevention processing within network interface circuitry"

The Invention Explained

• Problem Addressed: In virtualized server environments, data traffic between virtual machines (VMs) on the same host is typically handled by a software-based "virtual switch," which can become a performance bottleneck. Furthermore, performing intrusion detection on this inter-VM traffic consumes host CPU resources ʼ627 Patent, col. 1:12-49
• The Patented Solution: The invention proposes a NIC with a data frame processing pipeline that can intelligently route network traffic. The NIC can determine if a received data frame requires "additional processing" (such as intrusion detection). If so, it provides the frame to the host (e.g., to a specialized security VM) via the host bus. After the host performs the processing, the NIC receives the processed frame back, again via the host bus, and then forwards it to its final destination, which could be another VM or a peer on the external network ʼ627 Patent, abstract '627 Patent, FIG. 1 This creates a "hairpin" or "tromboning" data path that offloads the switching logic to the NIC while allowing for sophisticated, host-based security analysis.
• Technical Importance: This architecture enables hardware-accelerated switching for inter-VM traffic while still allowing for flexible, software-based security services like intrusion detection and prevention to be applied, balancing performance with security in virtualized environments.

Key Claims at a Glance

• The complaint asserts independent claim 7 Compl. ¶73
• Claim 7 Elements:
  • A network interface controller (NIC) configured to couple a host to a network via a host bus, with the host operating a plurality of virtual machines.
  • The NIC includes a data frame processing pipeline configured to:
  • receive at least one data frame with source and destination network addresses.
  • based on an indication in the data frame, determine if it is a frame on which additional processing should occur.
  • based on the result, cause the frame to be provided to the host, via the host bus, for the host to perform the additional processing.
  • receive, via the host bus, the frame on which additional processing has been performed and provide the frame to a destination.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

Multi-Patent Capsule: U.S. Patent No. 7,826,350

• Patent Identification: U.S. Patent No. 7,826,350, "Intelligent network adaptor with adaptive direct data placement scheme," issued November 2, 2010.
• Technology Synopsis: The patent addresses the overhead of copying data from operating system (OS) memory to application-specific memory. The invention is a method where an intelligent network adaptor adaptively determines whether to place incoming data directly into an application's memory ("zero-copy") or into general OS memory, based on characteristics like the size of the application's request ʼ350 Patent, abstract '350 Patent, col. 6:1-24 This decision aims to optimize performance by avoiding the setup overhead of zero-copy for small data transfers where a traditional memory copy would be faster.
• Asserted Claims: At least Claim 1 Compl. ¶94
• Accused Features: The complaint alleges that Defendants' products, through the NVIDIA DOCA software framework, perform a method of determining a destination for payload data, including whether to deliver it directly to application memory via DMA/RDMA Compl. ¶¶98-99

Multi-Patent Capsule: U.S. Patent No. 8,589,587

• Patent Identification: U.S. Patent No. 8,589,587, "Protocol offload in intelligent network adaptor, including application level signalling," issued November 19, 2013.
• Technology Synopsis: The patent concerns reducing the rate of host CPU interruptions for network events. The invention describes an intelligent network adaptor that moderates the rate at which it sends payload arrival notifications to the host. This moderation is based on processing "application level notifications" found within the transport layer of received packets, such as TCP urgent (URG) or push (PSH) flags, without terminating the connection ʼ587 Patent, abstract '587 Patent, col. 6:3-12
• Asserted Claims: At least Claim 6 Compl. ¶118
• Accused Features: The complaint alleges that the Accused Products' use of "intelligent interrupt coalescence" and Dynamically-tuned Interrupt Moderation (DIM), which adjust notification rates based on packet stream characteristics, infringes the patent Compl. ¶125 It also alleges the processing of TCP URG and PSH flags as part of inline firewall capabilities meets the claim limitations Compl. ¶126

Multi-Patent Capsule: U.S. Patent No. 8,060,644

• Patent Identification: U.S. Patent No. 8,060,644, "Intelligent network adaptor with end-to-end flow control," issued November 15, 2011.
• Technology Synopsis: The patent describes a method for end-to-end flow control that is tied to the application's actual data consumption. An intelligent network adaptor places data directly into an application's host memory buffer. The transport protocol's receive window, which is advertised to the sending peer, is then increased only when the application actually consumes the data from its buffer, rather than simply when the data arrives in an OS buffer ʼ644 Patent, abstract '644 Patent, col. 1:15-30
• Asserted Claims: At least Claim 1 Compl. ¶141
• Accused Features: The complaint alleges that the Accused Products' programmable data plane performs TCP state tracking in hardware, and that the method of using BlueField to offload TCP processing involves adjusting the receive window based on available space in the application buffer Compl. ¶149

III. The Accused Instrumentality

Product Identification

• The complaint identifies a broad range of products, including NVIDIA's BlueField series of DPUs (BlueField-2, 3, 4), ConnectX series of NICs/SuperNICs, and the associated DOCA software development kit. It also accuses Dell products that incorporate this technology, including Dell BlueField Cards and Dell EMC PowerEdge Servers (e.g., R650, R750) Compl. ¶34

Functionality and Market Context

• The Accused Products are described as high-performance networking components central to modern data centers and AI infrastructure Compl. ¶¶1-2 Their key functionality, as alleged in the complaint, is to act as "infrastructure-focused processors" that offload networking, storage, and security workloads from the host CPU Compl. ¶4 The complaint highlights the NVIDIA DOCA (Data Center on a Chip Architecture) software framework, which provides libraries and drivers for programming the hardware pipelines on the BlueField DPUs to perform functions like packet processing, filtering, and steering Compl. ¶¶55 Compl. ¶61 The complaint cites a market report valuing the global DPU market at $4.5 billion in 2026, projected to grow significantly Compl. ¶5 A diagram from NVIDIA documentation shows the architecture of a BlueField-3 DPU, illustrating its key components including Arm cores, a ConnectX-7 network front-end, and a PCIe switch integrated into a single chip Compl. p. 20 ¶52

IV. Analysis of Infringement Allegations

'733 Patent Infringement Allegations

Claim Element (from Independent Claim 12)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
Network interface circuitry configured to couple a host computer to a network...	The Accused Products, such as BlueField DPUs, are designed to provide networking to server systems and couple a host CPU to a network.	¶52	col. 2:1-4
circuitry configured to receive data from the network;	BlueField contains network and port interfaces (e.g., Ethernet, InfiniBand) that enable it to receive data from the network.	¶54	col. 2:60-65
circuitry configured to process the received data to determine an indication of a highest priority one of a plurality of actions... based not only on whether the portion of the received data ... matches data ... but also based on an order of the indications of the plurality of actions relative to each other in the lookup circuitry...	The DOCA Flow software suite, used with BlueField, implements packet processing "pipes" that consist of match criteria and actions. The complaint alleges that priority is managed by "chaining pipes," where a packet is analyzed by the highest-priority pipe first, and a "miss" forwards traffic to a lower-priority pipe.	¶55	col. 5:1-30
wherein the actions include protocol processing with respect to a connection ... or filtering for received data which does not belong to a connection whose protocol processing is being handled by the network interface circuitry...	The complaint alleges that the "actions" available in DOCA Flow include both protocol processing and filtering, such as through access-control list (ACL) matching.	¶55	col. 5:31-40
circuitry configured to provide, to the host computer, the received data having the particular indicated highest priority action applied...	BlueField hardware is alleged to decide to forward a matched packet to the host software stack. It is also alleged that packets not matching a hardware pipe can be sent to the Arm cores (an example of a host) if it meets the highest priority action.	¶56	col. 6:40-50
wherein the circuitry ... is configured to selectively block the received data from being provided to the host computer based at least in part on the indicated particular action being a filtering rule...	The complaint alleges that DOCA Flow pipes may drop packets rather than forward them to a host destination. A diagram in the complaint illustrates how an application can decide to drop a packet.	¶57; ¶30	col. 2:46-52

A diagram provided in the complaint shows the architecture of the DOCA Flow library, which defines processing "pipes" with match criteria and actions, allegedly implementing the claimed priority-based processing Compl. p. 24

Identified Points of Contention

• Scope Question: A central question will be whether the alleged "chaining" of software-defined "pipes" in the DOCA Flow framework Compl. ¶55 constitutes "lookup circuitry that is configured to automatically provide the indication of the highest priority action ... based on an order of the indications ... relative to each other in the lookup circuitry" as recited in the claim. The defense may argue that the claim requires a specific hardware architecture, such as the prioritized TCAM described in the patent's specification ('733 Patent, col. 5:12-30), which may differ from the accused pipe-chaining mechanism.
• Technical Question: The complaint alleges that if a packet does not match a hardware rule, it can be sent to the DPU's Arm cores for handling, and that this meets the "provide to the host computer" limitation Compl. ¶56 An issue for the court may be whether the integrated Arm cores on a DPU can be considered the "host computer" in the context of this claim limitation, versus the separate server CPU to which the DPU is connected.

'627 Patent Infringement Allegations

Claim Element (from Independent Claim 7)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A network interface controller (NIC) configured to couple a host to a network, the NIC coupled to the host via a host bus...	BlueField DPUs are described as NICs coupled to a host CPU via a PCIe bus.	¶74	col. 1:51-56
...and the host configured to operate a plurality of virtual machines...	The complaint alleges that host CPUs operate virtual machines and that BlueField is "designed to enable efficient network switching in virtualized environments such as virtual machines (VMs) and containers."	¶75	col. 1:12-16
...the NIC including a data frame processing pipeline configured to: receive at least one data frame...	BlueField is alleged to contain a data path with a programmable packet parser that receives data frames from its Ethernet/InfiniBand ports.	¶76; ¶77	col. 3:19-21
based on an indication in the data frame, determine if the received data frame is a frame on which additional processing should occur;	The BlueField data frame processing pipeline is alleged to determine if data requires exception handling from an accelerator, ARM core, or host CPU, based on a programmable packet parser.	¶77	col. 3:31-36
based on a result of the determining step, cause the frame to be provided to the host, via the host bus, for the host to perform the additional processing; and	When operating in DPU mode, it is alleged that all host traffic flows through a virtual switch on the DPU's Arm subsystem before reaching the host, and that the ARM cores can act as a host to which frames are sent for processing.	¶78; ¶44	col. 3:37-41
receive, via the host bus, the frame on which additional processing has been performed and provide the frame to a destination...	The complaint alleges that BlueField enables data paths where frames are provided to the host for processing and then sent back to the NIC to be provided to a destination on the network.	¶79	col. 3:42-46

A diagram from NVIDIA's documentation illustrates the DPL (DOCA Pipeline Language) architecture, showing a data pipeline with a parser and tables that allegedly determines the data flow, including to the host Compl. p. 41

Identified Points of Contention

• Scope Question: The claim requires causing the frame to be provided "to the host, via the host bus" and then receiving it back "via the host bus." The complaint alleges this is met when the DPU's own internal Arm cores perform the "additional processing" Compl. ¶78 A critical dispute will likely be whether the DPU's integrated Arm subsystem can be considered "the host" and its internal data paths "the host bus" as those terms are used in the patent, or if the claim requires the frame to be sent externally to the main server CPU.
• Technical Question: The claim requires determining if a frame is one on which "additional processing should occur." The complaint alleges BlueField's pipeline can determine if a frame "requires exception handling" Compl. ¶77 The court may need to evaluate what technical evidence supports that the accused products make this specific determination as claimed, rather than simply routing all traffic of a certain type through a specific path.

V. Key Claim Terms for Construction

For the '733 Patent

• The Term: "highest priority one of a plurality of actions"
• Context and Importance: This term is central to how the patented filtering system selects among multiple potential rules (e.g., protocol offload rules vs. filtering rules). The infringement allegation hinges on the theory that the accused "pipe chaining" mechanism in DOCA Flow meets this limitation Compl. ¶55 Practitioners may focus on this term because its construction will determine whether a sequential, chained evaluation of rulesets can be considered equivalent to automatically selecting a single highest-priority action from a co-equal set.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language itself refers to an "order of the indications of the plurality of actions relative to each other," which may support an interpretation that includes sequential or chained priority systems, not just a single-step lookup in a flat priority space ʼ733 Patent, col. 16:29-32
  • Evidence for a Narrower Interpretation: The specification heavily features an embodiment using a Ternary Content-Addressable Memory (TCAM) where different types of rules (active connection, server, filter) are placed in distinct regions, and the TCAM hardware inherently returns the first matching entry, which has the lowest index value, thereby establishing a clear hardware-based priority (ʼ733 Patent, col. 5:12-30; ʼ733 Patent, FIG. 3). This could support a narrower construction requiring a lookup in a single, ordered memory structure.

For the '627 Patent

• The Term: "additional processing"
• Context and Importance: The claim requires the NIC to send a frame to the host to perform "additional processing." The complaint alleges this is met by functions like intrusion detection Compl. ¶77 The meaning of this term is critical because it defines the purpose of the traffic "hairpin" to the host. If construed broadly, it could cover any processing; if construed narrowly, it might be limited to the security context described in the patent.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term itself is not explicitly defined in the specification, which may support giving it a plain and ordinary meaning that could encompass any type of host-based processing beyond what the NIC handles. The abstract refers to this step without limitation to security.
  • Evidence for a Narrower Interpretation: The patent is titled "Intrusion detection and prevention processing..." and the background section is entirely focused on the challenges of intrusion detection in virtualized environments ʼ627 Patent, col. 1:8-49 This pervasive context may support an argument that "additional processing" should be construed as being limited to security-related functions like intrusion detection.

VI. Other Allegations

Indirect Infringement

• The complaint alleges both induced and contributory infringement for all asserted patents. Inducement is primarily based on allegations that Defendants author and publish extensive documentation, programming guides, and application templates (e.g., NVIDIA's DOCA documentation) that affirmatively instruct customers on how to configure and use the Accused Products in an infringing manner Compl. ¶¶61 Compl. ¶83 Compl. ¶107 Contributory infringement is alleged on the basis that the Accused Products contain dedicated hardware components (e.g., "hardware match-action pipes," "priority lookup and steering tables") that are a material part of the invention, are not staple articles of commerce, and are specially made for the infringing use Compl. ¶¶64-66 Compl. ¶¶86-88

Willful Infringement

• Willfulness is alleged based on both pre- and post-suit knowledge. The complaint alleges NVIDIA had pre-suit knowledge of the '587 and '644 patents because its subsidiary, Mellanox, cited them during the prosecution of its own patent applications Compl. ¶40 It also alleges knowledge for both defendants through NVIDIA's acquisition of Mellanox and Dell's business collaborations with Chelsio, the original patent owner Compl. ¶¶38-41 Willfulness is also alleged based on continued infringement after receiving notice via the original complaint filed on April 16, 2026 Compl. ¶44

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the term "host computer" in the '627 patent, which is coupled to the NIC "via a host bus," be construed to read on the integrated Arm processing cores within the DPU itself, or does it exclusively refer to the separate server CPU? The resolution of this question will be pivotal for the infringement analysis of routing traffic internally within a DPU.
• A second key issue will be one of architectural equivalence: for the '733 patent, does the Accused Products' use of a "pipe chaining" model, where rules are evaluated sequentially across different logical pipes, meet the claim requirement for "lookup circuitry" that automatically determines a "highest priority" action based on a pre-defined "order" of actions within that circuitry? The case may turn on whether this software-defined priority model is functionally and structurally equivalent to the hardware-prioritized TCAM described in the patent.
• A third central question will be one of knowledge and intent: given the detailed allegations of pre-suit knowledge through patent prosecution history and industry relationships, a key focus will be whether Plaintiff can prove that Defendants' alleged infringement, particularly after the acquisition of Mellanox and post-filing of the original complaint, was willful, which would expose Defendants to the risk of enhanced damages.