GlobalFoundries US Inc v. Tower Semiconductor Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: GlobalFoundries US. Inc. (Delaware)
  • Defendant: Tower Semiconductor Ltd. (Israel), Tower Partners Semiconductor Co. Ltd. (Japan), TOWER SEMICONDUCTOR ITALY S.R.L. (Italy), Tower US Holdings Inc. (Delaware), TOWER SEMICONDUCTOR NPB HOLDINGS INC. (Delaware), Tower Semiconductor Newport Beach Inc. (Delaware), and Tower Semiconductor San Antonio Inc. (Delaware) (collectively "Tower")
  • Plaintiff's Counsel: Cleary Gottlieb Steen & Hamilton LLP; Jackson Walker LLP
• Case Identification: 7:26-cv-00109, W.D. Tex., 03/26/2026
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant Tower San Antonio maintains a regular and established place of business (a semiconductor fabrication facility) and has committed acts of infringement within the district. Venue over other domestic defendants is alleged based on their status as alter egos or agents of Tower San Antonio, and venue over foreign defendants is alleged to be proper in any judicial district.
• Core Dispute: Plaintiff alleges that semiconductor devices manufactured using Defendant's various fabrication processes (including BCD, SiGe, BiCMOS, and RF processes) infringe six U.S. patents related to semiconductor device structures and manufacturing methods.
• Technical Context: The dispute centers on nanoscale manufacturing technologies for radio frequency (RF) and power management semiconductors, which are essential components for the automotive, communications, and consumer electronics industries.
• Key Procedural History: The complaint notes that Plaintiff has concurrently filed a suit against Defendant in the U.S. International Trade Commission asserting the same patents at issue in this case.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,330,235 - "Method To Reduce MOL Damage On NiSi"

The Invention Explained

• Problem Addressed: The patent's background describes how nickel silicide (NiSi) layers, critical for forming electrical contacts in modern transistors, are susceptible to damage during subsequent manufacturing steps, particularly the etching process used to remove overlying "stress liners." This damage degrades device performance and reliability '235 Patent, col. 2:55-62
• The Patented Solution: The invention is a transistor structure with a NiSi layer specifically engineered to resist this damage. The solution involves creating a "composition gradient" of platinum (Pt) within the NiSi layer, where the platinum concentration is lowest at the silicon interface and increases toward the top surface of the silicide. This platinum-rich top surface acts as a protective shield during subsequent etching processes, preserving the integrity of the underlying NiSi. '235 Patent, abstract '235 Patent, col. 5:4-10
• Technical Importance: This approach allows semiconductor manufacturers to use performance-enhancing stress liners without the trade-off of damaging the critical NiSi contact layers, thereby improving both device performance and manufacturing yield '235 Patent, col. 2:63-68

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶72
• The essential elements of independent claim 1 include:
  • A semiconductor device comprising a silicon substrate and a transistor with source/drain regions and a gate electrode.
  • A nickel silicide (NiSi) layer on the gate electrode and source/drain regions.
  • The NiSi layer comprises platinum (Pt) with a "composition gradient," where the amount of Pt increases in a direction away from the silicon interface.
  • The gradient starts from between about 8 wt. % and about 12 wt. % Pt at the silicon interface.

U.S. Patent No. 8,507,983 - "High Voltage Device"

The Invention Explained

• Problem Addressed: The patent's background explains the difficulty in fabricating reliable high-voltage transistors with short channel lengths using conventional manufacturing processes. Process variations, particularly "overlay issues," make it hard to precisely align the channel region, which is critical for achieving the low on-resistance (Rds_on) required for high performance '983 Patent, col. 1:16-41
• The Patented Solution: The patent describes a device structure where the channel is "self-aligned" to the gate. This is achieved by using the gate itself as a mask during the ion implantation step that forms the "doped channel well." This self-alignment process eliminates alignment variability, enabling the creation of consistently short and well-controlled channel lengths. The structure also features a "doped drift well" on the other side of the gate to manage high-voltage tolerance. '983 Patent, abstract '983 Patent, col. 2:4-14
• Technical Importance: This self-aligned architecture allows for the production of high-voltage transistors with improved power efficiency (lower Rds_on) and greater manufacturing consistency, making them more suitable for integration into advanced semiconductor products '983 Patent, col. 6:1-6

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶88
• The essential elements of independent claim 1 include:
  • A device with a substrate and a gate (comprising a gate electrode over a gate dielectric).
  • A "doped channel well" in the substrate adjacent to a first edge of the gate, where the gate edge overlaps the channel well to define a channel.
  • The channel is "displaced from a first heavily doped region" adjacent to the first gate edge.
  • A "doped drift well" is adjacent to a second edge of the gate.

U.S. Patent No. 9,093,425 - "Self-Aligned Liner Formed On Metal Semiconductor Alloy Contacts"

• Patent Identification: U.S. Patent No. 9,093,425, "Self-Aligned Liner Formed On Metal Semiconductor Alloy Contacts", issued July 28, 2015 Compl. ¶54
• Technology Synopsis: This patent describes a semiconductor structure with improved electrical contacts. The invention involves forming a protective liner on top of a metal semiconductor alloy contact (e.g., nickel silicide) by depositing a transition metal (e.g., titanium) that reacts with the contact's surface. This creates a "transition metal-metal semiconductor alloy" liner that is self-aligned to the contact and more resistant to subsequent etching processes, protecting the underlying contact from damage. '425 Patent, abstract
• Asserted Claims: At least independent claim 1 Compl. ¶105
• Accused Features: The complaint alleges that devices manufactured using Tower's SiGe, BiCMOS, and RF processes, which are incorporated into products such as the DENSO DNSRR004 radar module and the Qorvo QM81026 smartphone chip, include this structure Compl. ¶105 Compl. ¶106 The complaint provides a micrograph of a chip allegedly containing the infringing structure Compl. ¶110

U.S. Patent No. 9,865,546 - "Contacts To Semiconductor Substrate And Methods Of Forming Same"

• Patent Identification: U.S. Patent No. 9,865,546, "Contacts To Semiconductor Substrate And Methods Of Forming Same", issued January 9, 2018 Compl. ¶58
• Technology Synopsis: This patent discloses a method for forming a robust electrical contact to a semiconductor substrate. The method involves creating a contact opening, depositing a liner layer, and causing a portion of that liner to diffuse into the substrate, forming an "intermix region." A refractory metal layer is then deposited over this intermix region before the contact is filled with metal, a process designed to create a stable, low-resistance interface. '546 Patent, abstract
• Asserted Claims: At least independent claim 1 Compl. ¶127
• Accused Features: The accused features are alleged to be present in Tower's SiGe, BiCMOS, and RF manufacturing processes Compl. ¶127 The complaint provides an SEM image of a device cross-section allegedly manufactured using the patented method Compl. ¶133

U.S. Patent No. 10,062,748 - "Segmented Guard-Ring and Chip Edge Seals"

• Patent Identification: U.S. Patent No. 10,062,748, "Segmented Guard-Ring and Chip Edge Seals", issued August 28, 2018 Compl. ¶61
• Technology Synopsis: This patent addresses reliability challenges in semiconductor devices that use porous low-k dielectric materials, which are susceptible to moisture damage. The invention is a structure that includes both a "guard ring" within the low-k dielectric to manage electrical fields and a separate "edge seal structure" that physically extends through the dielectric material to the substrate below. This combination is intended to seal the edge of the chip from moisture while allowing the guard ring to control electrical performance. '748 Patent, abstract
• Asserted Claims: At least independent claim 1 Compl. ¶152
• Accused Features: The complaint accuses devices manufactured using Tower's BCD processes, such as its TS18SOI process used in products like the Qorvo PAC22140, of infringing the '748 Patent Compl. ¶152 Compl. ¶153 An SEM image shows a guard ring structure alleged to be formed in a low-k dielectric material Compl. ¶158

U.S. Patent No. 10,707,167 - "Contacts To Semiconductor Substrate And Methods Of Forming Same"

• Patent Identification: U.S. Patent No. 10,707,167, "Contacts To Semiconductor Substrate And Methods Of Forming Same", issued July 7, 2020 Compl. ¶65
• Technology Synopsis: Related to the '546 patent, this patent claims the resulting semiconductor structure itself. The claimed contact includes an "intermix region" at the interface between the contact and the semiconductor substrate. This region's composition includes materials from the liner layer, a refractory metal layer, and the substrate, creating a physically and electrically robust connection. '167 Patent, abstract
• Asserted Claims: At least independent claim 1 Compl. ¶169
• Accused Features: The complaint alleges that devices made by Tower's SiGe, BiCMOS, and RF processes contain the claimed contact structure Compl. ¶169 A micrograph shows a cross-section of a semiconductor structure that allegedly includes a contact to a semiconductor substrate Compl. ¶173

III. The Accused Instrumentality

• Product Identification: The accused instrumentalities are semiconductor devices manufactured by Defendant Tower using its 180nm-65nm fabrication processes, including its BCD (e.g., TS18SOI), SiGe and BiCMOS (e.g., SBC18), and RF (e.g., 65nm) processes Compl. ¶23 Compl. ¶72
• Functionality and Market Context: These manufacturing processes are used to create chips for a variety of high-value markets Compl. ¶35 The complaint identifies several downstream products that allegedly incorporate these infringing devices to illustrate their function and market importance Compl. ¶24 These include the Qorvo PAC22140, a power management chip used in battery-operated tools Compl. ¶27; the DENSO DNSRR004, a 24-GHz radar sensor used in automotive safety systems like the Toyota Camry's blind spot monitor Compl. ¶¶29-31; and the Qorvo QM81026, an RF front-end module used in modern smartphones Compl. ¶¶32-33

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,330,235 Infringement Allegations

• Identified Points of Contention:
  • Evidentiary Question: The central dispute will likely be factual, turning on the accuracy and interpretation of the reverse engineering data presented. The question for the court will be whether the data reliably demonstrates that Tower's devices contain a nickel silicide layer with the specific platinum "composition gradient" and starting concentration (8-12 wt.%) required by Claim 1.
  • Scope Question: A potential issue may arise over the definition of "at the silicon interface." The parties may dispute the precise location and measurement methodology for determining the platinum weight percentage that satisfies this claim limitation.

U.S. Patent No. 8,507,983 Infringement Allegations

• Identified Points of Contention:
  • Scope Question: A primary point of contention may be the construction of the phrase "the channel is displaced from a first heavily doped region." The dispute will likely focus on what type and degree of physical or electrical separation is required to meet this limitation and whether the accused devices exhibit it.
  • Technical Question: A factual question will be whether the specific doped regions identified in Tower's devices through reverse engineering technically function as the "doped channel well" and "doped drift well" as those terms are understood in the context of the patent.

V. Key Claim Terms for Construction

U.S. Patent No. 8,330,235

• The Term: "composition gradient"
• Context and Importance: The infringement case for the '235 patent hinges on the existence and characteristics of this specific gradient. The construction of this term will determine whether the measured distribution of platinum in the accused devices meets the claim requirements. Practitioners may focus on this term because the patent's core novelty lies in this specific material property.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the gradient as the result of annealing two distinct layers with different platinum concentrations, which could support a construction that covers any resulting monotonic increase in platinum concentration, regardless of its specific mathematical profile '235 Patent, col. 5:1-10
  • Evidence for a Narrower Interpretation: Claim 1 itself qualifies the term by requiring the gradient to start "from between about 8 wt. % and about 12 wt. % at the silicon interface." This language may support a narrower construction where a gradient that starts outside this numerical range does not infringe.

U.S. Patent No. 8,507,983

• The Term: "the channel is displaced from a first heavily doped region"
• Context and Importance: This limitation defines the spatial relationship between the active channel and the source/drain contact region. The infringement analysis will depend on whether the accused device's structure satisfies this "displaced" arrangement. Practitioners may focus on this term because it is central to the self-aligned structure that distinguishes the invention.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term "displaced" is not explicitly defined and could be argued to mean any form of physical separation. The abstract simply states the channel is displaced from a heavily doped region, suggesting a general spatial relationship. '983 Patent, abstract
  • Evidence for a Narrower Interpretation: The patent's figures and detailed description show a specific embodiment where the channel is defined by the overlap of the gate with a channel well, and this channel is separated from the heavily doped source/drain region (146) by this overlap geometry. This could support a narrower construction requiring a specific structural cause for the displacement. '983 Patent, FIG. 1 '983 Patent, col. 4:51-61

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for all asserted patents, stating that Tower sells its semiconductor devices to customers (e.g., Qorvo, Denso) with the knowledge and intent that they will be imported and incorporated into products sold in the United States, thereby causing infringement Compl. ¶¶81-82 Compl. ¶¶98-99 Compl. ¶¶121-122 Compl. ¶¶146-147 Compl. ¶¶162-163 Compl. ¶¶188-189
• Willful Infringement: For all asserted patents, the complaint alleges that infringement is and will continue to be willful based on Defendant's knowledge of the patents acquired "through at least the filing and service of this complaint" Compl. ¶80 Compl. ¶97 Compl. ¶120 Compl. ¶145 Compl. ¶161 Compl. ¶187

VII. Analyst's Conclusion: Key Questions for the Case

• A central issue will be one of evidentiary proof: does the reverse engineering evidence presented by the Plaintiff definitively demonstrate that Tower's nanoscale semiconductor devices possess the specific material compositions and structural arrangements-such as the platinum "composition gradient" of the '235 patent or the gate-well overlap of the '983 patent-as required by the asserted claims?
• A key legal question will be one of definitional scope: how will the court construe critical claim limitations, such as "displaced from a first heavily doped region" ('983 patent)? The breadth or narrowness of these definitions will be pivotal in determining whether the physical structures of the accused devices fall within the scope of the patent claims.
• An overarching theme will be the link between process and product: the case will require a detailed technical analysis connecting Tower's accused manufacturing processes (e.g., BCD, SiGe, RF) to the final physical structures of the semiconductor devices they produce, and whether those structures embody the patented inventions.