GlobalFoundries US Inc v. Tower Semiconductor Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: GlobalFoundries U.S. Inc. (Delaware) and GlobalFoundries Singapore Pte. Ltd. (Singapore)
  • Defendant: Tower Semiconductor Ltd. (Israel), Tower Partners Semiconductor Co. Ltd. (Japan), Tower Semiconductor Italy S.r.l. (Italy), and multiple U.S.-based holding and operating subsidiaries (collectively "Tower")
  • Plaintiff's Counsel: Cleary Gottlieb Steen & Hamilton LLP; Jackson Walker LLP
• Case Identification: 7:26-cv-00108, W.D. Tex., 03/26/2026
• Venue Allegations: Venue is asserted based on Defendant Tower Semiconductor San Antonio Inc. having a regular and established place of business in the district (a fabrication facility known as "Tower Fab 9") where it allegedly commits acts of infringement. Venue for other domestic and foreign defendants is based on allegations of an integrated business enterprise, alter ego relationships, and acts of infringement committed within the district.
• Core Dispute: Plaintiff alleges that Defendant's semiconductor manufacturing processes-specifically its BCD, SiGe, BiCMOS, and RF processes-and the resulting semiconductor devices infringe five U.S. patents related to semiconductor structures and fabrication methods.
• Technical Context: The dispute is in the field of semiconductor fabrication, a highly complex and capital-intensive industry essential for producing integrated circuits for power management, radio frequency (RF), and automotive applications.
• Key Procedural History: The complaint notes that Plaintiff has filed separate lawsuits against Defendant in the Western District of Texas and the U.S. International Trade Commission, but asserts that those actions involve patents that are distinct from and unrelated to the patents-in-suit in this case.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 11,476,244 - "Laterally-Diffused Metal-Oxide-Semiconductor Devices for Electrostatic Discharge Protection Applications," issued October 18, 2022

The Invention Explained

• Problem Addressed: The patent's background section addresses the need to protect sensitive integrated circuits from electrostatic discharge (ESD) events. It notes that a specific type of protection device, a laterally-diffused metal-oxide-semiconductor (LDMOS) device, can have a trigger voltage that is too low for high-voltage applications, such as those in the automotive industry '244 Patent, col. 1:56-62
• The Patented Solution: The invention claims a specific LDMOS structure designed to improve ESD protection. The core of the solution is a specially placed "doped region" located beneath a source/drain region. This doped region is characterized by being "laterally spaced from the contact by a distance" and "fully positioned in a lateral direction between the gate electrode and the contact" '244 Patent, abstract '244 Patent, col. 2:7-10 This precise geometric arrangement, illustrated in the patent's figures, is intended to allow for tuning the device's electrical characteristics to meet the demands of high-voltage environments '244 Patent, FIG. 1
• Technical Importance: This design provides a way to engineer the trigger and holding voltages of on-chip ESD protection circuits, potentially making them more robust and suitable for automotive and other high-voltage applications without requiring a significant increase in the device's physical size '244 Patent, col. 6:11-40

Key Claims at a Glance

• The complaint asserts independent claim 1 Compl. ¶65
• The essential elements of claim 1 are:
  • a substrate;
  • a first source/drain region and a second source/drain region in the substrate;
  • a gate electrode over the substrate, laterally positioned between the source/drain regions;
  • an interconnect structure over the substrate with a contact connected to the first source/drain region; and
  • a doped region in the substrate beneath the first source/drain region, which has a side edge laterally spaced from the contact and is fully positioned laterally between the gate electrode and the contact.
• The complaint alleges infringement of "one or more claims," preserving the right to assert other claims Compl. ¶65

U.S. Patent No. 8,283,193 - "Integrated Circuit System With Sealring and Method of Manufacture Thereof," issued October 9, 2012

The Invention Explained

• Problem Addressed: The patent's background describes the function of a "sealring," a structure around the perimeter of a semiconductor die that protects the active circuitry from damage during the wafer dicing (singulation) process. A stated problem is that conventional wide metal sealrings are susceptible to electrical "arcing" during the reactive ion etching (RIE) step of manufacturing, which can damage the die and reduce production yield '193 Patent, col. 1:21-41
• The Patented Solution: The patent proposes a new sealring structure and manufacturing method to prevent this arcing. The solution involves forming the sealring's electrical contact "directly on and within planar extents of the insulator" of an insulation region that surrounds the chip. By landing the contact on an insulator rather than a conductive or semiconductive region, the invention claims to break the conductive path to the substrate that facilitates the damaging RIE arcing '193 Patent, abstract '193 Patent, col. 2:6-15
• Technical Importance: This invention purports to solve a key manufacturing yield problem by preventing a specific failure mode (RIE arcing) in sealring structures, thereby improving the reliability and cost-effectiveness of producing individual semiconductor chips from a wafer '193 Patent, col. 6:3-17

Key Claims at a Glance

• The complaint asserts independent claim 1, a method claim Compl. ¶84
• The essential steps of method claim 1 are:
  • forming an insulation region in a base layer;
  • filling an insulator in the insulation region around a perimeter of a main chip region;
  • forming a contact directly on and within planar extents of the insulator; and
  • forming at least one sealring with an upper layer over an active portion and the contact, such that the sealring surrounds and isolates an active surface area.
• The complaint reserves the right to assert other claims by alleging infringement of "one or more claims" Compl. ¶84

U.S. Patent No. 11,658,177 - "Semiconductor Device Structures With a Substrate Biasing Scheme," issued May 23, 2023

• Technology Synopsis: The patent addresses the technical challenge of high capacitance and electrical leakage in transistors built on standard bulk semiconductor substrates '177 Patent, col. 1:12-17 The patented solution involves forming an "isolation layer" of polycrystalline semiconductor material beneath the transistor's active body and applying a negative bias voltage to the substrate contact. This configuration is intended to electrically isolate the transistor from the bulk substrate, mimicking the performance benefits of more expensive Silicon-on-Insulator (SOI) substrates without incurring the same cost '177 Patent, abstract '177 Patent, col. 4:9-14
• Asserted Claims: The complaint asserts at least claim 7, a method claim Compl. ¶106
• Accused Features: The complaint accuses Tower's RF processes, including its 65nm RF process and processes run on SOI wafers, of infringing the '177 Patent. Specific accused products include the Qorvo QM81026 and QM81032 chips used in smartphones (Compl. ¶106; Compl. ¶107).

U.S. Patent No. 7,566,653 - "Interconnect Structure With Grain Growth Promotion Layer and Method for Forming the Same," issued July 28, 2009

• Technology Synopsis: This patent addresses a performance bottleneck in modern integrated circuits caused by the shrinking size of copper interconnects. As interconnects shrink, the copper grains tend to be smaller, which increases electrical resistance '653 Patent, col. 1:11-20 The invention proposes inserting a "grain growth promotion layer" (e.g., made of Ruthenium) between the traditional diffusion barrier layer and the copper seed layer. This additional layer is claimed to facilitate the growth of larger copper grains during the annealing process, thereby lowering resistance and improving the interconnect's reliability and performance '653 Patent, abstract '653 Patent, col. 2:7-14
• Asserted Claims: The complaint asserts at least claim 1, a structure claim Compl. ¶123
• Accused Features: The complaint accuses Tower's RF processes, including its 65nm RF process. The Qorvo QM81026 and QM81032 chips are identified as products embodying the accused structures Compl. ¶¶123-124

U.S. Patent No. 9,269,666 - "Methods for Selective Reverse Mask Planarization and Interconnect Structures Formed Thereby," issued February 23, 2016

• Technology Synopsis: The patent addresses a fabrication challenge known as planarization-creating a flat surface over complex topography, particularly tall metal features in an interconnect structure '666 Patent, col. 1:8-14 The patented method uses a multi-step "selective reverse mask planarization" process. A key feature is the use of an etch stop layer on top of a conductive feature, followed by the deposition of multiple dielectric layers that are selectively etched and polished. This approach is designed to achieve a high degree of planarity over tall, dense features, which is difficult with conventional chemical mechanical polishing (CMP) alone '666 Patent, abstract '666 Patent, col. 2:44-51
• Asserted Claims: The complaint asserts at least claim 1, a structure claim Compl. ¶140
• Accused Features: The complaint accuses Tower's BCD processes, including its TS18SOI process, of creating structures that infringe the '666 Patent. The PA22BZ die within the Qorvo PAC22140 power management chip is identified as an accused product Compl. ¶¶140-141

III. The Accused Instrumentality

Product Identification

• The complaint accuses several of Tower's semiconductor manufacturing processes, identified as its 180nm-65nm BCD (including TS18SOI), SiGe and BiCMOS (including SBC18), and RF processes Compl. ¶23

Functionality and Market Context

• These are foundry process technologies that Tower uses to manufacture semiconductor wafers and integrated circuits for its customers Compl. ¶23 Compl. ¶35 The complaint alleges that these processes are used to create commercially significant products that are incorporated into high-volume consumer and industrial goods. Specific examples cited include:
  • The Qorvo PAC22140, a power management chip allegedly made using Tower's BCD process and incorporated into battery-operated tools Compl. ¶27 Compl. ¶28
  • The DENSO DNSRR004, a radar sensor chip allegedly made using Tower's SiGe/BiCMOS process and incorporated into the Toyota Blind Spot Monitor system used in vehicles like the Toyota Camry Compl. ¶29 Compl. ¶31 An image of the circuit board from the monitor shows a close-up of the accused die Compl. p. 13
  • The Qorvo QM81026, an RF chip allegedly made using Tower's 65nm RF process and incorporated into modern smartphones Compl. ¶32 The complaint provides an image of this chip Compl. p. 14

IV. Analysis of Infringement Allegations

'244 Patent Infringement Allegations

Identified Points of Contention

• Scope Questions: A central question for the infringement analysis of the '244 Patent may be the construction of the phrase "fully positioned in a lateral direction between the gate electrode and the contact." The dispute could turn on whether the accused device's doped region satisfies this precise geometric limitation, which may require detailed analysis of dopant profiles beyond what is visible in the provided SEM images.
• Technical Questions: What evidence will be required to prove the exact boundaries of the "doped region" in the accused devices? The complaint's allegations are supported by SEM and Scanning Capacitance Microscopy (SCM) images, but the ultimate determination may depend on more sophisticated reverse engineering and process analysis to confirm the dopant concentrations and lateral extents.

'193 Patent Infringement Allegations

Identified Points of Contention

• Scope Questions: The construction of "directly on" will be critical. This term frequently raises questions of whether any intervening, even if very thin, adhesion or barrier layers are permissible. The case may turn on whether Tower's manufacturing process results in a structure that meets a strict definition of direct physical contact between the contact and the insulator.
• Technical Questions: As this is a method claim, a key question is what evidence demonstrates that Tower actually performs these steps. The complaint relies on images of the final product structure. Proving infringement may require evidence linking the final structure back to the specific manufacturing steps recited in the claim.

V. Key Claim Terms for Construction

For the '244 Patent:

• The Term: "fully positioned in a lateral direction between the gate electrode and the contact"
• Context and Importance: This term defines the core geometric innovation of the asserted structure claim. The infringement analysis will depend entirely on whether the physical layout of the accused device's doped region falls within the scope of this limitation.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party might argue that the claim language only requires the entire lateral extent of the doped region to fall within the vertical planes defined by the innermost edges of the gate and the contact, without requiring any specific margin or clearance '244 Patent, claim 1
  • Evidence for a Narrower Interpretation: A party could argue that the term, when read in light of the patent's goal of tuning electrical properties for ESD, implies a more constrained configuration. The patent's drawings show the doped region (26) as being distinctly separate from and not underlying either the gate electrode (40) or the contact (46), which may be used to argue for a narrower construction that requires clear spacing from both '244 Patent, FIG. 1 '244 Patent, col. 6:8-20

For the '193 Patent:

• The Term: "forming a contact directly on... the insulator"
• Context and Importance: This step is presented as the key to solving the RIE arcing problem. Whether the accused method practices this step is central to the infringement allegation. The term "directly on" is a common point of dispute in patent litigation.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification states, "The contact 218 can be formed directly on and within planar extents of the insulator 214" '193 Patent, col. 4:26-28 A party may argue this means no functionally significant or different material layer is interposed.
  • Evidence for a Narrower Interpretation: A party could argue that "directly on" requires immediate and contiguous physical contact, and that if standard manufacturing processes leave behind any thin, non-insulating residue or an adhesion layer, the claim limitation is not met. The stated purpose is to break a conductive path, so any interpretation that allows an intervening conductive layer would be inconsistent with the invention's objective '193 Patent, col. 6:3-17

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement for all five patents-in-suit. The allegations are based on Tower manufacturing and selling semiconductor wafers and dies to customers (e.g., Qorvo, Denso) with the knowledge and intent that these components will be incorporated into end-products (e.g., smartphones, automotive sensors) that are imported, sold, and used in the United States. The complaint asserts these components are a material part of the inventions and not staple articles of commerce Compl. ¶¶77-80 Compl. ¶¶100-102 Compl. ¶¶116-119 Compl. ¶¶133-136 Compl. ¶¶151-154
• Willful Infringement: For each asserted patent, the complaint alleges that the defendants' infringement is willful based on having knowledge of the patents and their infringement "through at least the filing and service of this complaint." This forms a basis for post-suit willfulness allegations Compl. ¶76 Compl. ¶99 Compl. ¶115 Compl. ¶132 Compl. ¶150

VII. Analyst's Conclusion: Key Questions for the Case

• A central issue will be one of structural and procedural interpretation: For the product claims (e.g., in the '244, '653, and '666 patents), does reverse engineering of the accused chips confirm they meet the precise geometric and material limitations required? For the method claims (e.g., in the '193 and '177 patents), what evidence will be presented to prove that the final chip structures were necessarily created by performing the specific, ordered steps recited in the claims?
• A key evidentiary question will be one of technical proof: The complaint's infringement theories rely heavily on the interpretation of SEM and other microscopy images. The case will likely depend on whether discovery and expert analysis can definitively establish the exact material compositions, dopant profiles, and three-dimensional layouts of nano-scale features in the accused devices to the satisfaction of the court.
• A significant procedural question may concern integrated enterprise liability: Given the complex, multi-national corporate structure of the defendants, a threshold issue may be whether the plaintiff can successfully prove that the various U.S. and foreign entities operate as a single, integrated enterprise, making the actions of one attributable to all for purposes of establishing liability, venue, and damages.