DCT
7:26-cv-00105
ExactoJoin LLC v. IBM Corp
Key Events
Complaint
Table of Contents
complaint Intelligence
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: ExactoJoin LLC (New Mexico)
- Defendant: International Business Machines Corporation (New York)
- Plaintiff's Counsel: Rabicoff Law LLC
- Case Identification: 7:26-cv-00105, W.D. Tex., 03/24/2026
- Venue Allegations: Venue is alleged to be proper in the Western District of Texas because the Defendant maintains an established place of business in the District and has allegedly committed acts of patent infringement there.
- Core Dispute: Plaintiff alleges that Defendant's IBM Utility Node server products, which contain certain semiconductor memory components, infringe a patent related to compact semiconductor memory device architecture.
- Technical Context: The technology concerns methods of designing semiconductor memory devices, such as those used in Solid-State Drives (SSDs), to increase storage density by reducing the number of electrical contacts required to access the memory cells.
- Key Procedural History: The complaint is the initial pleading in this matter. The patent-in-suit is a continuation of a series of prior applications, indicating a large and established patent family relating to this technology.
Case Timeline
| Date | Event |
|---|---|
| 2007-11-29 | '581 Patent Priority Date |
| 2014-02-11 | '581 Patent Application Filing Date |
| 2015-04-07 | '581 Patent Issue Date |
| 2026-01-07 | Accused Product Documentation Date |
| 2026-03-24 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
Patent Identification: U.S. Patent No. 9,001,581, "Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making," issued April 7, 2015.
The Invention Explained:
- Problem Addressed: The patent's background section describes a "continuing need for semiconductor memory devices that are smaller in size than currently existing devices" '581 Patent, col. 2:11-13 It notes that conventional memory like DRAM is difficult to scale down due to the physical space required by capacitors '581 Patent, col. 1:62-67
- The Patented Solution: The invention claims to solve this problem by proposing a memory architecture where multiple memory cells are connected in a "string" or "link" but share a reduced number of electrical contacts '581 Patent, abstract The patent states that "the number of contacts is the same as or less than the number of the memory cells" '581 Patent, col. 2:26-27, with specific embodiments disclosing that intermediate cells in a string are "contactless" '581 Patent, col. 17:25-26 This structure aims to reduce the overall area required for the memory array, allowing for higher density.
- Technical Importance: This approach addresses a fundamental bottleneck in semiconductor scaling by minimizing the silicon area consumed by electrical contacts, which do not scale as easily as transistors.
Key Claims at a Glance:
- The complaint asserts independent Claim 1 of the '581 Patent Compl. ¶11 Compl. Ex. 2, p. 2
- The essential elements of independent Claim 1 are:
- A semiconductor memory device comprising: a plurality of semiconductor memory cells;
- at least one contact configured to electrically connect said memory cells to at least one control line, wherein the number of said contacts is less than the number of said memory cells; and
- said memory device being configured to perform at least one of: injecting charge into or extracting charge out of a portion of at least one of said memory cells to maintain a state of said at least one memory cell.
- The complaint notes that Plaintiff may assert infringement of other claims, including dependent claims Compl. ¶11
III. The Accused Instrumentality
Product Identification: The complaint identifies the "IBM Utility Node" as an exemplary accused product Compl. Ex. 2, p. 2
Functionality and Market Context:
- The complaint alleges that the IBM Utility Node is a "General purpose, multifunctional x86 server" Compl. Ex. 2, p. 3 The allegedly infringing component is the server's boot drive, which is identified as a "Micron 7450 SSD (semiconductor memory) boot drive based on Micron 3D NAND Flash chips" Compl. Ex. 2, p. 2
- The infringement allegations focus on the internal architecture of this SSD, specifically its use of Triple-Level Cell (TLC) 3D NAND Flash memory, which stores data by trapping charge in semiconductor memory cells Compl. Ex. 2, pp. 5-8 Compl. Ex. 2, p. 14 A screenshot in the complaint's exhibit lists the "IBM Utility Node" as a supported configuration for certain IBM software Compl. Ex. 2, p. 2
IV. Analysis of Infringement Allegations
'581 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A semiconductor memory device comprising: a plurality of semiconductor memory cells; | The accused IBM Utility Node product contains a Micron 7450 SSD boot drive, which is a semiconductor memory device. This SSD is based on Micron 3D NAND Flash chips that contain a plurality of TLC (Triple-Level Cell) semiconductor memory cells (Compl. Ex. 2, pp. 2-8). A provided screenshot from IBM's website shows documentation for "Preparing a Utility Node" | ¶16 | col. 1:52-56 |
| at least one contact configured to electrically connect said memory cells to at least one control line, wherein the number of said contacts is less than the number of said memory cells; | In the accused SSD, a string of multiple TLC memory cells is connected to a single bit line (the "control line") via a single bit line contact (the "contact"). The complaint alleges that because one contact serves a large number of cells in the string, the number of contacts is less than the number of memory cells. An annotated SEM cross-section of a 3D-NAND stack is provided to identify the "contact," "control line," and "memory cells" | ¶16 | col. 2:27-29 |
| and said memory device being configured to perform at least one of: injecting charge into or extracting charge out of a portion of at least one of said memory cells to maintain a state of said at least one memory cell. | The accused SSD's Micron 3D NAND Flash chips use a non-conductive charge trap layer to store data. The complaint alleges that electrons are injected into this layer, which is a portion of the TLC memory cell, to program the cell and maintain its state (Compl. Ex. 2, pp. 12-15). A diagram of a "Charge trap cell" illustrates the process of programming and erasing the cell by injecting and removing charge | ¶16 | col. 15:9-24 |
- Identified Points of Contention:
- Scope Question: A potential dispute may arise over whether the technology described in the '581 Patent, which focuses heavily on memory cells with an electrically "floating body" region, can be construed to cover the accused "charge trap" technology used in modern 3D NAND flash memory. The patent's abstract, for instance, specifies that "each memory cell includes a floating body region for storing data" '581 Patent, abstract, which may raise the question of whether charge-trap cells fall within the patent's scope.
- Technical Question: The infringement theory maps the patent's concept of a "string" of cells onto the vertical architecture of a 3D NAND device. A technical question for the court may be whether the structure of a modern 3D NAND string and its connection to a bit line is technically and structurally the same as the "string" with a reduced number of "contacts" as contemplated and claimed by the '581 Patent, particularly as depicted in the patent's own figures (e.g.,'581 Patent, Fig. 16A).
V. Key Claim Terms for Construction
The Term: "semiconductor memory cell"
- Context and Importance: This term's definition is critical because the patent's specification extensively describes embodiments using "floating body" transistors, often on a Silicon-on-Insulator (SOI) substrate '581 Patent, col. 1:50-53 '581 Patent, col. 11:29-35, while the accused product is a 3D NAND flash device using charge-trap cells Compl. Ex. 2, p. 15 The outcome of the case may depend on whether this term is construed broadly to cover any semiconductor data storage element or is limited to the floating-body type primarily discussed.
- Intrinsic Evidence for a Broader Interpretation: The claim language itself does not specify the type of memory cell, which may support a broader reading that is not limited to the examples in the specification.
- Intrinsic Evidence for a Narrower Interpretation: The patent's abstract explicitly states that "each memory cell includes a floating body region for storing data" '581 Patent, abstract This, combined with numerous embodiments describing floating body operation '581 Patent, col. 12:1-12 '581 Patent, col. 15:11-24, may be used to argue for a narrower construction limited to that technology.
The Term: "contact"
- Context and Importance: The novelty of the patent rests on having fewer "contacts" than memory cells. The complaint alleges the bit line contact in the accused SSD is the claimed "contact" Compl. Ex. 2, p. 9 The construction of this term will determine if the architecture of the accused 3D NAND device meets this key limitation.
- Intrinsic Evidence for a Broader Interpretation: The term is not explicitly defined, and its plain meaning could encompass any structure that electrically connects the memory cells to a control line.
- Intrinsic Evidence for a Narrower Interpretation: The patent's figures, such as Figure 16A, depict "contacts" (71, 73) as discrete structures at the ends of a planar string of transistors '581 Patent, Fig. 16A This may support an argument that the term is limited to such end-point connections in a planar array and does not read on the different physical arrangement of a vertical 3D NAND string's connection to a bit line.
VI. Other Allegations
- Indirect Infringement: The complaint alleges induced infringement occurring "at least since being served by this Complaint" Compl. ¶15 The basis for this allegation is that Defendant distributes "product literature and website materials" that allegedly instruct end users on how to use the accused products in a manner that infringes the '581 Patent Compl. ¶14
- Willful Infringement: The complaint alleges that Defendant has actual knowledge of its infringement from the service of the complaint and has continued its allegedly infringing activities despite this knowledge Compl. ¶¶13-14 This forms the basis for a claim of post-filing willful infringement, for which Plaintiff seeks enhanced damages Compl. Prayer D The complaint does not allege pre-suit knowledge.
VII. Analyst's Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: can the term "semiconductor memory cell," described extensively in the patent's specification in the context of floating-body transistors, be construed to cover the distinct "charge trap" technology used in the accused 3D NAND SSD? The case may turn on whether the specification's detailed examples limit the scope of the broader claim language.
- A central evidentiary question will be one of structural correspondence: does the vertical architecture of a modern 3D NAND string, as found in the accused SSD, align with the claimed structure of a memory device having fewer "contacts" than "memory cells," as that concept is taught and envisioned in the '581 Patent? This will require a detailed technical comparison between the accused device's structure and the patent's claims and descriptions.
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