Signal LLP v. NXP USA Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Signal, LLP (Nevada)
  • Defendant: NXP USA, Inc. (Delaware)
  • Plaintiff's Counsel: Nelson Bumgardner Conroy PC
• Case Identification: 7:26-cv-00095, W.D. Tex., 06/16/2026
• Venue Allegations: Venue is alleged to be proper based on Defendant NXP USA, Inc. having regular and established places of business within the Western District of Texas, including its U.S. corporate headquarters and manufacturing facilities in Austin, Texas, where acts of infringement are alleged to have occurred.
• Core Dispute: Plaintiff alleges that Defendant's microcontrollers, microprocessors, and systems-on-chip that include memory controllers infringe six patents related to on-die termination and signal timing for high-speed memory interfaces.
• Technical Context: The technology at issue involves methods for improving signal integrity in high-speed memory systems, such as those using DDR SDRAM, which is fundamental to the performance and reliability of modern computing and electronic devices.
• Key Procedural History: The complaint alleges that Plaintiff's predecessor-in-interest, Rambus, Inc., had a patent license agreement with Defendant's predecessor, Freescale Semiconductor, which expired in March 2018. Following the expiration, Rambus allegedly provided Defendant NXP with notices of infringement in May and August of 2018. The patents were assigned to Plaintiff Signal, LLP in September 2025, and an original complaint was filed in March 2026.

Case Timeline

Date	Event
2005-10-17	Earliest Priority Date for '637 Patent
2006-06-02	Earliest Priority Date for '459, '902, and '400 Patents
2006-12-21	Earliest Priority Date for '962 and '129 Patents
2011-01-01	Rambus and Freescale enter Patent License Agreement (PLA)
2013-12-17	'459 Patent Issued
2014-01-28	'637 Patent Issued
2015-02-03	'962 Patent Issued
2015-12-01	Freescale and NXP Semiconductors complete merger
2017-02-14	'129 Patent Issued
2018-03-31	Freescale PLA term expires
2018-05-22	Rambus sends first notice of infringement to NXP
2018-08-21	'902 Patent Issued
2018-08-31	Rambus sends second notice of infringement to NXP
2021-03-09	'400 Patent Issued
2025-09-29	Asserted Patents assigned from Rambus to Signal, LLP
2026-03-16	Original Complaint filed
2026-04-10	Signal sends supplemental notice letter to NXP
2026-06-16	Amended Complaint filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,610,459 - "Controlling on-die termination in a dynamic random access memory device"

Issued December 17, 2013

The Invention Explained

• Problem Addressed: In memory systems with multiple memory modules on a shared bus, high-speed signals can reflect off the un-addressed modules (stubs), causing interference that degrades signal integrity Compl. ¶40 '459 Patent, col. 1:55-2:8 Conventional on-die termination (ODT) schemes that simply turn termination off for the active module can create an impedance mismatch, while leaving it on can unduly attenuate the signal '459 Patent, col. 2:40-50
• The Patented Solution: The invention proposes a "graduated" termination scheme where memory devices contain multiple, selectable termination structures with different impedance values '459 Patent, col. 3:10-15 When performing a write operation, the non-selected module applies a "hard" (low-impedance) termination to match the bus and absorb reflections, while the selected module applies a "soft" (higher-impedance) termination that reduces reflections without excessively weakening the incoming data signal '459 Patent, abstract '459 Patent, col. 3:25-40 Figure 2 of the patent illustrates a system where a memory controller directs two different memory modules to apply distinct termination values (R1 vs. R2) based on which module is being written to '459 Patent, Fig. 2
• Technical Importance: This method allows for more precise management of signal integrity in high-speed, multi-drop memory systems, enabling higher data rates and greater reliability '459 Patent, col. 5:35-40

Key Claims at a Glance

• The complaint asserts at least independent Claim 1 Compl. ¶60
• Claim 1 of the '459 Patent breaks down into these essential elements:
  • An integrated circuit device for controlling a DRAM.
  • A first interface to transmit a write command to the DRAM.
  • A second interface to transmit write data to the DRAM.
  • The device sets a first control value for a first termination and a second control value for a second, different termination.
  • It transmits a termination control signal that causes the DRAM to apply the first termination during a first time interval (while receiving write data) and the second termination during a second time interval (after data is received).
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 10,056,902 - "On-die termination control"

Issued August 21, 2018

The Invention Explained

• Problem Addressed: As with the '459 Patent, the technology addresses signal integrity degradation from impedance mismatches and reflections in high-speed memory systems '902 Patent, col. 1:55-2:8
• The Patented Solution: The invention describes a memory controller that transmits a series of distinct commands to a DRAM to manage its ODT state. The controller sends a command to specify storage of a "digital control value" indicating the termination impedance the DRAM should use; it separately sends a "chip-select signal" to enable the DRAM to respond; and it sends a "write command" to initiate the data transfer '902 Patent, abstract '902 Patent, col. 15:41-16:2 This allows the controller to programmatically set the termination impedance for an upcoming operation before that operation begins.
• Technical Importance: This provides a specific protocol for a memory controller to dynamically and preemptively configure the on-die termination characteristics of a DRAM device, enabling more sophisticated and flexible signal integrity management in complex systems '902 Patent, col. 10:20-33

Key Claims at a Glance

• The complaint asserts at least independent Claim 1 Compl. ¶72
• Claim 1 of the '902 Patent breaks down into these essential elements:
  • An integrated circuit device for controlling a DRAM.
  • A first interface to transmit one or more commands specifying a digital control value for termination impedance to be stored in a DRAM register, a write command, and a chip-select signal.
  • A second interface to transmit write data.
  • The DRAM is caused to couple the specified termination impedance to its data interface in response to the chip-select and write command.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

Multi-Patent Capsules

• U.S. Patent No. 10,944,400, "On-die termination control," issued March 9, 2021

  • Technology Synopsis: Belonging to the same family as the '459 and '902 patents, the '400 Patent describes a memory control component that manages on-die termination in a memory IC by asserting a control signal to apply a first termination impedance during a write operation and a second impedance after '400 Patent, abstract This allows for graduated termination to optimize signal integrity.
  • Asserted Claims: At least Claim 1 Compl. ¶84
  • Accused Features: The memory controller functionality within NXP's products is accused of infringing by implementing this graduated ODT control scheme Compl. ¶83; Compl. ¶84

• U.S. Patent No. 8,947,962, "On-die termination of address and command signals," issued February 3, 2015

  • Technology Synopsis: This patent addresses signal integrity on the address and command (RQ) bus, which is shared across multiple memory devices '962 Patent, abstract The invention is a memory controller that can selectively enable or disable ODT circuitry for the RQ bus lines on one or more memory devices, allowing for dynamic control of termination to reduce power and manage signal reflections '962 Patent, col. 2:22-32
  • Asserted Claims: At least Claim 1 Compl. ¶96
  • Accused Features: The accused NXP memory controllers are alleged to infringe by implementing this selective ODT control for address and command signal lines Compl. ¶95; Compl. ¶96

• U.S. Patent No. 9,570,129, "On-die termination of address and command signals," issued February 14, 2017

  • Technology Synopsis: Continuing the technology of the '962 patent, the '129 patent describes a memory system where different memory devices in a fly-by topology have different ODT values stored in control registers '129 Patent, abstract This allows a memory controller to apply different termination schemes to different devices on the shared RQ bus, providing fine-grained control over signal integrity based on system topology.
  • Asserted Claims: At least Claim 1 Compl. ¶108
  • Accused Features: NXP's memory controllers are accused of infringing by having the capability to manage these different ODT values across various memory devices Compl. ¶107; Compl. ¶108

• U.S. Patent No. 8,638,637, "Memory controller with staggered request signal output," issued January 28, 2014

  • Technology Synopsis: This patent addresses timing skew between different signal groups (e.g., control signals vs. address/command signals) that arises from unequal loading on their respective buses '637 Patent, col. 1:44-54 The invention is a memory controller that staggers the launch times of these signal groups-launching signals on more heavily loaded lines earlier-to ensure they arrive at the memory device simultaneously, thereby improving the timing margin '637 Patent, abstract
  • Asserted Claims: At least Claim 1 Compl. ¶120
  • Accused Features: The timing control circuitry within NXP's memory controllers is accused of infringing by implementing this staggered signal output functionality Compl. ¶119; Compl. ¶120

III. The Accused Instrumentality

Product Identification

The complaint accuses a wide range of NXP products that "incorporate a memory controller integrated circuit device" Compl. ¶47 These include, but are not limited to, various series of NXP's microcontrollers (MCUs), microprocessors (MPUs), and Systems-on-Chip (SoCs), such as the i.MX, LS, BSC, P-series, and S32 families Compl. ¶55

Functionality and Market Context

The accused products are semiconductor devices that serve as the central processing units or specialized controllers in a vast array of electronic systems. A core function of these devices is to manage communication with external Synchronous Dynamic Random-Access Memory (SDRAM) Compl. ¶47 The complaint alleges these controllers are designed to be compliant with industry standards from JEDEC for various generations of DDR memory (e.g., DDR3, LPDDR4, LPDDR5), and that this compliance necessitates the inclusion of the infringing functionality Compl. ¶¶48-49 The complaint includes a diagram illustrating the corporate structure of NXP, showing Defendant NXP USA, Inc. as a U.S.-based subsidiary of Netherlands-based NXP Semiconductors N.V. Compl. p. 6

IV. Analysis of Infringement Allegations

The complaint references infringement claim charts in Exhibits 1 through 6, but these exhibits were not attached to the publicly filed document. Per the instructions, the narrative infringement theory is summarized below in prose, and no claim chart table is provided.

• Summary of Allegations (Applicable to All Asserted Patents):
  The complaint's central infringement theory is that the accused NXP products, which are memory controller ICs, are themselves the infringing devices Compl. ¶59 Compl. ¶71 Compl. ¶83 Compl. ¶95 Compl. ¶107 Compl. ¶119 It alleges that the products are designed to operate with JEDEC-compliant SDRAM and that their own internal "structure and configuration" satisfy every limitation of the asserted claims Compl. ¶49 Compl. ¶59 This argument preempts a potential defense that infringement only occurs when the NXP controller is combined with a separate memory chip from another manufacturer. The complaint asserts that NXP directly infringes by making, using, and selling these controllers in the United States Compl. ¶61 Compl. ¶73

• Identified Points of Contention:

  • Claim Scope and Divided Infringement: For the ODT-related patents ('459, '902, '400, '962, '129), a primary legal dispute may concern the boundaries of the claimed "device." The court will have to determine whether the asserted claims are met by the NXP controller IC alone, as Plaintiff alleges Compl. ¶59, or if infringement requires the active participation of a separate DRAM chip. If the latter is true, it raises the possibility of a divided infringement defense, where no single entity performs all steps of the claimed method.
  • Technical Mismatch: For the '637 patent, the dispute may center on the technical operation of NXP's controllers. The key question will be whether the timing compensation methods used in the accused products fall within the scope of the claim term "staggered request signal output." This suggests a potential dispute over whether NXP's implementation is functionally and structurally equivalent to the specific mechanism disclosed in the patent.

V. Key Claim Terms for Construction

• Term ('459 Patent): "soft termination"

  • Context and Importance: The distinction between "soft" and "hard" termination is the crux of the '459 patent's "graduated" ODT scheme. The construction of this term will be critical for determining whether the accused devices' termination capabilities meet this limitation. Practitioners may focus on this term because it is a relative term defined by its function and relationship to "hard termination."
  • Intrinsic Evidence for a Broader Interpretation: The specification describes it as a "relatively low-load termination" '459 Patent, col. 3:34-35 This language may support an interpretation covering a wide range of impedance values that are simply higher than the corresponding "hard" termination value.
  • Intrinsic Evidence for a Narrower Interpretation: The specification also defines the term by its purpose: "to provide a desired level of energy absorption... without unduly attenuating the incoming signals" '459 Patent, col. 3:37-40 This functional language may support a narrower construction that requires the termination to achieve this specific technical balance, not just have a relatively higher impedance.

• Term ('902 Patent): "integrated circuit device for controlling a dynamic random access memory device (DRAM)"

  • Context and Importance: This preamble term is central to identifying the infringing article and will be a focal point for any divided infringement arguments. Its construction determines whether the NXP controller alone can infringe, or if infringement only occurs in a larger system.
  • Intrinsic Evidence for a Broader Interpretation: The body of the claims recites actions the device performs on a DRAM (e.g., "transmitting to the DRAM") '902 Patent, claim 1 This phrasing, combined with the complaint's assertion that the "Accused Product is itself that device" Compl. ¶71, may support a construction where the controller IC, designed for this purpose, is the complete infringing device.
  • Intrinsic Evidence for a Narrower Interpretation: The claim language describes an interactive system. This may support an argument that the "device" does not meet all limitations until it is actively "controlling a... DRAM," thereby implicating other components or actors and potentially placing the infringement outside the sole control of NXP.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for all asserted patents. The basis for inducement is NXP's alleged actions of "creating and disseminating advertisements and instructive materials," including technical documentation, manuals, training videos, and online support forums, that allegedly promote and instruct customers and integrators on how to use the accused products in an infringing manner Compl. ¶64 Compl. ¶76 Compl. ¶88 Compl. ¶100 Compl. ¶112 Compl. ¶124
• Willful Infringement: Willfulness is alleged for all asserted patents. The claims are based on extensive alleged pre-suit knowledge, including: a prior license between the parties' predecessors covering the patent families that expired in March 2018 Compl. ¶¶5, 8; specific written notices of infringement sent by Plaintiff's predecessor in May and August 2018 Compl. ¶¶9-10; and the filing of the original complaint in March 2026 Compl. ¶15 The complaint alleges that NXP's continued infringement despite this "detailed, ongoing knowledge" constitutes willful, deliberate, and egregious conduct Compl. ¶18

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope and liability: For the five patents related to on-die termination, the case may turn on whether the accused NXP controller ICs are themselves the complete infringing "device," as the plaintiff contends. This raises a fundamental question for claim construction and divided infringement doctrine: can a component be liable for infringement when the full claimed functionality is only realized in a system with other components?
• A second key issue will be evidentiary and technical: For the '637 patent on signal timing, the dispute will likely focus on whether NXP's internal timing compensation mechanisms are technically equivalent to the claimed "staggered request signal output." This will require a deep dive into the specific circuit-level operation of the accused products.
• Finally, a central question for damages will be willfulness: Given the alleged history of a prior license agreement and multiple, specific pre-suit infringement notices, the court will need to examine NXP's state of mind and the objective reasonableness of its decision to continue its conduct after the license expired. A finding of willfulness could expose the defendant to the possibility of enhanced damages.