Signal LLP v. NXP USA Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Signal, LLP (Nevada)
  • Defendant: NXP USA, Inc. (Delaware)
  • Plaintiff's Counsel: Nelson Bumgardner Conroy PC; The Law Offices of David A. Gerasimow, P.C.
• Case Identification: 7:26-cv-00095, W.D. Tex., 03/16/2026
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant maintains a regular and established place of business in the District, including its U.S. Corporate Headquarters and wafer fabrication facilities in Austin, Texas.
• Core Dispute: Plaintiff alleges that Defendant's semiconductor products that incorporate memory controllers supporting Double Data Rate (DDR) standards infringe five patents related to high-speed memory signaling, including on-die termination and signal timing.
• Technical Context: The technology at issue addresses signal integrity and timing in high-speed memory interfaces, which are fundamental to the performance of modern computing devices, from servers to mobile electronics.
• Key Procedural History: The complaint details a prior relationship between the parties' predecessors-in-interest. Rambus, Inc. (Plaintiff's predecessor) licensed the asserted patent families to Freescale Semiconductor (Defendant's predecessor) in an agreement that ran from 2011 until its expiration on March 31, 2018. Following the expiration, Rambus allegedly sent NXP notices of infringement in May and August of 2018. The patents were assigned from Rambus to Signal, LLP on September 29, 2025.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 10,944,400 - "On-die termination control"

(Issued Mar. 9, 2021)

The Invention Explained

• Problem Addressed: In high-speed memory systems with multiple memory modules connected to a shared data path, signals sent to one module can create undesirable reflections from the connection stubs leading to other, non-selected modules U.S. Patent No. 10,056,902, col. 1:53-2:6 Simultaneously, applying a standard termination resistor to the selected module can unduly weaken or attenuate the incoming signal, reducing the signaling margin and increasing the risk of errors '902 Patent, col. 2:41-50
• The Patented Solution: The patent describes a system of "graduated" on-die termination (ODT) to manage signal integrity. When a memory controller writes data to a selected memory module, it can signal the non-selected module to apply a "hard" termination (a low impedance value) to its data lines to absorb reflections '902 Patent, col. 3:28-34 Concurrently, the selected module can apply a "soft" termination (a higher impedance value) or no termination, which provides some energy absorption without excessively attenuating the data signal it is intended to receive '902 Patent, col. 3:34-42 This dual-state termination scheme aims to optimize signal integrity across the entire memory bus during write operations.
• Technical Importance: This approach allows for improved signaling margins in high-speed, multi-module memory systems, enabling faster and more reliable data transfer by actively managing signal reflections and attenuation.

Key Claims at a Glance

• The complaint asserts at least independent Claim 1 Compl. ¶48
• Claim 1 (Integrated circuit device):
  • A first signaling interface to be coupled to a DRAM, which has a first register and a second register.
  • Control circuitry to transmit commands to the DRAM via the interface.
  • The commands instruct the DRAM to store a first control value in the first register, specifying a first termination to be applied during a write-data reception interval.
  • The commands also instruct the DRAM to store a second control value in the second register, specifying a second termination to be applied after the write-data reception interval transpires.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,947,962 - "On-die termination of address and command signals"

(Issued Feb. 3, 2015)

The Invention Explained

• Problem Addressed: Similar to data lines, the address and command (RQ) bus in a memory system is also susceptible to signal integrity issues, especially in "fly-by" topologies where signal lines connect to multiple memory devices in sequence U.S. Patent No. 8,947,962, col. 1:21-30 Terminating these lines is necessary but consumes significant power and can require extra space on the printed circuit board '962 Patent, col. 2:35-43
• The Patented Solution: The patent proposes an on-die termination (ODT) system specifically for the address and command signal lines. A memory controller can selectively enable or disable the ODT circuitry within memory devices connected to the RQ bus '962 Patent, abstract This allows termination to be applied dynamically, for instance, only at the last device on the bus or only during active operations, thereby reducing power consumption during idle periods and optimizing signal integrity without requiring external termination components '962 Patent, col. 3:45-50
• Technical Importance: This invention provides a method for improving signal integrity and reducing power consumption on the address and command bus, a critical consideration for efficiency in modern memory systems.

Key Claims at a Glance

• The complaint asserts at least independent Claim 1 Compl. ¶58
• Claim 1 (Memory controller):
  • A memory controller configured to be connected to one or more memory devices via an address and control (RQ) bus.
  • Each memory device has ODT circuitry connected to a subset of the RQ bus signal lines.
  • The memory controller is operable to selectively disable the ODT circuitry in at least one memory device.
  • Disabling is achieved by driving control signals on a plurality of ODT control lines.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,638,637 - "Memory controller with staggered request signal output"

(Issued Jan. 28, 2014)

• Technology Synopsis: This patent addresses the problem of "request skew," where differences in capacitive loading between various signal lines (e.g., control vs. address/command lines) cause signals to arrive at memory devices at different times U.S. Patent No. 8,638,637, col. 1:40-52 The invention is a memory controller with timing circuitry that provides a programmable phase offset, or "stagger," between the output times of different signal groups to compensate for these propagation delays and ensure they arrive at the memory device more synchronously '637 Patent, col. 2:20-35
• Asserted Claims: At least independent Claim 1 Compl. ¶68
• Accused Features: The complaint alleges that NXP's products incorporating memory controller integrated circuits infringe the '637 Patent Compl. ¶41 Compl. ¶68

U.S. Patent No. 10,056,902 - "On-die termination control"

(Issued Aug. 21, 2018)

• Technology Synopsis: As a member of the same family as the '400 Patent, this patent similarly addresses signal integrity in high-speed, multi-module memory systems. It describes a "graduated" on-die termination (ODT) scheme where non-selected memory modules apply a "hard" termination to prevent signal reflections, while the selected module applies a "soft" termination to receive the signal without undue attenuation '902 Patent, abstract '902 Patent, col. 3:20-42
• Asserted Claims: At least independent Claim 1 Compl. ¶78
• Accused Features: The complaint alleges that NXP's products incorporating memory controller integrated circuits infringe the '902 Patent Compl. ¶41 Compl. ¶78

U.S. Patent No. 9,570,129 - "On-die termination of address and command signals"

(Issued Feb. 14, 2017)

• Technology Synopsis: This patent, related to the '962 Patent, also concerns on-die termination (ODT) for address and command (RQ) signal lines in memory systems. It describes a system where memory devices include control registers for storing ODT values, allowing for different termination values to be used on different devices within the same system U.S. Patent No. 9,570,129, abstract This enables fine-tuned control over signal termination to optimize performance and power.
• Asserted Claims: At least independent Claim 1 Compl. ¶88
• Accused Features: The complaint alleges that NXP's products incorporating memory controller integrated circuits infringe the '129 Patent Compl. ¶41 Compl. ¶88

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are a broad range of NXP's semiconductor products, including integrated circuits, microcontrollers (MCUs), microprocessors (MPUs), and Systems-on-Chip (SoCs) that incorporate memory controller circuits supporting one or more Double Data Rate (DDR) memory standards (e.g., DDR3, DDR3L, DDR4, LPDDR4, LPDDR5) Compl. ¶41

Functionality and Market Context

• The relevant functionality of the accused products is the integrated memory controller, which manages the high-speed interface between the processor and external DRAM memory Compl. ¶41 The complaint identifies numerous NXP product families, such as the i.MX, Layerscape (LS), and S32 series, as containing the allegedly infringing technology Compl. ¶44
• The complaint provides a corporate organizational chart for NXP Semiconductors N.V. to illustrate the relationship between the U.S.-based defendant and its foreign parent entities Compl. p. 5 These products are positioned for a wide array of applications, including automotive, industrial, and consumer electronics, and constitute a significant portion of Defendant's business Compl. ¶13

IV. Analysis of Infringement Allegations

The complaint references, but does not include, claim chart exhibits (Exhibits 1-5) that purportedly detail the infringement of each asserted patent Compl. ¶52 Compl. ¶62 Compl. ¶72 Compl. ¶82 Compl. ¶92 In the absence of these exhibits, the analysis is based on the narrative allegations.

U.S. Patent No. 10,944,400

• Narrative Infringement Theory: The complaint alleges that NXP's products with DDR memory controllers infringe at least Claim 1 of the '400 Patent Compl. ¶48 The core allegation is that these products implement the claimed method of on-die termination control, which involves using different termination impedance values during and after a write-data reception interval. The complaint suggests this functionality is inherent to the operation of the accused products when interfacing with DDR memory Compl. ¶41 Compl. ¶48
• Identified Points of Contention: The infringement analysis may turn on whether the standard ODT modes defined in JEDEC DDR standards and implemented in the accused products meet the specific limitations of Claim 1. A key question for the court will be whether the accused products' functionality constitutes storing and applying two distinct termination values-one "during" and a second "after" the write reception interval-as recited in the claim, or if their operation differs in a material way.

U.S. Patent No. 8,947,962

• Narrative Infringement Theory: The complaint alleges that NXP's products infringe at least Claim 1 of the '962 Patent by making, using, and selling memory controllers that can "selectively disable" the ODT circuitry for the address and command (RQ) bus Compl. ¶58 The complaint's theory appears to be that the accused memory controllers practice this claimed feature as part of their standard operation with external memory devices Compl. ¶41
• Identified Points of Contention: A central question will be one of claim scope: what actions constitute "selectively disabl[ing] the ODT circuitry" as required by the claim. The dispute may focus on whether standard power-saving modes or other operational states in the accused products meet this limitation, and whether this is achieved by "driving control signals on a plurality of ODT control lines" as further required by the claim.

V. Key Claim Terms for Construction

For U.S. Patent No. 10,944,400

• The Term: "a second termination that is to be applied to the data interface after the write-data reception interval transpires" (Claim 1)
• Context and Importance: This term is critical because it defines the two-stage temporal nature of the claimed termination scheme. The infringement analysis will depend on whether the accused products apply a first impedance value during the data reception and a distinct second value after it concludes, or if they employ a different timing or a single termination state.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes a transition from a "soft" termination to a "hard" termination or decoupling the termination entirely, suggesting "second termination" could encompass multiple distinct states that occur post-reception '902 Patent, col. 3:34-42 '902 Patent, Fig. 6
  • Evidence for a Narrower Interpretation: The claim language "after the... interval transpires" suggests a specific event-based trigger. An embodiment in a related patent figure shows a transition from a "Write (Soft T)" state to a "Precharge (Hard T)" or "Active (Hard T)" state, which might be argued to limit the "second termination" to a specific post-write operational state ('902 Patent, Fig. 6, transitions 355 to 359 or 353).

For U.S. Patent No. 8,947,962

• The Term: "selectively disable the ODT circuitry" (Claim 1)
• Context and Importance: The definition of this term is central to the infringement case. Whether the accused products infringe will hinge on what technical operations are construed as "disabling" the ODT. Practitioners may focus on this term because standard memory controllers have various power-down and idle modes, and the question is whether these modes meet the claim limitation.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification discusses disabling termination to save power during idle times, suggesting that entering a power-saving state where termination is turned off could be construed as "selectively disabl[ing]" the circuitry '962 Patent, col. 3:45-50 The term "disable" itself could be interpreted broadly to mean turning off or de-powering.
  • Evidence for a Narrower Interpretation: The specification also discusses dynamic control where termination is disabled for a non-addressed device, implying an active, transaction-specific disabling command rather than a general power-saving mode '962 Patent, col. 3:10-15 The patent also describes a specific "CAODT" control signal, and a defendant may argue that "selectively disable" requires the use of such a specific, dedicated control mechanism '962 Patent, col. 3:5-8

VI. Other Allegations

Indirect Infringement

The complaint alleges that NXP induces infringement by knowingly and intentionally encouraging its customers and downstream users to infringe. This is allegedly done through the creation and dissemination of advertisements, user manuals, technical documentation, design tools, and online support forums that instruct on the use of the accused products' memory controller functionalities Compl. ¶¶50-51 Compl. ¶¶60-61

Willful Infringement

The complaint alleges willful infringement based on NXP's purported knowledge of the asserted patent families. This knowledge is alleged to arise from a long-standing patent license agreement between Rambus and Freescale (later acquired by NXP), which covered the asserted patent families and expired in March 2018 Compl. ¶¶5-8 The allegation is further supported by two specific notices of infringement that Rambus allegedly sent to NXP in May and August of 2018, with the latter notice including detailed claim charts Compl. ¶¶9-11

VII. Analyst's Conclusion: Key Questions for the Case

• Definitional Scope vs. Industry Standards: A core issue will be whether the specific ODT and signal timing methods recited in the patent claims can be read onto the functionality of memory controllers that comply with JEDEC DDR standards. The case may turn on whether the accused products perform the exact sequence of "graduated" termination or "staggered" signal launching as claimed, or if their standards-compliant operation is technically distinct.
• The Weight of History: A central legal question will be the impact of the prior licensing agreement and the subsequent 2018 infringement notices on the issue of willfulness. The analysis will likely focus on whether NXP's continued conduct after the license expired and after receiving specific notice constitutes the "egregious" behavior required for enhanced damages.
• Evidentiary Proof of Operation: For a patent like the '637, which claims a specific method of staggering signal outputs via programmable offsets, a key evidentiary question will be what proof demonstrates that the accused controllers actively and programmably implement this technique. The dispute may center on whether any observed timing offsets are the result of the claimed invention or are merely inherent, uncompensated signal skew.