Nextech Semiconductor LLC v. Advanced Micro Devices Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Nextech Semiconductor, LLC (Texas)
  • Defendant: Advanced Micro Devices, Inc. (Delaware)
  • Plaintiff's Counsel: Cherry Johnson Siegmund James PLLC
• Case Identification: 7:26-cv-00080, W.D. Tex., 03/06/2026
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant AMD maintains multiple regular and established places of business in the district, including in Austin, Texas, where it has represented it has "significant operations" and where its CEO and CTO are based.
• Core Dispute: Plaintiff alleges that Defendant's Radeon and Ryzen processors infringe five U.S. patents related to semiconductor circuit design, including technologies for electrostatic discharge (ESD) protection, phase-locked loops, tunable oscillators, and level shifters.
• Technical Context: The patents-in-suit address fundamental circuit-level challenges in modern, high-performance integrated circuits, focusing on reliability, signal integrity, and power management in complex multi-power-domain environments.
• Key Procedural History: The asserted patents were previously owned by NXP Semiconductors N.V. or its affiliates. The complaint alleges that on May 11, 2023, NXP sent a notice letter to AMD identifying all five asserted patents and providing "evidence of use documents or claim charts demonstrating the alleged infringement." This alleged pre-suit notice is cited as the basis for willful infringement claims. NXP subsequently assigned the patents to Plaintiff Nextech.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,593,202 - Electrostatic Discharge (ESD) Protection Circuit for Multiple Power Domain Integrated Circuit

• Issued: September 22, 2009

The Invention Explained

• Problem Addressed: The patent addresses the challenge of providing effective ESD protection in complex integrated circuits that operate with multiple, distinct power domains. Specifically, when input/output (I/O) buffers for different power domains are physically mixed or "interspersed," conventional ESD protection schemes can require substantial and inefficient layout area '202 Patent, col. 1:41-48
• The Patented Solution: The invention proposes an integrated circuit architecture where a bank of I/O cells, coupled to first and second power domains, is protected by corresponding first and second pluralities of "active clamps." The key innovation is that these two sets of active clamps "overlap along said bank of I/O cells," enabling a more compact and modular layout for ESD protection in multi-power-domain environments '202 Patent, abstract '202 Patent, col. 2:9-18
• Technical Importance: This approach allows for greater flexibility in chip design by permitting I/O cells from different power domains to be placed adjacent to one another without compromising ESD protection or incurring significant area penalties '202 Patent, col. 7:4-9

Key Claims at a Glance

• The complaint asserts at least Claim 1 Compl. ¶185
• Independent Claim 1 requires:
  • An integrated circuit with a first and second power domain.
  • A bank of input/output (I/O) cells coupled to both power domains.
  • A first plurality of active clamps for the first power domain.
  • A second plurality of active clamps for the second power domain.
  • A final limitation stating that the first and second pluralities of active clamps "overlap along said bank of I/O cells."
• The complaint reserves the right to assert other claims Compl. ¶183

U.S. Patent No. 8,558,591 - Phase Locked Loop with Power Supply Control

• Issued: October 15, 2013

The Invention Explained

• Problem Addressed: Phase-locked loops (PLLs), which are critical for generating precise clock frequencies, are primarily analog circuits. However, they are often integrated into larger digital systems manufactured using processes optimized for logic, not analog performance. Different components within a PLL-such as the voltage-controlled oscillator (VCO), charge pump, and phase frequency detector-have different requirements for transistor speed, leakage, and operating voltage, which are difficult to satisfy with a single power supply in a logic-optimized process '591 Patent, col. 1:11-26 '591 Patent, col. 2:40-62
• The Patented Solution: The patent describes a PLL where the three key analog components are powered by three distinct analog supply voltages, each tailored to the component's specific needs. A "filtered supply voltage provider" generates the separate supply voltages for the phase frequency detector, the charge pump, and the VCO from a single external analog source, allowing for optimized performance of each component '591 Patent, abstract '591 Patent, col. 4:18-24
• Technical Importance: This architecture allows for the use of different types of transistors (e.g., high-speed/leaky for the VCO, low-leakage for the charge pump) within the same PLL, improving overall performance and noise isolation without requiring complex, separate external power supplies '591 Patent, col. 2:38-54

Key Claims at a Glance

• The complaint asserts at least Claim 1 Compl. ¶228
• Independent Claim 1 requires:
  • A phase frequency detector powered by a "first analog supply voltage."
  • A charge pump powered by a "second analog supply voltage, different from the first."
  • A voltage controlled oscillator (VCO) powered by a "third analog supply voltage, different from the first... and different from the second."
  • A supply voltage provider with circuit nodes that provide these first, second, and third analog supply voltages.
• The complaint reserves the right to assert other claims Compl. ¶226

U.S. Patent No. 8,604,889 - Tunable LC Oscillator with Common Mode Voltage Adjustment

• Issued: December 10, 2013

Technology Synopsis

The patent addresses phase noise degradation in tunable oscillators that use MOS switches to change frequency. The invention proposes adjusting the oscillator tank's common mode voltage in coordination with frequency changes to prevent the MOS switches from undesirably transitioning between inversion and depletion states, thereby preserving phase noise performance '889 Patent, abstract

Asserted Claims

The complaint asserts at least independent Claim 1 Compl. ¶277

Accused Features

The complaint alleges that adjustable frequency oscillators, such as the "VCOa" component, within AMD's processors infringe the '889 Patent Compl. ¶282

U.S. Patent No. 8,654,488 - Secondary ESD Circuit

• Issued: February 18, 2014

Technology Synopsis

The patent describes a solution to the problem where internal circuit buffers can trigger during an ESD event before the primary, pad-based ESD protection circuit can activate. The invention introduces a "secondary ESD circuit" located between the primary protection and the buffer, which is designed to activate quickly to protect the buffer by limiting the voltage drop across it '488 Patent, abstract

Asserted Claims

The complaint asserts at least independent Claim 1 Compl. ¶324

Accused Features

The complaint alleges that secondary ESD circuits, such as the "ESDb" component, within AMD's processors infringe the '488 Patent Compl. ¶344

U.S. Patent No. 9,917,588 - Level Shifter and Approach Therefor

• Issued: March 13, 2018

Technology Synopsis

The patent discloses a level shifter for translating signals between different voltage domains, particularly in stacked power domain architectures. The invention uses a combination of driver circuits operating at different voltage levels to shift the input signal to the appropriate level for the output domain, avoiding reliance on large capacitors or AC-path dependencies '588 Patent, abstract

Asserted Claims

The complaint asserts at least independent Claim 1 Compl. ¶374

Accused Features

The complaint alleges that level shifter circuits within AMD's processors infringe the '588 Patent Compl. ¶376 Compl. ¶384

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are Defendant AMD's "Radeon Processors and Ryzen Processors" Compl. ¶52 The complaint provides an extensive, non-limiting list of specific product models (Compl. ¶52, fn 12).

Functionality and Market Context

• The complaint identifies the accused products as including integrated circuits that implement technologies such as electrostatic discharge (ESD) protection, level shifters, active clamps, and adjustable frequency oscillators Compl. ¶¶47-50 The infringement allegations focus on the specific circuit-level implementations of these features within the processors.
• For example, infringement allegations against the '202 Patent target the ESD protection architecture in the PCIe interface of the AMD Radeon RX 6600 processor Compl. ¶¶196-197 Allegations against the '591 Patent target the PLL circuits within the same processor Compl. ¶¶233-235 Allegations against the '488 Patent target ESD circuits in the AMD Ryzen 9 5900X processor Compl. ¶328 Compl. ¶332 The complaint provides an annotated die photograph of an AMD Radeon RX 6600, identifying functional blocks such as the "PCIe Interface," "Digital PLL," and "Oscillator Block" Compl. p. 24

IV. Analysis of Infringement Allegations

Claim Chart Summary: 7,593,202 Patent Infringement Allegations

The complaint provides an annotated die layout of the AMD Radeon RX 6600, which purports to show the physical overlap of the ESDc_0 (red box) and ESDb_1 (blue box) components along the bank of I/O cells Compl. p. 29

Identified Points of Contention

• Scope Questions: A central question may be the construction of "active clamps overlap along said bank of I/O cells." The dispute could turn on whether this requires a specific degree of physical interspersion, functional interaction, or merely adjacency within the same general layout area.
• Technical Questions: A factual question will be whether the circuits identified as "ESDc_0" and "ESDb_1" in the accused product function as the "active clamps" described in the '202 Patent specification.

Claim Chart Summary: 8,558,591 Patent Infringement Allegations

The complaint includes a circuit diagram of the PLLa component, annotating the phase frequency detector (red box) and charge pump (blue box) and identifying their respective power supplies as VREG[3] and VREG[2] Compl. p. 39

Identified Points of Contention

• Scope Questions: The interpretation of "different from" will be critical. The question for the court will be whether this requires the supply voltages to be generated from wholly independent sources, or if it is sufficient for them to be regulated to different levels from a common source, as may be the case in the accused products.
• Technical Questions: A key factual dispute may be whether the alleged differences between VREG[1], VREG[2], and VREG[3] are technically significant enough to achieve the patent's stated goals of noise isolation and component optimization, or if they are functionally equivalent to a single supply.

V. Key Claim Terms for Construction

For U.S. Patent No. 7,593,202:

• The Term: "active clamps overlap"
• Context and Importance: This phrase is the central limitation of the asserted independent claim and captures the core of the purported invention. The infringement case for the '202 Patent will likely depend entirely on whether the physical arrangement of the ESD protection circuits in AMD's processors falls within the court's construction of this term.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the invention in general terms, stating "I/O cells associated with each of the two power domains are interspersed along and are adjacent to the set of rails" '202 Patent, col. 7:38-41 This language could support a construction where mere adjacency or intermingling in the same physical area constitutes "overlap."
  • Evidence for a Narrower Interpretation: The patent's abstract states the pluralities of active clamps "overlap along the bank of I/O cells" '202 Patent, abstract Figure 3 of the patent depicts a specific physical arrangement where I/O cells for different domains are interleaved. A defendant may argue this disclosure limits the term "overlap" to a direct physical interspersion of the clamp circuits themselves, not just the I/O cells they protect.

For U.S. Patent No. 8,558,591:

• The Term: "different from the first analog supply voltage"
• Context and Importance: The novelty of the '591 Patent hinges on using distinct power supplies for different PLL components. The definition of "different" is therefore crucial. If voltages that are merely regulated to different levels from a common source are deemed "different," the claim scope is broader. If "different" requires a higher degree of electrical isolation or separate generation, the scope is narrower.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The plain meaning of "different" simply means not identical. The claim language does not explicitly require the voltages to be generated by separate sources.
  • Evidence for a Narrower Interpretation: The patent's background explains the need to address noise and use different transistor types, stating "it is desirable though to isolate the power supply for the VCO from the logic" and noting that different components require different voltages for optimal operation '591 Patent, col. 2:42-54 This context suggests that "different" should be construed to mean sufficiently distinct and isolated to achieve these technical benefits, a potentially higher standard than simply having non-identical voltage values.

VI. Other Allegations

• Indirect Infringement: The complaint alleges that AMD induces infringement by third parties (including manufacturers, customers, and subsidiaries) by providing "specifications, datasheets, instruction manuals, support materials, developer materials, marketing materials, and user guide materials" that instruct on the use of the Accused Products Compl. ¶212 Compl. ¶261 Compl. ¶308 Compl. ¶357 Compl. ¶433
• Willful Infringement: The complaint alleges willful infringement based on AMD's alleged knowledge of the asserted patents since at least May 11, 2023. This knowledge is purportedly based on a notice letter and accompanying infringement evidence provided by the previous patent owner, NXP Compl. ¶214 Compl. ¶263 Compl. ¶310 Compl. ¶359 Compl. ¶435 The complaint further alleges that AMD continued its infringing conduct despite this notice Compl. ¶135

VII. Analyst's Conclusion: Key Questions for the Case

This case appears to center on highly technical, circuit-level details within complex semiconductor products. The central questions for the court will likely involve both claim construction and the detailed factual analysis of the accused devices' internal architecture.

1. A core issue will be one of definitional scope: For the '202 Patent, can the term "overlap," used to describe the arrangement of ESD active clamps, be construed to cover the physical adjacency of protection circuits shown in the accused products' die layouts, or does it require a more specific form of structural interspersion as depicted in the patent's own figures?
2. A second key issue will be one of functional distinction: For the '591 Patent, are the different voltage levels (VREG[1], VREG[2], VREG[3]) supplied to the PLL components in AMD's processors "different" in the manner required by the claim? This may turn on whether they provide the functional isolation and performance optimization that forms the basis of the patented invention, or are merely incidental variations from a common regulated source.
3. An overarching evidentiary question will be one of technical mapping: Given the complexity of the accused processors, the case will depend heavily on the parties' ability to present clear and convincing evidence (e.g., from reverse engineering and circuit analysis) that either proves or disproves that the specific, multi-part functions described in each claim element are performed by the corresponding structures within AMD's products.