Nextech Semiconductor LLC v. Micron Technology Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Nextech Semiconductor, LLC (Texas)
  • Defendant: Micron Technology, Inc. (Delaware); Micron Semiconductor Products, Inc. (Idaho)
  • Plaintiff's Counsel: Cherry Johnson Siegmund James PLLC
• Case Identification: 7:26-cv-00079, W.D. Tex., 03/06/2026
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant Micron maintains a regular and established place of business in Austin, Texas, and has employees in Austin responsible for working on, marketing, and selling the Accused Products.
• Core Dispute: Plaintiff alleges that Defendant's Solid-State Drive (SSD), 3D NAND, and DDR SDRAM products infringe six patents related to semiconductor circuit design, including technologies for electrostatic discharge protection, power management, and clock generation.
• Technical Context: The patents-in-suit address fundamental circuit-level challenges in modern semiconductors, such as protecting chips from static electricity, efficiently managing power consumption in battery-operated devices, and generating stable clock signals.
• Key Procedural History: The complaint states that the asserted patents were previously owned by NXP Semiconductors N.V. (NXP) or its predecessors. It is alleged that on September 13, 2022, NXP sent a notice letter to Micron that identified all of the now-asserted patents and was accompanied by claim charts or other evidence demonstrating infringement. Following Micron's decision not to take a license, NXP assigned the patents to Plaintiff Nextech to pursue this litigation.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,593,202 - "Electrostatic Discharge (ESD) Protection Circuit for Multiple Power Domain Integrated Circuit"

• Patent Identification: U.S. Patent No. 7,593,202, issued September 22, 2009 Compl. ¶40

The Invention Explained

• Problem Addressed: The patent's background section describes the difficulty of providing effective electrostatic discharge (ESD) protection in complex integrated circuits that operate with multiple, distinct power domains (e.g., different voltages for different parts of the chip), noting that interspersing I/O buffers from different domains requires substantial layout area for protection circuitry '202 Patent, col. 1:39-48
• The Patented Solution: The invention proposes an architecture where a bank of input/output (I/O) cells is coupled to two different power domains, and the ESD protection circuits (specifically, the "active clamps") for each domain are physically distributed and overlap along this bank of I/O cells '202 Patent, abstract '202 Patent, col. 2:10-18 This structure allows for shared and more area-efficient ESD protection in a mixed-voltage environment, as illustrated in the embodiment of Figure 3 '202 Patent, FIG. 3
• Technical Importance: This distributed approach to ESD protection was important for enabling the design of complex, power-efficient Systems-on-Chip (SoCs) where core logic and peripheral I/O circuits often operate at different voltages.

Key Claims at a Glance

• The complaint asserts at least Claim 1 Compl. ¶195 Compl. ¶198
• Independent Claim 1 requires:
  • An integrated circuit comprising:
  • a first power domain;
  • a second power domain; and
  • a bank of input/output (I/O) cells coupled to said first and second power domains, including a first plurality of active clamps for said first power domain and a second plurality of active clamps for said second power domain wherein said first and second pluralities of active clamps overlap along said bank of I/O cells.
• The complaint reserves the right to assert other claims Compl. ¶196

U.S. Patent No. 7,999,601 - "Charge Pump and Control Scheme"

• Patent Identification: U.S. Patent No. 7,999,601, issued August 16, 2011 Compl. ¶41

The Invention Explained

• Problem Addressed: The patent's background discusses the need to control power for electronic devices like microprocessors, which may be placed into low-power states '601 Patent, col. 1:10-18 When re-enabling a circuit, a high initial current is needed to charge its capacitance, which can be slow if performed by a charge pump alone, but a charge pump may be needed to reach a final voltage higher than the main power source (e.g., a battery) '601 Patent, col. 1:56-65
• The Patented Solution: The invention describes a two-stage power-up sequence. First, a main power source (e.g., a battery) is connected to pre-charge an output channel to a first, intermediate voltage. Subsequently, the power source is disconnected, and a charge pump is used to complete the charging to a second, higher final voltage '601 Patent, abstract '601 Patent, col. 2:15-32 This approach uses the high-current capability of the main source for the initial bulk charging and the voltage-boosting capability of the charge pump for the final stage, optimizing speed and efficiency.
• Technical Importance: This control scheme provides an efficient method for power-gating and managing different voltage levels in battery-powered electronics, where both power conservation and fast wake-up times are critical.

Key Claims at a Glance

• The complaint asserts at least Claim 1 Compl. ¶236 Compl. ¶239
• Independent Claim 1 requires:
  • A switch controller comprising:
  • a charge pump configured to provide a first charge voltage;
  • a selector switch connected to the charge pump and operable to connect to an output channel;
  • a power source connection communicating with the input to the selector switch, providing power at a second charge voltage that is less than the first charge voltage;
  • wherein during enablement, the selector switch first provides power from the power source connection to charge the output channel to a voltage below the first charge voltage, and subsequently provides power from the charge pump to charge the output channel to the first charge voltage.
• The complaint reserves the right to assert other claims Compl. ¶237

U.S. Patent No. 8,179,108 - "Regulator Having Phase Compensation Circuit"

• Patent Identification: U.S. Patent No. 8,179,108, issued May 15, 2012 Compl. ¶272
• Technology Synopsis: The patent describes a voltage regulator circuit that includes a phase compensation circuit with a variable resistor. The resistance of this variable resistor is designed to decrease as the regulator's output current increases, which adjusts the output impedance of a differential amplifier to improve stability (phase margin) across a wide range of load currents '108 Patent, abstract
• Asserted Claims: The complaint asserts at least Claim 1 Compl. ¶276 Compl. ¶279
• Accused Features: The complaint alleges that regulators, such as the VN_VREG circuit, found in Micron's DDR SDRAM Products (e.g., the D9XPC memory chip) infringe the '108 Patent Compl. ¶¶281-284

U.S. Patent No. 8,558,591 - "Phase Locked Loop with Power Supply Control"

• Patent Identification: U.S. Patent No. 8,558,591, issued October 15, 2013 Compl. ¶312
• Technology Synopsis: The patent discloses a phase-locked loop (PLL) where its core components-the phase frequency detector, the charge pump, and the voltage-controlled oscillator (VCO)-are powered by three different analog supply voltages. This power separation helps to isolate noise and improve the performance and stability of the PLL '591 Patent, abstract
• Asserted Claims: The complaint asserts at least Claim 1 Compl. ¶316 Compl. ¶319
• Accused Features: The complaint alleges that PLLs within Micron's SSD Products, such as the Micron 2300 SSD, infringe the '591 Patent Compl. ¶¶321-324

U.S. Patent No. 8,604,889 - "Tunable LC Oscillator with Common Mode Voltage Adjustment"

• Patent Identification: U.S. Patent No. 8,604,889, issued December 10, 2013 Compl. ¶362
• Technology Synopsis: The patent describes a tunable LC oscillator that includes a common mode voltage adjustment circuit. As the oscillator's frequency is changed (e.g., by switching capacitors), this circuit adjusts the common mode voltage to reduce state changes (e.g., from inversion to depletion) in the MOS switches, thereby minimizing phase noise degradation '889 Patent, abstract
• Asserted Claims: The complaint asserts at least Claim 1 Compl. ¶366 Compl. ¶369
• Accused Features: The complaint alleges that adjustable frequency oscillators, such as the PCIe PLLa, within Micron's SSD Products infringe the '889 Patent Compl. ¶¶371-375

U.S. Patent No. 8,704,587 - "Configurable Multistage Charge Pump Using a Supply Detect Scheme"

• Patent Identification: U.S. Patent No. 8,704,587, issued April 22, 2014 Compl. ¶411
• Technology Synopsis: The patent discloses a multistage charge pump that includes control logic to determine the input voltage range. Based on this determination, the logic can disable and bypass one or more of the pump's stages, effectively reconfiguring the charge pump to operate efficiently across a wide range of input supply voltages '587 Patent, abstract
• Asserted Claims: The complaint asserts at least Claim 1 Compl. ¶415 Compl. ¶418
• Accused Features: The complaint alleges that configurable multistage charge pumps found in the 3D NAND chips of Micron's SSD Products infringe the '587 Patent Compl. ¶¶420-424

III. The Accused Instrumentality

Product Identification

• The accused instrumentalities are broadly identified as Micron's SSD Products, 3D NAND Products, and DDR SDRAM Products Compl. ¶54 Specific product examples provided in the complaint include the Micron 2300 SSD and the Micron D9XPC DDR SDRAM memory chip Compl. ¶202 Compl. ¶283

Functionality and Market Context

• The complaint alleges that these products contain complex integrated circuits that implement the specific technologies claimed by the asserted patents Compl. ¶¶47-53 For example, the Micron 2300 SSD is alleged to contain an integrated circuit with multiple power domains and overlapping ESD clamps Compl. ¶206 Compl. ¶207, a switch controller that uses a two-stage charging scheme Compl. ¶255, a PLL with multiple analog supply voltages Compl. ¶335, and a tunable oscillator with common mode voltage adjustment Compl. ¶388 The complaint provides an annotated photograph of the Micron 2300 SSD's printed circuit board, identifying the controller IC and NAND flash memory chips as containing the infringing functionalities Compl. ¶204 Compl. ¶244
• The complaint positions Micron as a major semiconductor company that was a "holdout" from licensing NXP's patent portfolio, suggesting a significant market presence for the accused products Compl. ¶16

IV. Analysis of Infringement Allegations

'202 Patent Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: A central question may be the construction of the term "overlap." The dispute could turn on whether the alleged physical interspersing of separate clamp circuits along a bank of I/O cells meets the definition of "overlap," or if a more direct physical layering or sharing of components is required by the claim language.
  • Technical Questions: The complaint relies on static die layouts to show the physical arrangement. The technical question will be whether this structural evidence is sufficient to demonstrate the functional coupling and operational characteristics of the "active clamps" as required by the patent.

'601 Patent Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: A potential issue may be whether the accused "power source connection" and "selector switch" are discrete components or functions that map clearly onto the claim limitations, or if they are part of a more integrated circuit whose operation does not align with the claimed structure.
  • Technical Questions: The infringement theory rests on a specific sequence of operations. The key technical question will be evidentiary: what proof does the complaint or subsequent discovery provide that the accused circuit actually operates by first charging from the power source connection and subsequently charging from the charge pump, as opposed to another method of operation? The complaint's static circuit diagrams do not, by themselves, demonstrate this temporal sequence.

V. Key Claim Terms for Construction

For the '202 Patent

• The Term: "overlap"
• Context and Importance: The novelty of Claim 1 centers on the arrangement of active clamps from different power domains. The construction of "overlap" will be dispositive for infringement, determining whether the physical interspersing of clamp circuits alleged in the complaint is sufficient to meet the limitation.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes how "I/O cells associated with each of the two power domains are interspersed" and that "active clamp networks may be described as overlapping ('interspersed')" '202 Patent, col. 8:36-37 '202 Patent, col. 9:39-41 This language may support an argument that physical interspersing along the I/O bank is what the patent means by "overlap."
  • Evidence for a Narrower Interpretation: Figure 5 of the patent depicts a layout view where metal lines for different ESD structures are physically layered on top of one another '202 Patent, FIG. 5 This could be used to argue for a narrower construction requiring some form of vertical stacking or direct physical contact, rather than just lateral adjacency.

For the '601 Patent

• The Term: "subsequently provides power from the charge pump"
• Context and Importance: This term establishes a required sequence of events. Infringement depends on proving that the accused device performs the charge pump step after the initial pre-charge step from the power source connection. Practitioners may focus on this term because it defines the core operational method of the invention.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The abstract and summary describe the process functionally: "disconnecting the power source, and running the charge pump for a second determined time" '601 Patent, col. 2:20-22 This broad description may support finding infringement even if the transition is not instantaneous or involves intermediate steps, as long as the general sequence is maintained.
  • Evidence for a Narrower Interpretation: The detailed description explains the sequence in the context of specific state tables and control logic signals '601 Patent, Table I '601 Patent, col. 6:40-66 A defendant may argue that "subsequently" should be construed in light of these specific embodiments, requiring a distinct and non-overlapping sequence of control signals that may not be present in the accused device.

VI. Other Allegations

Indirect Infringement

• The complaint alleges induced infringement for all asserted patents. The allegations are based on Micron's creation and distribution of "specifications, datasheets, instruction manuals, support materials... and user guide materials that explain, advertise, instruct on, or provide support for the Accused Products" Compl. ¶222 Compl. ¶262 Compl. ¶302 Compl. ¶352 Compl. ¶401 Compl. ¶443 These materials allegedly encourage and instruct third parties, such as customers and system integrators, to use the accused products in an infringing manner.

Willful Infringement

• The complaint alleges that Micron's infringement has been and continues to be willful Compl. ¶227 Compl. ¶267 Compl. ¶307 Compl. ¶357 Compl. ¶406 Compl. ¶448 The primary basis for this allegation is the claim that Micron received a notice letter from NXP, the prior patent owner, on or around September 13, 2022. This letter allegedly identified all the asserted patents and was "accompanied by evidence of use documents or claim charts demonstrating the alleged infringement" Compl. ¶¶140-142 Compl. ¶224 This alleges pre-suit knowledge of both the patents and the specific infringement theories.

VII. Analyst's Conclusion: Key Questions for the Case

1. A central issue will be one of definitional scope: can the term "overlap," as used in the '202 patent, be construed to cover the physical interspersing of separate ESD circuits along a bank of I/O cells, as alleged in the complaint, or does it require a more direct physical integration or vertical layering?

2. A key evidentiary question will be one of proof of operation: the infringement allegations for several patents, including the '601 and '587 patents, depend on the accused circuits performing a specific sequence of actions or reconfiguring dynamically. As the complaint relies primarily on static circuit and layout diagrams, a core issue for the court will be whether the plaintiff can produce sufficient operational evidence (e.g., from testing, simulations, or internal defendant documents) to prove these claimed functional and sequential limitations are met.

3. The case will likely feature a significant dispute over willfulness and damages, hinging on the alleged pre-suit notice letter from September 2022. A critical question for the court will be what actions, if any, Micron took to assess the infringement allegations upon receipt of that notice and whether it formed a good-faith belief of non-infringement or invalidity, which will be central to determining enhanced damages.