UNM Rainforest Innovations v. NXP Semiconductors NV

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: UNM Rainforest Innovations (New Mexico)
  • Defendant: NXP Semiconductors N.V. (Netherlands), NXP BV. (Netherlands), and NXP USA, Inc. (Delaware)
  • Plaintiff's Counsel: Cahill Gordon & Reindel LLP; Key Kesan Dallmann PLLC; Cherry Johnson Siegmund James PLLC.
• Case Identification: 7:26-cv-00058, W.D. Tex., 06/30/2026
• Venue Allegations: Venue is alleged to be proper for the foreign NXP entities because an action against a foreign defendant can be brought in any judicial district. For NXP USA, Inc., venue is based on its alleged maintenance of regular and established places of business in the district, including its corporate headquarters and wafer fabrication facilities.
• Core Dispute: Plaintiff alleges that Defendant's microprocessors and related products, which are used in automotive, industrial, and consumer electronics, infringe a portfolio of eight U.S. patents concerning microprocessor memory management, virtual-to-physical address translation, and page size handling.
• Technical Context: The technology at issue relates to the architecture of Memory Management Units (MMUs) within modern processors, which are fundamental for enabling operating systems to manage virtual memory, enforce security protections, and support multitasking and virtualization.
• Key Procedural History: The complaint asserts that Plaintiff, as an arm of the University of New Mexico, possesses sovereign immunity and does not waive it for the purposes of inter partes review or other post-grant proceedings at the U.S. Patent and Trademark Office. The complaint also references prior litigation in the same district where Defendants allegedly submitted to the court's jurisdiction.

Case Timeline

Date	Event
2007-06-01	Priority Date for '620, '703, '916, '191, '520 Patents
2007-12-31	Priority Date for '855, '155, '244 Patents
2014-08-05	U.S. Patent No. 8,799,620 Issues
2015-01-01	NXP merger with Freescale, Inc.
2015-10-13	U.S. Patent No. 9,158,703 Issues
2015-10-20	U.S. Patent No. 9,164,916 Issues
2016-01-26	U.S. Patent No. 9,244,855 Issues
2018-04-03	U.S. Patent No. 9,934,155 Issues
2019-02-08	NXP admissions regarding product sales in prior litigation
2019-10-15	U.S. Patent No. 10,445,244 Issues
2021-07-27	U.S. Patent No. 11,074,191 Issues
2022-06-17	Asserted Patents assigned from Intel Corp. to UNMRI
2023-05-01	NXP litigation on the merits in ParkerVision, Inc. v. NXP
2026-03-31	U.S. Patent No. 12,591,520 Issues
2026-06-30	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,799,620 - "Linear to Physical Address Translation with Support for Page Attributes"

The Invention Explained

• Problem Addressed: Conventional methods for translating a virtual (linear) memory address to a physical one require a "page table walk," a process involving multiple memory accesses that consumes processing time and energy Compl. ¶36 '620 Patent, col. 2:16-19 This is inefficient, particularly for tasks like diagnostics or enforcing security policies that only need metadata about a memory page, not its actual content.
• The Patented Solution: The patent describes a processor instruction that, when executed, accepts a virtual address and returns both the corresponding physical address and associated page attributes (e.g., access rights, caching policy, fault status) without accessing the underlying data at that memory location Compl. ¶35 The invention leverages a Translation Lookaside Buffer (TLB), which caches previous translations, to retrieve the physical address and attributes directly, bypassing the need for a full data access and accelerating memory operations Compl. ¶36 '620 Patent, col. 8:14-22
• Technical Importance: This approach allows operating systems and hypervisors to perform frequent, low-level tasks like checking permissions, diagnosing faults, and managing virtualization more efficiently, improving overall system performance and security Compl. ¶36

Key Claims at a Glance

• The complaint asserts independent claims 1 (a method) and 11 (a system) Compl. ¶66
• The essential elements of independent claim 1 include:
  • Receiving an instruction to translate a virtual memory pointer to a physical memory address for a memory location without accessing the data stored at that address.
  • Translating the virtual memory pointer to the physical memory address based on page table information.
  • Returning, in one or more registers, the physical memory address and one or more page attributes (including access bits) without returning the stored data.
  • Wherein the returning step comprises obtaining the physical address and page attributes from a translation look-aside buffer entry.
• The complaint reserves the right to assert additional claims Compl. ¶66

U.S. Patent No. 9,158,703 - "Linear to Physical Address Translation with Support for Page Attributes"

The Invention Explained

• Problem Addressed: This patent, a continuation of the '620 Patent, targets inefficiencies in kernel-level memory management. Specifically, it addresses situations where the system needs to diagnose a page fault or check memory attributes without triggering a full, exception-handling process, which can be resource-intensive Compl. ¶39
• The Patented Solution: The '703 Patent claims a processor with a specific hardware structure designed to execute a privileged, kernel-level instruction for address translation. The structure includes a plurality of registers, a TLB, a "page miss handler" for performing a table walk, and a dedicated 64-bit physical address return register '703 Patent, claim 1 A key feature is the ability to indicate a page fault without generating a system exception, which streamlines memory management decisions for the operating system or hypervisor Compl. ¶39
• Technical Importance: By providing a mechanism to query memory attributes and fault status without the overhead of exception handling, the invention improves microprocessor performance and energy efficiency, particularly in virtualization and security-sensitive contexts Compl. ¶39

Key Claims at a Glance

• The complaint asserts independent claim 1 (a processor) Compl. ¶83
• The essential elements of independent claim 1 include:
  • A processor comprising a plurality of registers, at least one TLB, a page miss handler, and a 64-bit physical address return register.
  • The processor is to receive a kernel-level privileged instruction to translate a virtual address.
  • The instruction causes the processor, in 64-bit mode, to:
    • translate the virtual address to the first physical address;
    • store the translated physical address in the physical address return register; and
    • store at least one associated attribute in the physical address return register.
• The complaint reserves the right to assert additional claims Compl. ¶83

Multi-Patent Capsules

• Patent Identification: U.S. Patent No. 9,164,916, "Linear to Physical Address Translation with Support for Page Attributes," issued October 20, 2015.

• Technology Synopsis: The patent covers a processor executing a privileged instruction that translates a virtual address to a physical address and stores both the address and selected attributes in a return register Compl. ¶42 This reduces overhead for kernel/hypervisor operations and improves performance for memory management and fault diagnosis Compl. ¶42

• Asserted Claims: Claim 1 is asserted Compl. ¶116

• Accused Features: The "Accused Modem Products," which allegedly bundle a modem with processors containing Arm Cortex CPU cores and MMUs, are accused of infringing Compl. ¶117

• Patent Identification: U.S. Patent No. 9,244,855, "Method, System, and Apparatus for Page Sizing Extension," issued January 26, 2016.

• Technology Synopsis: The patent claims techniques that allow multiple smaller, aligned memory pages to be treated as a single larger page by setting a designated bit or flag Compl. ¶45 This reduces address-translation overhead while maintaining compatibility with existing paging hierarchies, enabling dynamic use of larger pages to improve performance Compl. ¶45

• Asserted Claims: Claims 1 and 9 are asserted Compl. ¶94

• Accused Features: The accused features are the MMUs in NXP's processors, which allegedly support different page sizes (termed "granules") and implement a "contiguous block entries" feature that aligns with the claimed invention Compl. ¶¶96-97

• Patent Identification: U.S. Patent No. 9,934,155, "Method, System, and Apparatus for Page Sizing Extension," issued April 3, 2018.

• Technology Synopsis: As a continuation of the '855 Patent, this patent covers techniques to manage groups of smaller, aligned pages as larger pages, specifying page table entry formats and the use of TLBs for different page sizes Compl. ¶48 This enables more flexible memory management by allowing reserved bits in page table entries to designate a larger page, improving TLB hit rates Compl. ¶48

• Asserted Claims: Claim 1 is asserted Compl. ¶109

• Accused Features: The accused features are the TLBs in NXP's processors, which allegedly implement different page sizes and use a "contiguous bit" to indicate when smaller pages (e.g., 4KB granules) should be treated as a larger page (e.g., 64KB) Compl. ¶112

• Patent Identification: U.S. Patent No. 10,445,244, "Method, System, and Apparatus for Page Sizing Extension," issued October 15, 2019.

• Technology Synopsis: This patent, also in the '855 patent family, claims techniques to initialize and recognize multiple page sizes, including intermediate sizes like 64KB formed from 4KB pages Compl. ¶51 It specifies using bit fields in page table entries to define page size and caching behavior through size-specific TLBs, reducing translation overhead and improving performance Compl. ¶51

• Asserted Claims: Claim 1 is asserted Compl. ¶127

• Accused Features: The accused features are the MMUs in NXP processors, which allegedly support combining smaller page "granules" into larger ones (e.g., 4KB pages into 64KB pages) using a "contiguous block entries" feature Compl. ¶131

• Patent Identification: U.S. Patent No. 11,074,191, "Linear to Physical Address Translation with Support for Page Attributes," issued July 27, 2021.

• Technology Synopsis: This patent provides for an enhanced instruction set to return page attributes, supporting virtualization contexts (guest/host) and both synchronous and asynchronous invocation models Compl. ¶54 The invention enables software to query memory mappings and protections efficiently without accessing memory data, facilitating faster permission checks and diagnostics Compl. ¶54

• Asserted Claims: Claim 1 is asserted Compl. ¶136

• Accused Features: The accused features are the virtualization hardware logic and memory address translation circuitry in NXP's processors, which allegedly implement two-stage address translation (guest-to-guest-physical, then guest-physical-to-host-physical) Compl. ¶¶138-139

• Patent Identification: U.S. Patent No. 12,591,520, "Linear to Physical Address Translation with Support for Page Attributes," issued March 31, 2026.

• Technology Synopsis: A continuation of the '191 Patent, this patent claims systems for address translation that support page attributes, comprising an application, a kernel executing at a higher privilege level, and a hardware circuit Compl. ¶¶57; 145 A key feature is the ability to determine page status and report a page fault without generating a system exception, saving an access to the memory hierarchy Compl. ¶149

• Asserted Claims: Claim 1 is asserted Compl. ¶145

• Accused Features: The accused features are NXP's Layerscape Access LA12xx Development System products, which allegedly include a processor with Arm Cortex A72 cores, a preloaded Linux kernel (the "kernel"), and bundled applications (the "application") Compl. ¶¶146-147

III. The Accused Instrumentality

Product Identification

• The complaint names a broad range of NXP's semiconductor products ("Accused Products"), including those with processor cores designed according to Arm v8-A, v8-R, v9-A, and v9-R architectures, as well as those based on Power Architecture technology Compl. ¶59 Specific product families identified include the i.MX 8 and i.MX 9 Application Processors, S32 Automotive Processors, Layerscape processors, and the QorIQ and PowerQUICC product lines Compl. ¶59

Functionality and Market Context

• The accused functionality resides within the Memory Management Units (MMUs) of these processors, which are responsible for translating virtual memory addresses into physical memory addresses used by the system Compl. ¶69 These processors are marketed for a wide array of applications, including automotive systems (domain/zonal control, radar, vision processing), industrial IoT, smart home devices, and portable healthcare applications Compl. ¶¶61-63 The complaint presents a block diagram from NXP's marketing materials for the S32G2 processor, illustrating its use in both "Domain Vehicle Architectures" and "Zonal Vehicle Architectures" Compl. p. 21 Another diagram shows NXP's "Broadband Modem and Residential Gateway" solution, which integrates a network processor with a broadband modem and other components Compl. p. 23

IV. Analysis of Infringement Allegations

'620 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A machine-implemented method comprising: receiving an instruction to translate a virtual memory pointer to a physical memory address for a memory location without accessing data stored at the physical memory address in response to the instruction;	The MMUs in the Accused Products, designed by ARM, receive Address Translation ("AT") instructions which perform translation "as if reading from the given virtual address" but store the resulting physical address in a register without fetching the actual data.	¶71	col. 8:1-13
translating the virtual memory pointer to the physical memory address based on page table information;	The Accused Products' MMUs translate the virtual address to a physical address using translation tables in memory, a process performed by table walk hardware.	¶70	col. 4:40-46
and returning in one or more registers... the physical memory address and one or more page attributes without returning data stored at physical memory address... the one or more page attributes including a set of access bits,	The MMUs return the translated physical address and associated "memory attributes," including access bits, in a register denoted as PAR_EL1.	¶71	col. 8:4-13
wherein returning in said one or more registers... comprises: obtaining the physical memory address and the one or more page attributes from a translation look-aside buffer entry to return in said one or more registers in response to the instruction.	The MMUs use L1 and L2 Translation Look-Aside Buffers (TLBs) which hold "virtual-to-physical address mappings and memory attributes" to provide the translation result without a full page table walk on a TLB hit.	¶72	col. 8:14-22

'703 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A processor comprising: a plurality of registers;	The Accused Products contain ARM-designed CPU cores which comprise a plurality of registers as set out in ARM documentation.	¶85	col. 1:17-23
at least one translation look aside buffer, wherein the at least one translation look aside buffer is to include a plurality of entries, wherein at least one entry is to include a physical address and a plurality of attributes...	The Accused Products' ARM architecture implements Translation Lookaside Buffers (TLBs) whose entries contain physical addresses and attributes such as memory type, cache policies, and access permissions.	¶¶85-86	col. 1:24-29
a page miss handler to perform a table walk; and	The Accused Products' MMUs are alleged to automatically read translation tables when necessary, a process known as a "Table Walk," upon a TLB miss.	¶87	col. 1:30-31
a physical address return register, wherein the physical address return register is a 64-bit register,	The Accused Products implement PAR_EL1, a 64-bit register whose stated purpose is to receive the physical address from an address translation operation.	¶88	col. 1:32-34
wherein the processor is to receive an instruction to translate a virtual address... wherein the instruction is a kernel level privileged instruction...	The operating kernel in the Accused Products allegedly runs at a privileged level (EL1) and can execute privileged instructions like the Address Translation ("AT") instructions.	¶89	col. 1:35-40
wherein the instruction is to cause the processor, when in a 64-bit mode, to: translate...; store the first physical address...; and store at least one attribute...	The "AT" instructions allegedly cause the processor to translate a 64-bit virtual address, return the resulting physical address in PAR_EL1, and include associated attributes with the returned address.	¶90	col. 1:41-49

• Identified Points of Contention:
  • Scope Questions: A potential area of dispute for the '620 Patent is whether the accused "AT" instructions, which perform translation "as if reading," meet the negative limitation of "without accessing data stored at the physical memory address." For the '703 Patent, a question may arise as to whether the ARM architecture's "Table Walk" hardware is structurally and functionally equivalent to the claimed "page miss handler."
  • Technical Questions: A factual question for the court may be what specific "page attributes" are returned by the accused processors' PAR_EL1 register and whether that set of attributes satisfies the claim requirements, such as the "set of access bits" in claim 1 of the '620 Patent. Another question is whether the ARM architecture's process for handling a translation fault without generating a system exception aligns with the functionality claimed in the '520 Patent.

V. Key Claim Terms for Construction

For the '620 Patent:

• The Term: "without accessing data stored at the physical memory address"
• Context and Importance: This negative limitation is central to the patent's claimed efficiency improvement. Its construction will determine whether the accused ARM "AT" instructions, which the complaint states operate "as if reading from the given virtual address" (Compl. ¶71), fall within the claim scope. Practitioners may focus on this term because the distinction between an instruction that simulates a read versus one that strictly avoids any data access pathway could be a core technical issue.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification may describe this functionally as avoiding the return of "underlying data" to the register file, which could permit some internal hardware access as long as the data itself is not the final output. The purpose is to avoid the "processing time and energy expense of accessing the underlying data" Compl. ¶36, which may support an interpretation focused on the external result, not every internal processor action.
  • Evidence for a Narrower Interpretation: The claim language "without accessing" is explicit. A defendant may argue this requires a complete disengagement from the memory hierarchy's data pathways during the instruction's execution. The abstract of the parent '620 patent refers to returning the physical address "without providing any additional information" '620 Patent, col. 2:32-33, suggesting a very limited operation.

For the '703 Patent:

• The Term: "page miss handler"
• Context and Importance: This is a specific structural element required by claim 1. The infringement analysis hinges on whether the accused processors' hardware for handling a TLB miss, which ARM documentation refers to as performing a "Table Walk" (Compl. ¶87), is properly characterized as a "page miss handler."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent specification may use terms like "page table walker" and "page miss handler" interchangeably or describe the component in broad functional terms as the hardware that resolves a TLB miss by accessing page tables in memory '620 Patent, col. 4:42-46 This could support construing the term to cover any hardware that performs this function.
  • Evidence for a Narrower Interpretation: The term "handler" might imply a software or microcode component, whereas the ARM "Table Walk" is described as "dedicated hardware" (Compl. ¶87). If the specification provides a specific structure for the "page miss handler" that differs from the ARM implementation, a defendant could argue for a narrower construction that excludes the accused products.

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement of infringement for all asserted patents. The basis for this allegation is that NXP knowingly instructs customers and end-users on how to use the infringing functionalities through materials such as "hardware design guides," reference manuals, development boards (e.g., the FRDM i.MX 93 board), and online training modules Compl. ¶¶80; 91; 106; 113 The complaint includes a screenshot of an NXP webpage offering training for its processors Compl. p. 10
• Willful Infringement: While not pleaded as a separate count, the complaint establishes a basis for post-filing willfulness by alleging that NXP has knowledge of the patents and their infringement "no later than service of the Original Complaint" and continues to infringe (Compl. ¶¶66; 83). The prayer for relief seeks enhanced damages under 35 U.S.C. § 284, which is consistent with an allegation of willful infringement.

VII. Analyst's Conclusion: Key Questions for the Case

This case presents a broad challenge to the memory management architecture of NXP's core processor lines. The outcome will likely depend on the court's resolution of several key technical and procedural questions:

• Claim Scope and Technical Equivalence: A primary issue will be whether the specific implementation of address translation in the accused ARM-based processors (e.g., the AT instruction and PAR_EL1 register) performs the same function in substantially the same way to achieve the same result as the methods and systems claimed in the patents. This will involve a detailed comparison of the claimed steps, such as "returning... attributes without accessing data," against the actual operation of the accused MMUs.
• Structural vs. Functional Claiming: The dispute may turn on whether key claim terms like "page miss handler" are interpreted as requiring a specific hardware structure described in the patent or are construed more broadly to cover any component that performs the function of resolving a TLB miss. The degree to which the claims are tied to the specific Intel architecture in which they were developed versus general microprocessor principles will be critical.
• Impact of Sovereign Immunity: A significant procedural battle may arise from the Plaintiff's assertion of sovereign immunity as an arm of a state university. The central question will be whether this status successfully shields the asserted patents from validity challenges in inter partes review (IPR) proceedings before the Patent Trial and Appeal Board, which could limit the Defendant's options and consolidate the entire dispute, including validity, within the district court.