UNM Rainforest Innovations v. NXP Semiconductors NV

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: UNM Rainforest Innovations (New Mexico)
  • Defendant: NXP Semiconductors N.V. (Netherlands), NXP BV. (Netherlands), and NXP USA, Inc. (Delaware)
  • Plaintiff's Counsel: Cahill Gordon & Reindel LLP; Key Kesan Dallmann PLLC; Cherry Johnson Siegmund James P.C.
• Case Identification: 7:26-cv-00058, W.D. Tex., 02/19/2026
• Venue Allegations: Venue is alleged to be proper for the foreign defendants in any judicial district. For NXP USA, Inc., venue is based on its corporate headquarters, design and manufacturing facilities, and wafer fabrication facilities located within the Western District of Texas.
• Core Dispute: Plaintiff alleges that Defendant's application processors, automotive processors, and related products, which incorporate Arm or Power Architecture-based cores, infringe seven U.S. patents related to virtual memory management, address translation, and page sizing techniques.
• Technical Context: The patents relate to fundamental technologies in modern microprocessors for managing virtual memory, which is critical for the functioning of complex operating systems, virtualization, and ensuring system security and performance.
• Key Procedural History: The asserted patents were originally assigned to Intel Corporation and were subsequently conveyed to Plaintiff. The complaint asserts that Plaintiff, as an arm of the University of New Mexico, is entitled to sovereign immunity and does not waive this immunity with respect to post-grant proceedings at the U.S. Patent and Trademark Office, such as inter partes review.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,799,620 - "Linear to Physical Address Translation With Support for Page Attributes," issued August 5, 2014

The Invention Explained

• Problem Addressed: Conventional processor instructions for translating a virtual (or linear) memory address to a physical memory address returned only the physical address Compl. ¶19 To determine the attributes of that memory page (e.g., access rights, caching policy), software would need to perform additional, inefficient operations, such as a full page table walk or accessing the data, consuming processing time and energy Compl. ¶20 '191 Patent, col. 2:20-33
• The Patented Solution: The invention provides a machine-implemented method, executed via a single instruction, that translates a virtual memory pointer to its corresponding physical memory address and, critically, also returns one or more associated page attributes Compl. ¶19 This is accomplished by obtaining the address and attributes from a translation look-aside buffer (TLB) or page table information without needing to access the actual data stored at that memory location '620 Patent, abstract '620 Patent, col. 3:1-13
• Technical Importance: This approach allows operating system kernels and hypervisors to more efficiently query memory mappings, enforce security protections, and diagnose memory faults, thereby improving overall system performance and support for virtualization Compl. ¶20

Key Claims at a Glance

• The complaint asserts independent claim 1 Compl. ¶46
• Claim 1 of the '620 patent recites a machine-implemented method with the following essential steps:
  • Receiving an instruction to translate a virtual memory pointer to a physical memory address for a memory location without accessing data stored at that address.
  • Translating the virtual memory pointer to the physical address based on page table information.
  • Returning, in one or more registers, both the physical memory address and one or more page attributes, also without returning the data stored at the physical address.
  • Wherein the returning step comprises obtaining the physical address and page attributes from a translation look-aside buffer (TLB) entry.

U.S. Patent No. 9,158,703 - "Linear to Physical Address Translation With Support for Page Attributes," issued October 13, 2015

The Invention Explained

• Problem Addressed: As computing systems, particularly those using virtualization, became more complex, the overhead associated with memory management operations remained a significant performance bottleneck Compl. ¶23 A specific challenge was handling memory access faults (e.g., a page not being present) efficiently without triggering costly, general-purpose processor exceptions Compl. ¶23
• The Patented Solution: The '703 Patent claims a processor architecture designed to streamline address translation. The processor includes a TLB, registers, and a "page miss handler" to perform table walks '703 Patent, claim 1 It is designed to execute a privileged instruction that translates a virtual address and stores both the resulting physical address and its attributes in a dedicated 64-bit physical address return register '703 Patent, abstract '703 Patent, claim 1 This framework allows for robust memory-management decisions, including indicating page-walk faults without triggering exceptions Compl. ¶23
• Technical Importance: The claimed processor design enhances kernel-level memory management, streamlining the enforcement of memory protection, caching policies, and page-size handling, which improves microprocessor performance and energy efficiency Compl. ¶23

Key Claims at a Glance

• The complaint asserts independent claim 1 Compl. ¶56
• Claim 1 of the '703 patent recites a processor with the following key components and functions:
  • A plurality of registers.
  • At least one TLB containing entries with physical addresses and associated attributes.
  • A page miss handler to perform a table walk.
  • A 64-bit physical address return register.
  • The processor is configured to receive a kernel-level privileged instruction to translate a virtual address and, in response, cause the processor to: translate the virtual address, store the resulting physical address in the return register, and store at least one associated attribute in the same return register.

U.S. Patent No. 9,164,916 - "Linear to Physical Address Translation With Support for Page Attributes," issued October 20, 2015

• Technology Synopsis: This patent, related to the '620 and '703 patents, claims a complete system comprising a modem and a processor Compl. ¶26 Compl. ¶82 The processor performs a privileged instruction to translate a virtual address to a physical address, storing both the address and its attributes in a return register to reduce overhead for kernel/hypervisor operations and improve fault diagnosis Compl. ¶26
• Asserted Claims: Independent claim 1 is asserted Compl. ¶82
• Accused Features: The complaint accuses NXP products that bundle a modem with a processor containing Cortex CPU cores, referred to as "Accused Modem Products" Compl. ¶83

U.S. Patent No. 9,244,855 - "Method, System, and Apparatus for Page Sizing Extension," issued January 26, 2016

• Technology Synopsis: This patent claims a method for improving virtual memory efficiency by allowing multiple smaller memory pages to be treated as a single larger page Compl. ¶29 The method involves initializing a fixed number of page table entries for contiguous, aligned smaller pages and setting a specific bit in those entries to indicate they should be handled as one combined larger page, reducing address-translation overhead Compl. ¶29
• Asserted Claims: Independent claim 1 is asserted Compl. ¶67
• Accused Features: The infringement allegations target the "contiguous block entries" feature in the Arm architecture used by the accused processors, where a "contiguous bit" signals to the TLB that it can cache a single entry covering multiple smaller pages (termed "granules") Compl. ¶¶69, 71

U.S. Patent No. 9,934,155 - "Method, System, and Apparatus for Page Sizing Extension," issued April 3, 2018

• Technology Synopsis: As a continuation of the '855 patent, this patent claims a processor architecture with multiple TLBs for different page sizes Compl. ¶32 Compl. ¶75 The format for page table entries (PTEs) includes specific bits to indicate page size (e.g., 4KB vs 64KB), whether a page has been written or accessed, and whether the PTE is valid for translation, enabling more flexible memory management Compl. ¶32 Compl. ¶75
• Asserted Claims: Independent claim 1 is asserted Compl. ¶75
• Accused Features: The complaint accuses processors with multiple TLBs and whose page table entry formats include a "contiguous bit" to combine pages, a "dirty bit modifier flag" to indicate writes, and an "access flag bit" Compl. ¶¶77-78

U.S. Patent No. 10,445,244 - "Method, System, and Apparatus for Page Sizing Extension," issued October 15, 2019

• Technology Synopsis: This patent, also in the '855 family, claims a processor with distinct instruction and data address translation circuits Compl. ¶35 Compl. ¶93 The processor sets bits in page table entries to distinguish between different page sizes (e.g., 4KB, 64KB, 4MB) and combines sequential smaller pages into larger ones. The entries also include "cacheable" and "supervisor/user" indicators Compl. ¶93
• Asserted Claims: Independent claim 1 is asserted Compl. ¶93
• Accused Features: The allegations target processors with MMUs that perform address translation, support multiple page "granules," use "contiguous block entries" to combine pages, and define cache policies and access permissions in translation tables Compl. ¶¶95-98

U.S. Patent No. 11,074,191 - "Linear to Physical Address Translation With Support for Page Attributes," issued July 27, 2021

• Technology Synopsis: This patent, from the '620 family, claims a processor with virtualization hardware that translates guest virtual addresses to guest physical addresses, and then to host physical addresses, using two sets of page tables Compl. ¶38 Compl. ¶102 A key feature is a privileged instruction that can access and modify a TLB entry to retrieve attributes without accessing the underlying data in memory or caches Compl. ¶102
• Asserted Claims: Independent claim 1 is asserted Compl. ¶102
• Accused Features: The accused features include processors with virtualization environments (hypervisor and guests) and memory address translation circuitry that executes privileged instructions to access and modify TLB entries Compl. ¶¶104-107

III. The Accused Instrumentality

Product Identification

The complaint names a broad category of NXP products as the "Accused Products" Compl. ¶40 This includes all NXP products that contain processor cores designed according to Arm v8-A, Arm v8-R, Arm v9-A, and Arm v9-R architectures, as well as those built on Power Architecture technology Compl. ¶40 Specific product lines identified include the NXP i.MX 8 and i.MX 9 Application Processors, S32 Automotive Processors, Layerscape network processors, and the QorIQ and PowerQUICC product lines Compl. ¶40 A sub-category, "Accused Modem Products," comprises processors bundled with modems Compl. ¶41 Compl. ¶44

Functionality and Market Context

The accused products are processors and systems-on-chip that provide scalable computing for a wide range of applications, including industrial IoT, smart home, automotive vehicle networking, and broadband gateways Compl. pp. 11-14 Their core infringing functionality, as alleged, resides within their Memory Management Units (MMUs), which are responsible for implementing virtual-memory address translation according to the Arm or Power Architecture specifications Compl. ¶40 For example, the complaint provides a block diagram of the S32G2 Processor for Vehicle Networking, illustrating its Arm Cortex-A53 processor cores and associated memory and networking subsystems Compl. p. 14 Another diagram shows how Layerscape network processors are used in a "Broadband Modem and Residential Gateway" system Compl. p. 15 These processors enable modern, protected operating systems like Linux and Android to run on embedded and automotive devices Compl. p. 11

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,799,620 Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: A central point of contention may be the construction of the phrase "without accessing data stored at the physical memory address." The complaint alleges that the Arm architecture's "AT" instructions, which perform translation "as if reading from the given virtual address" Compl. ¶51, satisfy this limitation. A defendant may argue that performing a translation "as if reading" inherently constitutes a form of "access" (e.g., a permission check that interacts with the memory subsystem) that falls outside the claim's scope, raising the question of what level of interaction qualifies as "accessing data."

U.S. Patent No. 9,158,703 Infringement Allegations

• Identified Points of Contention:
  • Technical Questions: The claim recites a "page miss handler." The complaint alleges that the MMU's automated hardware for performing a "Table Walk" meets this limitation Compl. ¶60 A potential dispute could arise over whether the term "handler," as understood in the context of the patent, can read on fully automated hardware logic or if it requires a specific microcode or software-based routine that is distinct from the accused implementation.

V. Key Claim Terms for Construction

• For the '620 Patent:

  • The Term: "without accessing data stored at the physical memory address"
  • Context and Importance: This negative limitation is crucial for distinguishing the claimed invention from a standard memory read operation. The plaintiff's infringement theory relies on mapping this term to the Arm architecture's "AT" instructions, which perform translation "as if reading" Compl. ¶51 The construction of "accessing data" will therefore be a central issue in determining infringement.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation (i.e., 'accessing' means only reading the content): The '620 patent family describes the benefit of the invention as avoiding the time and energy expense of a full data access Compl. ¶20 Language in the '191 patent specification, part of the same family, clarifies that the LPA instruction determines a page's status "without accessing the data in memory, which saves an access to the memory hierarchy and in many cases a cache miss" '191 Patent, col. 4:40-42 This may support a construction where "accessing data" means retrieving the substantive content at an address, while operations like permission checks do not count as "accessing data."
    • Evidence for a Narrower Interpretation (i.e., 'accessing' includes permission checks): The patent describes instruction variants that "touch as read" or "touch as write" '620 Patent, Table 1 A defendant may argue that these "touch" operations, which test permissions, constitute a form of "access" and that the "without accessing data" limitation requires complete non-interaction with the memory location's state, a standard which the "as if reading" functionality might not meet.

• For the '703 Patent:

  • The Term: "page miss handler"
  • Context and Importance: This term defines a key functional component of the claimed processor. The complaint equates this term with the automated "Table Walk" hardware within the accused MMUs Compl. ¶60 Practitioners may focus on this term because its construction will determine whether a dedicated hardware block for resolving TLB misses meets the definition of a "handler."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation (i.e., a functional definition): The '703 patent specification describes a "page miss handler (PMH)" that "performs a page walk" when a translation is not in the TLB '703 Patent, col. 3:51-53 This functional description, which is not limited to a specific software or hardware implementation, may support a construction broad enough to encompass the accused hardware-based table walkers.
    • Evidence for a Narrower Interpretation (i.e., a structural or software-based definition): The term "handler" in computer architecture often refers to a software routine (e.g., an interrupt handler) or a specific microcode sequence that takes control of the processor to perform a task. A defendant may argue that the common understanding of "handler" at the time of invention implied more than an automated hardware state machine, and that the patent's use of the term without further definition defaults to this narrower meaning.

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement of infringement for all asserted patents. The factual basis for these allegations is that NXP knowingly and intentionally instructs its customers and end-users to infringe by providing extensive technical documentation, including "hardware design guides," reference manuals, and white papers Compl. ¶53 Compl. ¶64 The complaint further alleges that NXP provides development boards and online training modules that encourage and facilitate the use of the Accused Products in an infringing manner Compl. ¶53 Compl. ¶64
• Willful Infringement: The complaint does not contain an explicit count for willful infringement. However, for each patent, it alleges inducement of infringement "since at least the service of this Complaint" (e.g., Compl. ¶46; Compl. ¶56). This allegation establishes a basis for potential liability for post-suit willful infringement or enhanced damages, as it puts Defendant on notice of the alleged infringement.

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the claim term "without accessing data," which is central to the '620 patent family, be construed to cover the accused Arm processors' "as if reading" translation functionality? The case may turn on whether a permission check is considered a form of "accessing data" under the patent's definition.
• A second key question will be one of structural interpretation: does the term "page miss handler," as recited in the '703 patent, read on the automated, hardware-based "Table Walk" mechanism in the accused processors, or does the term require a distinct software or microcode-based routine not present in the accused architecture?
• A significant procedural question will be the impact of sovereign immunity. Plaintiff's assertion of sovereign immunity from post-grant proceedings raises the question of whether Defendants will be precluded from challenging the validity of the asserted patents at the Patent Trial and Appeal Board, potentially limiting a key defensive strategy and focusing the dispute entirely within the district court.