Vampire Labs LLC v. Advanced Micro Devices Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Vampire Labs, LLC (Texas)
  • Defendant: Advanced Micro Devices, Inc. (Delaware)
  • Plaintiff’s Counsel: Reichman Jorgensen Lehman & Feldberg LLP; DiNovo Price LLP
• Case Identification: 7:25-cv-00533, W.D. Tex., 02/13/2026
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant maintains multiple regular and established places of business in Austin, including a large corporate campus, and employs a significant number of individuals in the district.
• Core Dispute: Plaintiff alleges that Defendant’s CPU and GPU products incorporating fine-grained power management features infringe three patents related to methods for reducing static power dissipation in microprocessor functional units.
• Technical Context: The technology addresses the problem of static power leakage in modern semiconductors, a critical issue for energy efficiency and thermal management as transistor dimensions continue to shrink.
• Key Procedural History: The complaint is a First Amended Complaint, indicating a prior version was filed. For willfulness, the complaint alleges pre-suit knowledge of U.S. Patent No. 9,098,271, citing a USPTO Office Action from August 2017 where an examiner cited the patent during the prosecution of one of Defendant’s own patent applications.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,218,048 - “Individually activating or deactivating functional units in a processor system based on decoded instruction to achieve power saving” (Issued Dec. 22, 2015)

The Invention Explained

• Problem Addressed: As microprocessors become more complex with numerous specialized functional units (FUs), many of these units remain idle for significant periods yet continue to consume power due to static leakage, reducing battery life and increasing heat (’048 Patent, col. 1:50-62).
• The Patented Solution: The patent describes a fine-grained power management system that operates at the instruction-decode stage of a processor’s pipeline ’048 Patent, abstract When an instruction is decoded, a power controller determines precisely which FU is needed to execute it. The controller then powers up only that specific FU for the minimum number of clock cycles required and deactivates it immediately afterward, thereby eliminating both static and dynamic power loss for unused units on a near-instantaneous, instruction-by-instruction basis ’048 Patent, col. 2:10-23
• Technical Importance: This approach allows for more aggressive processor designs with many FUs, as the power penalty for unused components is mitigated without requiring software-level awareness or predictive algorithms that can introduce latency ’048 Patent, col. 2:48-56

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶46
• Essential elements of Claim 1 include:
  • An instruction decoder configured to decode an instruction.
  • A power controller unit coupled to the decoder.
  • A first functional unit coupled to the power controller and decoder.
  • A plurality of switches coupled to the power controller and functional unit, configurable to improve power-up latency by accelerating in-rush current.
  • The power controller is configured to determine the need for the functional unit based on data from the instruction decoder.
  • The power controller activates and deactivates the functional unit, powering it on for the minimal number of clock cycles needed.
  • The functional unit is prevented from incurring static and dynamic power loss when deactivated.
• The complaint reserves the right to assert infringement under the doctrine of equivalents Compl. ¶47

U.S. Patent No. 9,104,416 - “Autonomous microprocessor re-configurability via power gating pipelined execution units using dynamic profiling” (Issued Aug. 11, 2015)

The Invention Explained

• Problem Addressed: In a multitasking operating system, different programs have vastly different needs for a processor's FUs. A "one-size-fits-all" hardware configuration leads to inefficiency, as FUs needed by one program sit idle and leak power while another program is running (’416 Patent, col. 1:40-52).
• The Patented Solution: The invention proposes a method using a performance monitoring unit to dynamically profile the real-time utilization of FUs for each running process ’416 Patent, abstract This utilization data is compared against a threshold to decide whether to power gate an FU. Crucially, the system stores these "specific needs values" in a lookup-table. During an operating system "context switch" (when the processor switches from running one program to another), the pre-profiled needs value for the incoming program is retrieved and used to instantly configure the processor's power-gated FUs, avoiding the need to re-profile each time ’416 Patent, col. 2:50-65
• Technical Importance: This invention allows a processor’s hardware configuration to autonomously and efficiently adapt to the specific workload of different applications in a multitasking environment, improving power efficiency without modifying the instruction stream ’416 Patent, col. 2:63-65

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶62
• Essential elements of Claim 1 include:
  • Using a performance monitoring unit to collect performance data for a first type of functional unit.
  • Determining a utilization level of the functional unit based on that data.
  • Comparing the utilization level to a first threshold.
  • Power gating the functional unit when a first condition (e.g., utilization below the threshold) is satisfied.
  • Updating a configuration register that controls a power switch.
  • Updating a lookup-table, where the configuration register is updated using information from the lookup-table during a context switch to limit startup time.
  • The lookup-table stores specific needs values for multiple processes to permit reuse during each context switch.
• The complaint asserts infringement under the doctrine of equivalents Compl. ¶63

Multi-Patent Capsule

• Patent Identification: U.S. Patent No. 9,098,271, “Autonomous microprocessor re-configurability via power gating pipelined execution units using static profiling,” issued Aug. 4, 2015 Compl. ¶17
• Technology Synopsis: This patent discloses a method for power gating FUs based on static profiling performed during the software compilation process, before the program is executed ’271 Patent, abstract A static code profiler analyzes the software to create a "specific needs profile" that identifies which FUs the program will require. This profile is then used by the target processor's operating system to power gate unneeded FUs when that specific program is running ’271 Patent, col. 2:38-44
• Asserted Claims: At least independent claim 1 Compl. ¶81
• Accused Features: The complaint alleges that AMD's developer tools, such as the ROCProfiler and Radeon GPU Profiler, function as the claimed static code profilers to generate machine executable instructions and determine FU usage Compl. ¶¶83-84

III. The Accused Instrumentality

• Product Identification: The accused products are broad categories of AMD processors, including AMD's product lines with "Zen 3+ and later CPU architectures," corresponding server CPUs, "Baffin and later consumer/gaming GPU architectures," and corresponding data center GPUs Compl. ¶44 The AMD Ryzen 6000 series (using the "Zen 3+" architecture) and products using the RDNA GPU architecture are identified as illustrative examples (Compl. ¶¶48, 64).
• Functionality and Market Context: The complaint alleges these products implement "fine-grained power gating" to manage power consumption Compl. ¶44 For the Zen 3+ architecture, this functionality is allegedly controlled by a System Management Unit (SMU) that enables "per-thread power/clock control," allowing parts of a processor core to remain in a low-power state even when a thread is running (Compl. ¶¶52, 56). The complaint references AMD materials describing features like "New SoC-wide Save-restore Acceleration" for fast transitions between sleep and wake states and "tighter power-gating" Compl. ¶55 Compl. Fig. 048-7 For RDNA GPUs, the complaint points to tools like ROCProfiler as evidence of the ability to monitor performance counters and utilization of the computational pipeline (Compl. ¶¶65, 68).

IV. Analysis of Infringement Allegations

’048 Patent Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: A central issue may be the interpretation of "based on data of the instruction decoder." The court will need to determine if this requires a decision for each individual instruction as it is decoded, or if it can be read more broadly to cover decisions made for a "decoded instruction stream or thread" as alleged in the complaint Compl. ¶56 The distinction between per-instruction and per-thread control could be a focal point of claim construction.
  • Technical Questions: The complaint alleges the accused switches improve latency by "accelerating in-rush current," directly quoting the claim language. However, the supporting evidence cited discusses "hardware assisted acceleration for very fast transitions between sleep and wake" Compl. ¶55 A technical question for the court will be whether the mechanism described by AMD is the same as, or equivalent to, the specific mechanism of accelerating in-rush current recited in the claim.

’416 Patent Infringement Allegations

• Identified Points of Contention:
  • Evidentiary Questions: The complaint heavily relies on the capabilities of the ROCProfiler developer tool to demonstrate infringement. A key question will be whether the functionality described (e.g., collecting performance data, determining utilization) is performed autonomously by the hardware during normal runtime operation as the claim method requires, or if this is merely a diagnostic capability available to developers and not part of the chip's intrinsic power management method.
  • Scope Questions: Does the general process of "dynamic profiling ... for multiple processes" and storing results in memory (Compl. ¶74) meet the specific claim limitation of a "lookup-table" that stores "specific needs values" for "reuse ... during each context switch"? The court may need to construe the term "lookup-table" and determine if the evidence shows the specific structure and OS-level integration for reuse during context switches as described in the patent.

V. Key Claim Terms for Construction

For the ’048 Patent:

• The Term: "based on data of the instruction decoder"
• Context and Importance: This term is central to defining the timing and granularity of the power-gating decision. Practitioners may focus on this term because the complaint’s evidence points to "Per-Thread Power/Clock Control" Compl. ¶56, while the patent specification appears to describe a more granular, per-instruction decision. The outcome of this construction could determine whether AMD's thread-level management falls within the scope of the claim.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language itself does not explicitly say "for a single instruction." One could argue that analyzing a "stream" or "thread" of decoded instructions still constitutes a decision "based on data of the instruction decoder."
  • Evidence for a Narrower Interpretation: The summary states the method "detects when an instruction is about to be issued to a functional unit ... and then powers up the FU shortly before it is needed" ’048 Patent, col. 2:36-40 This language, coupled with the description of powering on for the "minimal number of clock cycles needed to execute the instruction" ’048 Patent, claim 1, suggests a direct, one-to-one link between a single decoded instruction and the power-gating decision.

For the ’416 Patent:

• The Term: "lookup-table stores specific needs values for a plurality of processes after each has been profiled to permit reuse ... during each context switch"
• Context and Importance: This limitation defines the mechanism for making the dynamic profiling efficient in a multitasking environment. The infringement case depends on whether AMD's architecture implements this specific reuse mechanism. The complaint alleges this element is met but provides limited direct evidence of a table structure explicitly used for reuse during an OS context switch.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party could argue that any system that stores profiling data from a process's prior execution and uses it to inform power settings upon a subsequent execution meets the spirit of this limitation, regardless of the specific data structure.
  • Evidence for a Narrower Interpretation: The specification describes a process where a "process tailored hardware configuration is stored in a look up table" and that during a "context switch" the OS or hardware forwards a "configuration profile" to a register ’416 Patent, col. 2:41-44 ’416 Patent, col. 3:3-8 This suggests a specific, structured table indexed by process that is integrated with the OS context switch mechanism, a potentially narrower scope than just storing profiling data.

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement for all three patents-in-suit. The allegations are based on claims that AMD instructs customers on how to use the infringing products through designs, specifications, and technical manuals, and specifically intends for customers to use the infringing "thread-level fine-grained power gating" Compl. ¶¶58-59 Compl. ¶¶77-78 Compl. ¶¶89-90
• Willful Infringement: The complaint alleges willfulness based on AMD’s knowledge of the patents since at least the filing of the original complaint Compl. ¶92 It further alleges pre-suit knowledge of at least the ’271 Patent, providing as evidence a Notice of References Cited from an August 24, 2017 Office Action issued by the USPTO, in which the ’271 Patent was cited against one of AMD's own patent applications Compl. ¶93

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of operational granularity: for the '048 patent, can Plaintiff prove that AMD's "per-thread" power control system operates "based on data of the instruction decoder" in the manner required by the claims, which may be construed to require a per-instruction, rather than a thread-level, analysis?
• A key evidentiary question will be one of runtime implementation versus developer capability: for the '416 patent, does the functionality of AMD's ROCProfiler tool reflect an autonomous, runtime power management system that continuously monitors hardware utilization as claimed, or is it a diagnostic tool separate from the processor's intrinsic, operational method of power management?
• The case presents three distinct patented inventions for power gating—based on static profiling ('271), dynamic profiling ('416), and instruction-decoding ('048). A fundamental question will be one of technical mapping: how do the specific mechanisms within a single accused AMD processor architecture align with these three different and potentially mutually exclusive technical approaches to solving the same underlying problem?