TurboCode LLC v. Itron Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:

  • Plaintiff: TurboCode LLC (Texas)
  • Defendant: Itron, Inc. (Washington)
  • Plaintiff’s Counsel: Direction IP Law

• Case Identification: 7:25-cv-00493, W.D. Tex., 02/16/2026

• Venue Allegations: Venue is based on Defendant allegedly maintaining a regular and established place of business within the Western District of Texas and committing acts of patent infringement in the district.

• Core Dispute: Plaintiff alleges that Defendant’s smart meters and communication modules that comply with 4G/LTE and LTE-M cellular standards infringe a patent related to high-speed, efficient architectures for turbo code decoding.

• Technical Context: Turbo codes are a form of high-performance forward error correction used in modern digital communication standards to ensure reliable data transmission over noisy channels, critical for technologies like 4G/LTE cellular networks.

• Key Procedural History: The patent-in-suit was the subject of an ex parte reexamination proceeding requested in 2006, which concluded in 2009 with the issuance of a Reexamination Certificate. The asserted claim was amended during this proceeding to add limitations intended to distinguish it from prior art.

Case Timeline

Date	Event
2001-01-02	U.S. Patent No. 6,813,742 Priority Date
2004-11-02	U.S. Patent No. 6,813,742 Issue Date
2006-07-13	Reexamination request filed for U.S. Patent No. 6,813,742
2009-02-10	Ex Parte Reexamination Certificate issued for U.S. Patent No. 6,813,742
2026-02-16	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,813,742 - "High Speed Turbo Codes Decoder for 3G Using Pipelined SISO Log-Map Decoders Architecture"

• Patent Identification: U.S. Patent No. 6,813,742, "High Speed Turbo Codes Decoder for 3G Using Pipelined SISO Log-Map Decoders Architecture," issued November 2, 2004 (the "'742 Patent").

The Invention Explained

• Problem Addressed: The patent addresses the challenge of implementing powerful "turbo code" error correction in consumer wireless devices Compl. ¶14 Prior methods, like the Maximum A Posteriori (MAP) algorithm, were highly effective but computationally intensive, requiring complex circuitry that was too slow, costly, and power-hungry for practical use in devices like 3G cellular phones ’742 Patent, col. 2:16-28
• The Patented Solution: The invention proposes a more efficient hardware architecture for a turbo decoder that uses two serially connected Soft-Input-Soft-Output (SISO) Log-MAP decoders operating in a pipelined, iterative fashion ’742 Patent, col. 2:40-48 As shown in the patent's system block diagram, the decoders exchange processed data through dedicated memory modules (an Interleaver and De-Interleaver) in a feedback loop, allowing for iterative refinement of the decoded data while producing an output every clock cycle ’742 Patent, Fig. 4 ’742 Patent, col. 2:54-60 This architecture is designed to simplify implementation in silicon, reduce power consumption, and achieve high data throughput ’742 Patent, col. 2:35-39
• Technical Importance: The described architecture aimed to make high-performance turbo decoding practical for mass-market, power-constrained mobile communication devices, a critical step for enabling high-speed data services over cellular networks Compl. ¶14

Key Claims at a Glance

• The complaint asserts independent claim 6, as amended by the Ex Parte Reexamination Certificate Compl. ¶¶23-24
• The essential elements of asserted method claim 6 include:
  • Providing an input buffer with at least three shift registers to generate three shifted versions of an input signal.
  • Providing first and second soft decision decoders serially coupled in a circular circuit, where each decoder processes output from the preceding one, and where the decoders also receive the different shifted input signals.
  • Providing at least one memory module for each decoder, where the output of the second decoder's memory module is fed back as an input to the first decoder.
  • Processing data using a maximum a posteriori (MAP) probability algorithm or an approximation thereof.
  • Generating a soft decision based on the MAP algorithm.
  • Weighing and storing the soft decision information into the memory module.
  • Performing iterative decoding for a predetermined number of times, with the output of the last decoder fed back to the first decoder in a circular circuit.

III. The Accused Instrumentality

Product Identification

The complaint identifies two categories of accused instrumentalities. The first includes products compliant with the LTE-M standard, such as the "OpenWay Centron Cellular LTE-M Meters" and the "Itron Cellular 500W Module" Compl. ¶¶23-24 The second includes products compliant with the 4G/LTE standard, such as the "OpenWay Riva Socket Based Router" Compl. ¶33

Functionality and Market Context

The accused products are smart utility meters and communication modules that use public cellular networks (LTE-M and 4G/LTE) for data transmission Compl. ¶23 Compl. p. 10 The complaint alleges that to comply with the 3rd Generation Partnership Project (3GPP) standards for these networks, the products must implement turbo coding for error correction Compl. ¶25 The core of the infringement allegation is that the turbo decoding functionality mandated by these standards necessarily performs the method claimed in the ’742 Patent Compl. ¶25 Compl. ¶34 The complaint includes a block diagram from a technical document illustrating a User Equipment (UE) receiver that contains a "Decoding + RM" (Rate Matching) block as part of its data processing chain Compl. p. 13

IV. Analysis of Infringement Allegations

’742 Patent Infringement Allegations

| Claim Element (from Independent Claim 6) | Alleged Infringing Functionality - |
| providing an input buffer comprising at least three shift registers, for receiving an input signal and generating first, second, and third shifted input signals; | The accused products use a data or memory buffer that receives an input signal and performs shifting to generate three delayed copies of the signal for the turbo decoder. - | ¶26 - | col. 4:55-65 - |
| providing first and second soft decision decoders serially coupled in a circular circuit, wherein each decoder processes soft decision from the preceding decoder output data... | The LTE-M specification allegedly describes decoders connected in a loop where each processes the soft decision output from the previous one, creating a circular flow of data. - | ¶27 - | col. 4:8-26 - |
| ...and wherein the first decoder further receives the first and second shifted input signals from the input buffer and the second decoder further receives the third shifted input signal from the input buffer; | The first decoder allegedly receives two shifted versions of the input signal from the buffer, while the second decoder receives a third shifted version, asymmetrically feeding fresh input signals into the decoding loop. - | ¶27 - | col. 4:8-26 - |
| providing at least one memory module coupled to an output of each of the first and second soft decision decoders, wherein the output of the memory module associated with the second soft decision decoder is fed back as an input of the first soft decision decoder; | LTE turbo decoding allegedly involves two sub-decoders where data from the memory connected to the second decoder is sent back and used as input for the first decoder to improve results. - | ¶28 - | col. 4:8-26 - |
| processing systematic information data and extrinsic information data using the maximum a posteriori (AP) probability algorithm, and/or logarithm approximation algorithm; | The accused products, in complying with the LTE-M standard, allegedly use a logarithmic algorithm (MAP or an approximation) to process systematic and extrinsic information data. - | ¶29 - | col. 6:25-33 - |
| generating soft decision based on the maximum a posteriori (MAP) probability algorithm, and/or logarithm approximation algorithm; | The accused products allegedly utilize Soft-Input Soft-Output (SISO) decoders to generate soft decisions based on the MAP probability algorithm. - | ¶30 - | col. 6:33-41 - |
| weighing and storing soft decision information into the corresponding memory module; | The LTE-M decoder allegedly performs rate matching and memory management, which includes weighing decision information (LLRs) and storing it. - | ¶31 - | col. 4:40-47 - |
| performing, for a predetermined number of times, iterative decoding from the first to the last of multiple decoders, wherein an output from the last soft decision decoder is fed back as an input to the first soft decision decoder...and propagate to the last decoder in a circular circuit. | The accused systems allegedly run data repeatedly through a chain of decoders in a loop, where the output of the last decoder is sent back to the first, to refine the data multiple times. The complaint provides a diagram illustrating an iterative decoding procedure with two SISO decoders to support this allegation Compl. p. 58 - | ¶32 - | col. 9:41-49 - |

Identified Points of Contention

• Structural Questions: A primary point of contention may be whether the accused products, by complying with the LTE-M/LTE standards, necessarily implement the specific architecture claimed. For example, the complaint acknowledges that the standard "does not explicitly disclose shift registers" but argues their presence is "implicit" and can be "reasonably inferred" Compl. ¶26 The defense may argue that other buffering mechanisms that are not "shift registers" can satisfy the standard's functional requirements.
• Scope Questions: The interpretation of "serially coupled in a circular circuit" may be a key issue. The defense could contend that modern turbo decoders in LTE chipsets use parallel processing architectures that are structurally different from the two-decoder serial loop depicted in the patent ’742 Patent, Fig. 4, even if the data flow is functionally iterative.

V. Key Claim Terms for Construction

The Term: "input buffer comprising at least three shift registers"

• Context and Importance: This limitation was added during reexamination to distinguish the invention from the prior art Compl. ¶22 Its construction will be critical, as infringement depends on whether the accused products contain this specific structure. Practitioners may focus on this term because the complaint concedes its literal hardware basis is not explicit in the accused standards Compl. ¶26
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent describes the function of the input buffer as storing a block of N input data and providing it as serial streams ’742 Patent, col. 4:55-63 A party could argue that any structure performing this function meets the limitation, with "shift registers" being an exemplary embodiment.
  • Evidence for a Narrower Interpretation: The patent provides a specific diagram, Figure 5, explicitly labeled "Input Buffer Shift Registers" and showing three distinct "N-BIT SHIFT REGISTER" blocks ’742 Patent, Fig. 5 A party will likely argue that this explicit disclosure, combined with its addition during reexamination, limits the term to its specific structural meaning.

The Term: "soft decision decoders serially coupled in a circular circuit"

• Context and Importance: This phrase defines the core architecture of the claimed method. The dispute will likely center on whether the functional data loop in an LTE turbo decoder meets this "serially coupled" structural limitation.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes a functional process where the output of Decoder A is stored and used by Decoder B, and the output of Decoder B is fed back to Decoder A, creating an iterative loop ’742 Patent, col. 4:8-26 This may support a construction where the key is the serial flow of processed information, not necessarily the hardware layout.
  • Evidence for a Narrower Interpretation: Figure 4 of the patent depicts two distinct decoder blocks, A and B, connected sequentially through memory modules ’742 Patent, Fig. 4 A party could argue this requires a specific two-stage serial hardware configuration, not a more complex or parallelized architecture that achieves a similar iterative result.

VI. Other Allegations

Indirect Infringement

The complaint does not provide sufficient detail for analysis of indirect infringement. It does not plead specific facts alleging knowledge of the patent and intent to encourage infringement.

Willful Infringement

The complaint does not provide sufficient detail for analysis of willful infringement. It does not contain allegations of pre-suit knowledge or egregious conduct. The only mention of notice is an allegation of constructive notice by operation of law Compl. ¶43

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of claim construction and proof: Can the plaintiff demonstrate that architectural limitations added during reexamination, such as "at least three shift registers," are present in the accused products, especially when the complaint concedes these structures are not explicitly required by the governing LTE-M standard? The case may depend on whether these terms are given a narrow, structural definition or a broader, functional one.
• A second key question will be structural equivalence: Does the architecture of a modern, standard-compliant LTE turbo decoder, which may employ parallel processing, fall within the scope of the claimed "serially coupled" two-decoder circular circuit? The resolution will likely depend on whether the court focuses on the patent's specific embodiment or the functional description of the iterative data flow between decoding stages.