Daedalus Prime LLC v. Google LLC

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Daedalus Prime LLC (Delaware)
  • Defendant: Google, LLC (Delaware)
  • Plaintiff's Counsel: Blue Peak Law Group
• Case Identification: Daedalus Prime LLC v. Google, LLC, 7:25-cv-00313, W.D. Tex., 07/15/2025
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Google has committed acts of infringement in the district and maintains regular and established places of business, including numerous offices and employees, in Austin and Midland, Texas.
• Core Dispute: Plaintiff alleges that Defendant's Tensor System-on-Chips (SOCs) and Axion microprocessors infringe five U.S. patents, originally invented by Intel, related to microprocessor power management, architecture, and cache coherency.
• Technical Context: The technology at issue involves methods for dynamically managing power and performance across different functional domains within a single processor, a critical function for optimizing efficiency in modern mobile and data center chips.
• Key Procedural History: The complaint notes that U.S. Patent Nos. 8,775,833 and 8,898,494 previously underwent inter partes review (IPR) proceedings, in which the Patent Trial and Appeal Board (PTAB) found that the petitioner failed to establish the unpatentability of a subset of the patents' claims. While not precluding a new validity challenge, this history may be presented by the Plaintiff to suggest the strength of those patents.

Case Timeline

Date	Event
2006-11-17	Google first registered to do business in Texas
2011-09-06	Earliest Priority Date for '833 Patent
2011-12-13	Earliest Priority Date for '228 Patent
2011-12-15	Earliest Priority Date for '494 and '197 Patents
2013-03-11	Earliest Priority Date for '167 Patent
2014-07-08	'833 Patent Issued
2014-11-25	'494 Patent Issued
2015-03-17	'228 Patent Issued
2019-08-06	'197 Patent Issued
2021-10-19	Google announces Tensor G1 SOC
2022-11-22	'167 Patent Issued
2024-04-09	Google announces Axion Processors
2025-07-15	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,775,833 - "Dynamically Allocating a Power Budget Over Multiple Domains of a Processor"

• Patent Identification: U.S. Patent No. 8,775,833, "Dynamically Allocating a Power Budget Over Multiple Domains of a Processor," issued July 8, 2014.

The Invention Explained

• Problem Addressed: The patent does not explicitly state a problem, but the described solution addresses the challenge of managing a finite power budget across different functional units of a modern processor, such as CPU cores and graphics engines, which have varying power needs depending on the workload Compl. ¶17
• The Patented Solution: The patent describes a system where a processor is divided into at least three domains: a first domain (e.g., CPU cores), a second domain (e.g., graphics), and a third domain (e.g., system agent). The third domain includes "power sharing logic" to dynamically allocate a variable power budget between the first and second domains based on stored power sharing values, while the third domain itself operates on a fixed power budget '833 Patent, cl. 13 Compl. ¶17 Figure 8 of the patent illustrates a multiprocessor system with distinct processor cores, graphics, and memory components, embodying this multi-domain concept Compl. ¶19 '833 Patent, Fig. 8
• Technical Importance: This approach allows a processor to shift its power resources to the components that need them most at any given time, improving overall performance and efficiency for diverse computing tasks.

Key Claims at a Glance

• The complaint asserts at least dependent claim 14 Compl. ¶42, which depends on independent claim 13.
• Independent Claim 13 recites a system comprising:
  • A multicore processor with a first domain (plurality of cores), a second domain (graphics engine), and a third domain (system agent circuitry).
  • The third domain operates at a fixed power budget.
  • The third domain includes a power sharing logic to dynamically allocate a variable power budget between the first and second domains.
  • The allocation is based at least in part on a first power sharing value (for the first domain) and a second power sharing value (for the second domain) stored in respective first and second storages.
  • A dynamic random access memory (DRAM) coupled to the processor.
• The complaint does not explicitly reserve the right to assert other claims but makes general allegations covering one or more claims of the patent Compl. ¶42

U.S. Patent No. 8,898,494 - "Power Budgeting Between a Processing Core, A Graphics Core, And a Bus on an Integrated Circuit When a Limit Is Reached"

• Patent Identification: U.S. Patent No. 8,898,494, "Power Budgeting Between a Processing Core, A Graphics Core, And a Bus on an Integrated Circuit When a Limit Is Reached," issued November 25, 2014.

The Invention Explained

• Problem Addressed: The patent addresses the need for efficiently balancing performance and power consumption between different processing elements on an integrated circuit, particularly when operating under a thermal or power limit Compl. ¶22 '494 Patent, abstract
• The Patented Solution: The invention is a processor with workload monitors for both a processing core and a communication bus. It includes "balancing control" logic that dynamically adjusts power allocation between the core and the bus. This adjustment is based on a comparison of the bus workload to a threshold and an overall power limit for the chip, which corresponds to the maximum thermal dissipation capacity. The system ensures that any power reduction is limited to maintain operation above a "low limit" '494 Patent, cl. 1 Figure 6 illustrates a power management module receiving inputs from workload monitors for GPU and CPU cores to make power balancing decisions Compl. ¶24 '494 Patent, Fig. 6
• Technical Importance: This method provides a mechanism to make intelligent power-throttling decisions based on the real-time activity of specific components, rather than applying uniform power reductions.

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶54
• Independent Claim 1 recites a processor comprising an integrated circuit that includes:
  • A first core, a cache memory, and a communication bus coupling the two.
  • A core workload monitor and a bus workload monitor.
  • "Balancing control" adapted to receive the bus workload and dynamically tune power allocation between the core and bus.
  • The tuning is based on a power limit (corresponding to maximum thermal dissipation) and a comparison between the bus workload and a bus workload threshold.
  • When power consumption of the core or bus is reduced, the reduction is limited to maintain operation above a "low limit."
• The complaint does not explicitly reserve the right to assert other claims but makes general allegations covering one or more claims of the patent Compl. ¶54

Multi-Patent Capsules

• Patent Identification: U.S. Patent No. 10,372,197, "User Level Control of Power Management Policies," issued August 6, 2019.

• Technology Synopsis: The patent describes a processor with a power controller that receives workload configuration inputs and multiple energy performance bias (EPB) values. Based on these inputs, it determines a "global EPB value" and updates power management settings, allowing for user-level or OS-level influence over power policies Compl. ¶27

• Asserted Claims: Independent claim 1 Compl. ¶66

• Accused Features: The complaint alleges that Google's Tensor SOCs and Axion microprocessors, which feature sophisticated power management control systems, infringe the '197 Patent Compl. ¶66

• Patent Identification: U.S. Patent No. 8,984,228, "Providing Common Caching Agent for Core and Integrated Input/Output (IO) Module," issued March 17, 2015.

• Technology Synopsis: The patent addresses problems that arise when an I/O component is integrated onto the same chip as a multiprocessor Compl. ¶32 It proposes an apparatus with a single, common caching agent, distributed across the cores, to handle cache coherency operations for both the processor cores and an integrated input/output (IIO) module, reducing snoop traffic Compl. ¶32 '228 Patent, abstract

• Asserted Claims: Independent claim 1 Compl. ¶78

• Accused Features: The complaint alleges that Google's Tensor SOCs and Axion microprocessors, which integrate CPU cores and I/O functions, infringe the '228 Patent Compl. ¶78

• Patent Identification: U.S. Patent No. 11,507,167, "Controlling Operating Voltage of a Processor," issued November 22, 2022.

• Technology Synopsis: The patent describes a method for managing multi-phase voltage ramps in a processor to reduce latency when a core exits a low-power state Compl. ¶37 A power control unit handles requests to alter a core's operating state by first increasing voltage to an interim "safe" level, allowing another core to become active, and only then increasing the voltage to the final, higher level Compl. ¶38

• Asserted Claims: Independent claim 1 Compl. ¶90

• Accused Features: The complaint alleges that Google's Tensor SOCs and Axion microprocessors, which employ multi-stage power state transitions, infringe the '167 Patent Compl. ¶90

III. The Accused Instrumentality

Product Identification

• The accused instrumentalities are Google's Tensor SOCs (including G1, G2, G3, and G4) and Google's Axion microprocessors Compl. ¶8

Functionality and Market Context

• The complaint identifies the Tensor SOCs as the custom processors used in Google's Pixel mobile phones, designed for machine learning and other advanced mobile computing tasks Compl. ¶8 The Axion microprocessors are identified as Google's custom Arm-based CPUs for data centers Compl. ¶8 Plaintiff alleges these products incorporate groundbreaking microprocessor circuitry for power management and have particular application in smartphones, tablets, and data center products Compl. ¶14 The complaint includes a screenshot from a Google blog post announcing the Axion processors, highlighting their role in powering Google's cloud services Compl. p. 4

IV. Analysis of Infringement Allegations

'833 Patent Infringement Allegations

Claim Element (from Independent Claim 13)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a multicore processor having a first domain including a plurality of cores, a second domain including a graphics engine, and a third domain including system agent circuitry...	The complaint alleges Google's Tensor SOCs are multicore processors that include a CPU domain (plurality of ARM Cortex cores), a GPU domain (graphics engine), and a System Control Processor that acts as the system agent circuitry (Doc. 1-6, p. 5).	¶¶18-19; ¶42	col. 10:31-57
the third domain to operate at a fixed power budget and including a power sharing logic to dynamically allocate a variable power budget between the first and second domains...	The complaint alleges the System Control Processor (SCP) in Tensor SOCs operates at a fixed power budget and comprises power sharing logic to manage power across different domains, including the CPU and GPU (Doc. 1-6, pp. 5-8). A diagram from an ARM specification document is provided to show a System Control Processor managing Power Policy Units for different domains (Doc. 1-6, p. 8).	¶¶18-19; ¶42	col. 4:55-67
...based at least in part on a first power sharing value for the first domain stored in a first storage and a second power sharing value for the second domain stored in a second storage; and	The complaint alleges the SCP and associated Power Policy Units (PPUs) dynamically allocate a variable power budget based on stored values that represent power sharing policies (Doc. 1-6, p. 8; Doc. 1-6, p. 14).	¶¶18-19; ¶42	col. 5:25-42
a dynamic random access memory (DRAM) coupled to the multicore processor.	The complaint alleges the Tensor SOCs are coupled to LPDDR5 memory, a type of DRAM (Doc. 1-6, p. 12).	¶¶18-19; ¶42	col. 10:47-50

• Identified Points of Contention:
  • Scope Questions: A central dispute may be whether the "System Control Processor" (SCP) and "Power Policy Units" (PPUs) in the accused ARM-based architecture, as alleged by the Plaintiff, collectively constitute the claimed "power sharing logic." A court may need to determine if the claim requires a single, monolithic logic block or if it can read on a distributed system of controllers and policy units.
  • Technical Questions: The analysis may turn on whether the accused SCP is part of a "third domain" that operates at a "fixed power budget" as required by the claim. Evidence will be needed to establish the power characteristics of the SCP relative to the CPU and GPU domains.

'494 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
an integrated circuit including: a first core; a cache memory; a communication bus coupled to the first core...	The complaint alleges Google's Axion and Tensor SOCs are integrated circuits containing multiple CPU cores, cache memory, and a communication bus (e.g., CMN-700 mesh network) (Doc. 1-7, pp. 3-7).	¶23; ¶54	col. 11:48-52
a core workload monitor configured to determine a core workload for the first core; a bus workload monitor configured to determine a bus workload for the communication bus;	The complaint alleges that the accused Axion processors use a System Control Processor (SCP) that manages power for the entire system and uses workload monitors to determine core and bus workloads (Doc. 1-7, p. 12).	¶23; ¶54	col. 11:60-67
balancing control adapted to receive the bus workload from the bus workload monitor and to dynamically tune power allocation between the first core and the communication bus...	The complaint alleges the SCP and associated Power Policy Units (PPUs) in the accused products constitute "balancing control" that tunes power allocation between the core and bus (Doc. 1-7, pp. 15-18). A diagram illustrating the function of PPUs is provided (Doc. 1-7, p. 19).	¶23; ¶54	col. 12:20-41
...based on a power limit for the integrated circuit and a comparison between the bus workload and a bus workload threshold...	The complaint alleges the accused products use "intelligent power allocation" (IPA) which considers the "thermal envelope" (the power limit) and compares device workloads against demands to allocate power, which it equates to the claimed comparison (Doc. 1-7, pp. 25-26).	¶23; ¶54	col. 12:20-41
...wherein a power consumption of one of the first core and the communication bus is to be reduced, the power consumption reduction to be limited to maintain operation of the one of the first core and the communication bus above a low limit.	The complaint alleges that the ARM Power Policy Unit architecture allows for static and dynamic power mode transitions, including setting a "minimum power mode," which it equates to the claimed "low limit" that ensures continued operation (Doc. 1-7, pp. 26-27).	¶23; ¶54	col. 12:47-51

• Identified Points of Contention:
  • Scope Questions: A key issue will be whether the accused products' complex, policy-driven power management system (which uses IPA, SCPs, and PPUs) performs the specific function of a "comparison between the bus workload and a bus workload threshold" as recited in the claim, or if its operation is materially different.
  • Technical Questions: It may be disputed whether the "minimum power mode" in the ARM architecture functions as the claimed "low limit" to "maintain operation." The defense may argue that these are functionally distinct concepts, one being a policy floor and the other a hardware-level operational necessity.

V. Key Claim Terms for Construction

'833 Patent

• The Term: "power sharing logic"
• Context and Importance: This term is the central active element of claim 13. Its construction will determine whether Google's distributed power control architecture, which uses a System Control Processor and Power Policy Units, falls within the scope of the claim. Practitioners may focus on this term because the infringement theory hinges on mapping these modern, complex ARM components onto this claim element.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the logic in functional terms, as a mechanism for determining a power budget and controlling frequency based on allocated portions Compl. ¶17 This functional language may support a construction that is not limited to a specific hardware structure.
  • Evidence for a Narrower Interpretation: Claim 13 recites the "power sharing logic" as being included in the "third domain including system agent circuitry." This locational constraint could support a narrower construction that requires the logic to be physically or logically part of the system agent, potentially excluding a more distributed control plane.

'494 Patent

• The Term: "balancing control"
• Context and Importance: This is the functional heart of claim 1, defining the logic that tunes power allocation. The case may turn on whether the accused products' multi-faceted power management system, which considers numerous factors, meets the claim's more specific requirement of being based on a "comparison between the bus workload and a bus workload threshold."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent's abstract describes the invention broadly as a "method for efficiently balancing performance and power" Compl. ¶22 This could support a construction covering any logic that achieves this functional goal.
  • Evidence for a Narrower Interpretation: The claim language is specific: the "balancing control" must be "adapted to... tune... based on... a comparison between the bus workload and a bus workload threshold" '494 Patent, cl. 1 This suggests the control logic must perform this specific comparison, which could be argued to be different from the more holistic, policy-based decision-making alleged to occur in the accused products' Intelligent Power Allocation systems.

VI. Other Allegations

• Indirect Infringement: The complaint alleges Google induces infringement by supplying the Accused Products to consumers and "instructing and encouraging such customers to use the Accused Products in the ordinary, customary, and intended way," which Google allegedly knew was infringing Compl. ¶44 Compl. ¶56 Compl. ¶68 Compl. ¶80 Compl. ¶92 Contributory infringement is also alleged on the basis that the accused components are especially made for use in an infringing manner and are not staple articles of commerce Compl. ¶46 Compl. ¶58 Compl. ¶70 Compl. ¶82 Compl. ¶94
• Willful Infringement: Plaintiff alleges that Google's infringement "has been and continues to be deliberate, intentional, and willful" based on knowledge of the patents "at a minimum... as of the filing of this Complaint" Compl. ¶49 Compl. ¶61 Compl. ¶73 Compl. ¶85 Compl. ¶97 This appears to be a claim for post-suit willfulness.

VII. Analyst's Conclusion: Key Questions for the Case

1. Claim Construction and Architectural Mismatch: A central issue will be whether the asserted claims, which describe specific logical structures like a "power sharing logic" ('833 Patent) or "balancing control" based on a direct "comparison" ('494 Patent), can be construed to cover the complex, distributed, and policy-driven power management architectures (e.g., SCP, PPU, IPA) used in Google's modern ARM-based processors. The case will likely feature a battle of experts on the functional and structural equivalence between the claimed inventions and the accused systems.

2. Impact of Prior IPRs: Plaintiff highlights that claims of the '833 and '494 patents survived IPR challenges. A key question is how the court and a jury will weigh this procedural history. While it does not immunize the patents from invalidity arguments on other grounds, it may be used by the Plaintiff as a persuasive indicator of the patents' strength and validity.

3. Evidentiary Sufficiency: The complaint relies heavily on public documentation from Google and ARM to build its infringement case. The dispute may turn on whether this public-facing technical information is sufficient to prove that the accused products operate in a manner that meets every limitation of the asserted claims, or if discovery will reveal operational details that distinguish the products from the claimed inventions.