Ascale Tech LLC v. Intel Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Ascale Technologies LLC (Texas)
  • Defendant: Intel Corporation (Delaware)
  • Plaintiff's Counsel: The Mort Law Firm, PLLC
• Case Identification: 7:25-cv-00273, W.D. Tex., 11/03/2025
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant Intel is registered to do business in Texas, has transacted business in the district, has committed alleged acts of infringement in the district, and maintains a regular and established place of business at a facility in Austin, Texas.
• Core Dispute: Plaintiff alleges that Defendant's microprocessors, FPGAs, and photonic integrated circuits infringe five U.S. patents related to power management, dynamic voltage and temperature compensation, thread scheduling, and optical communications.
• Technical Context: The technologies at issue relate to the fundamental design and operation of modern, high-performance integrated circuits, addressing efficiency, reliability, and data throughput in complex System-on-Chip (SoC) devices.
• Key Procedural History: The currently operative complaint is a First Amended Complaint, filed following an original complaint on June 16, 2025. Plaintiff states the asserted patents were developed by Freescale Semiconductor and SigmaTel, companies it identifies as former direct competitors to Intel. Plaintiff has dismissed claims for pre-suit indirect infringement and willfulness without prejudice, but maintains claims for post-suit indirect and willful infringement.

Case Timeline

Date	Event
2006-02-15	'266 Patent Priority Date
2006-02-27	'991 Patent Priority Date
2008-01-22	'165 Patent Priority Date
2009-02-10	'266 Patent Issue Date
2010-03-08	'136 Patent Priority Date
2011-05-31	'991 Patent Issue Date
2013-06-10	'135 Patent Priority Date
2014-05-27	'165 Patent Issue Date
2014-06-24	'136 Patent Issue Date
2015-07-28	'135 Patent Issue Date
2025-06-16	Original Complaint Filing Date
2025-11-03	First Amended Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,490,266 - Integrated Circuit and Processing System with Improved Power Source Monitoring and Methods For Use Therewith

The Invention Explained

• Problem Addressed: The patent's background section describes how interruptions in power supplied to portable electronic devices, such as from a low battery, can cause the device to "hang-up, crash or otherwise malfunction" '266 Patent, col. 1:27-31
• The Patented Solution: The invention is a processing system that includes a power monitor circuit. This circuit monitors the power source and, upon detecting an error condition (e.g., low voltage), can power down the processing module and memory module in an "organized fashion" to prevent a crash '266 Patent, col. 2:35-41 The system can also use a software-based routine to monitor for a second error condition and disable the hardware monitor circuit. The architecture is depicted in the patent's Figure 4, showing a power monitor circuit (120) coupled to a power source (110) and a processing module (100) '266 Patent, FIG. 4
• Technical Importance: The technology provides a mechanism for graceful power-down sequences in battery-operated devices, enhancing system stability and preventing data corruption during power-loss events.

Key Claims at a Glance

• The complaint asserts at least dependent claim 23 Compl. ¶23, which depends from independent method claim 21.
• The complaint's description of the infringing method includes the following essential steps Compl. ¶23:
  • Powering up a power source in response to a user event to provide power to a processing module.
  • Monitoring the power source using an on-chip power monitor circuit.
  • Powering down the power source and the processing module from the on-chip power monitor circuit when a first error condition is detected.

U.S. Patent No. 7,953,991 - Processing System and Methods for use Therewith

The Invention Explained

• Problem Addressed: The patent addresses the need for handheld devices with memory circuits to operate reliably over a wide range of environmental temperatures '991 Patent, col. 1:29-37
• The Patented Solution: The invention describes a system where a controller module receives a temperature signal and adjusts a target voltage for a memory module in response '991 Patent, abstract Specifically, it increases the source voltage to the memory module when the temperature is either below a first, colder threshold or above a second, hotter threshold, and maintains a steady voltage between those thresholds '991 Patent, col. 2:3-16 This compensates for performance variations in memory at temperature extremes.
• Technical Importance: This method of dynamic voltage adjustment based on temperature improves the operational reliability of memory systems in devices exposed to varying thermal conditions.

Key Claims at a Glance

• The complaint asserts at least independent claim 13 Compl. ¶36
• The essential elements of independent claim 13 include:
  • Receiving a temperature signal.
  • Making a first comparison between the signal and a first temperature threshold.
  • Making a second comparison between the signal and a second, higher temperature threshold.
  • Adjusting a source voltage to a memory module by increasing it when the temperature is below the first threshold or above the second threshold.
  • Maintaining the source voltage at a current level when the temperature is between the two thresholds.

U.S. Patent No. 8,739,165

• Patent Identification: U.S. Patent No. 8,739,165, Shared Resource Based Thread Scheduling with Affinity and/or Selectable Criteria, issued May 27, 2014.
• Technology Synopsis: The patent addresses the problem of efficiently scheduling software threads on multi-core processors. The solution is a method that first checks if a thread has an "affinity" for a particular core (based on recent cache activity) and, if so, assigns it there. If no affinity exists, the system chooses a core to either minimize the number of active devices (to save power) or maximize the number of active devices (to boost performance) '165 Patent, abstract Compl. ¶51
• Asserted Claims: At least independent claim 1 Compl. ¶51
• Accused Features: The complaint accuses Intel products that incorporate Intel Thread Director, including 12th, 13th, and 14th Generation Intel Core Processors Compl. ¶19 Compl. ¶50

U.S. Patent No. 9,094,135

• Patent Identification: U.S. Patent No. 9,094,135, Die Stack with Optical TSVs, issued July 28, 2015.
• Technology Synopsis: The patent addresses bandwidth and power limitations in stacked integrated circuits (3D-ICs). The invention describes using an on-die laser source to generate an unmodulated light beam, which is transmitted via optical routing structures (such as Through-Silicon Vias) to a modulator on a receiving die. The receiving die then modulates the light beam with data, enabling high-speed, low-power, inter-die communication '135 Patent, abstract Compl. ¶65
• Asserted Claims: At least independent claim 13 Compl. ¶65
• Accused Features: The complaint accuses Intel Photonic Integrated Circuits (PIC) and products using its Optical Compute Interconnect (OCI) technology Compl. ¶19 Compl. ¶64

U.S. Patent No. 8,760,136

• Patent Identification: U.S. Patent No. 8,760,136, Dynamic Voltage Scaling Interface, issued June 24, 2014.
• Technology Synopsis: The patent addresses latency issues in dynamic voltage scaling (DVS) systems, which can lead to power waste or performance degradation. The solution is a method that monitors a DVS signal, assesses the time the signal is in a particular state by counting clock edges, and provides a real-time adjustment signal to a power supply based on that assessment. This allows for faster and more precise voltage adjustments '136 Patent, abstract Compl. ¶78
• Asserted Claims: At least independent claim 1 Compl. ¶78
• Accused Features: The complaint accuses Intel products that implement DVS and/or Dynamic Voltage and Frequency Scaling (DVFS), such as Intel 12th Generation processors Compl. ¶77 Compl. ¶79

III. The Accused Instrumentality

Product Identification

• The complaint names several categories of Intel products:
  • For the '266 Patent: Intel microprocessors with Fully Integrated Voltage Regulators (FIVR) Compl. ¶22
  • For the '991 Patent: Intel Agilex 5 Series FPGAs and SoCs Compl. ¶35
  • For the '165 Patent: Intel Core Processors (12th, 13th, and 14th Gen) with Intel Thread Director Compl. ¶50
  • For the '135 Patent: Intel Photonic Integrated Circuits (PIC) and Optical Compute Interconnect (OCI) with PIC Compl. ¶64
  • For the '136 Patent: Intel products implementing dynamic voltage scaling (DVS) or DVFS Compl. ¶77

Functionality and Market Context

• The complaint alleges that FIVR is a key technology in Intel's 4th generation Core microprocessors and beyond, enabling a significant increase in battery life for mobile products by integrating voltage regulators directly onto the processor die Compl. p. 8 A diagram from wccftech.com illustrates how FIVR technology consolidates multiple platform voltage regulators into a single on-die solution, simplifying power delivery design Compl. p. 9
• For the '991 Patent, the complaint alleges that Intel's Agilex 5 devices use a "SmartVID" feature to perform dynamic voltage adjustments based on temperature readings from on-chip sensors Compl. ¶38 This feature is allegedly managed by a Secure Device Manager (SDM) Power Manager to compensate for performance degradation at different temperatures Compl. ¶16 Compl. ¶39

IV. Analysis of Infringement Allegations

'266 Patent Infringement Allegations

Claim Element (from method described in Compl. ¶23)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
powering up a power source in response to a user event to thereby provide power to a processing module of an integrated circuit;	Intel microprocessors with FIVR integrate voltage regulators that manage power delivery to processor cores (processing modules) located on the same die.	¶24	col. 2:8-12
monitoring the power source using an on-chip power monitor circuit of the integrated circuit;	The on-chip Power Control Unit (PCU) in Intel microprocessors with FIVR receives data from monitors for voltage, current, and temperature to optimize power settings.	¶25	col. 2:17-21
and powering down the power source and the processing module from the on-chip power monitor circuit when a first error condition is detected in the power source.	Intel's voltage regulators allegedly detect when input voltage is outside the normal range (an error condition) and shut down, a function described in Intel's documentation for Under-Voltage Lockout (UVLO).	¶¶25-26	col. 2:21-28

• Identified Points of Contention:
  • Scope Question: The complaint asserts claim 23, but the infringement theory described in paragraph 23 does not match the elements of claim 23 or its parent claim 21, which involve software routines and disabling a monitor circuit. The provided theory aligns more closely with the general operation of the system described in the patent's abstract and system claim 1. This discrepancy raises the question of which claim language truly governs the infringement analysis.
  • Technical Question: Does Intel's Under-Voltage Lockout (UVLO) feature, which appears to be an automatic hardware safety mechanism, perform the claimed function of "monitoring the power source using an on-chip power monitor circuit" that "powers down the processing module"? The analysis may focus on whether this automated shutdown is equivalent to the "organized fashion" of powering down taught by the patent '266 Patent, col. 2:38-39

'991 Patent Infringement Allegations

Claim Element (from Independent Claim 13)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
receiving a temperature signal;	Intel Agilex 5 devices contain "on-chip voltage and temperature sensors."	¶37	col. 3:9-12
making a first comparison between the temperature signal and a first temperature threshold;	Agilex 5 devices are alleged to compensate for performance at "colder temperatures by raising the voltage," with the SDM Power Manager checking if the temperature "crosses the threshold point."	¶38	col. 3:13-19
making a second comparison between the temperature signal and a second temperature threshold that is greater than the first temperature threshold;	The complaint alleges Agilex 5 devices also manage performance at "hot temperature" by comparing against a second, higher threshold.	¶39	col. 3:20-27
adjusting a source voltage to a memory module in response to the first comparison and the second comparison, by increasing the source voltage when the temperature signal indicates that a temperature is either below the first temperature threshold or above the second temperature threshold;	The "SmartVID" feature in Agilex 5 devices is alleged to perform "dynamic voltage adjustment" by updating the VID value when the temperature crosses a threshold, as shown in a graph provided in the complaint. A graph titled 'Temperature Compensation for SmartVID' illustrates how the VID Value (voltage) is adjusted in steps as the temperature crosses various thresholds Compl. p. 19	¶40	col. 3:32-41
and maintaining the source voltage at a current level when the temperature signal indicates that the temperature of the memory module is between the first and second temperature thresholds.	The complaint alleges that in Agilex 5 devices, "dynamic voltage adjustment does not occur if the temperature remains within 20 +/- 5 degrees."	¶41	col. 3:41-46

• Identified Points of Contention:
  • Applicability Question: A central question will be whether the alleged "dynamic voltage adjustment" in the accused Agilex 5 SoCs is being supplied to a memory module as required by claim 13. The defense may argue that the voltage scaling is a general adjustment for the entire logic fabric of the SoC, not specifically for the memory components, and thus falls outside the claim scope.
  • Technical Question: Does the accused "SmartVID" feature, which adjusts voltage in discrete steps (e.g., 5 mV) as temperature crosses a threshold, meet the claim limitation of increasing voltage "as a function of the difference" between the temperature and the threshold, which could imply a proportional or more continuous relationship? '991 Patent, claim 7

V. Key Claim Terms for Construction

For the '266 Patent:

• The Term: "on-chip power monitor routine" (from claim 21, the independent claim from which asserted claim 23 depends).
• Context and Importance: The complaint's infringement theory relies on Intel's FIVR and its associated power control circuitry (e.g., PCU, UVLO) meeting this limitation Compl. ¶25 Compl. ¶26 Practitioners may focus on this term because its construction will determine whether a hardware-based safety circuit like UVLO can be considered a "routine," a term that often implies a sequence of software or firmware instructions.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation (Hardware included): The patent specification states that the processing module can be implemented in various ways, including "logic circuitry, analog circuitry, digital circuitry" '266 Patent, col. 2:65-67, which may support an argument that a "routine" can be implemented purely in hardware.
  • Evidence for a Narrower Interpretation (Software/Firmware required): The patent repeatedly discusses the "power monitor routine" as a set of "operational instructions" executed by the "processing module" '266 Patent, col. 2:51-54 '266 Patent, FIG. 5, suggesting it is a software or firmware function distinct from the hardware-only "power monitor circuit" (120) also described.

For the '991 Patent:

• The Term: "memory module"
• Context and Importance: The entirety of asserted claim 13 is directed to adjusting voltage supplied to a memory module. The accused products are Intel Agilex 5 FPGAs and SoCs Compl. ¶35 The case may turn on whether the alleged voltage adjustments are made specifically to the memory elements within the SoC.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent states the memory module could be various types, including "cache memory" '991 Patent, col. 2:51-52, which is commonly integrated within SoCs. This could support an argument that embedded memory blocks within an FPGA or SoC qualify as the claimed "memory module."
  • Evidence for a Narrower Interpretation: The patent's background and figures consistently depict the "memory module" as a distinct functional block from the "processing module," often in the context of systems with discrete components like DRAM or SRAM '991 Patent, FIG. 1 '991 Patent, col. 1:17-25 This could support an argument that the term refers to a primary system memory component, not just incidental embedded memory within a larger logic device.

VI. Other Allegations

• Indirect Infringement: For all asserted patents, the complaint alleges both induced and contributory infringement. Inducement is based on allegations that Intel provides customers with technical documentation, product manuals, and support that instruct and encourage use of the accused products in an infringing manner (e.g.,Compl. ¶28; Compl. ¶29). Contributory infringement is based on allegations that the accused components are material to the inventions, are not staple articles of commerce, and are especially made or adapted for infringing use (e.g., Compl. ¶30; Compl. ¶45).
• Willful Infringement: The complaint alleges willful infringement based on Intel's continued alleged infringement after receiving notice of the patents via the original complaint, filed on June 16, 2025 Compl. ¶18 Plaintiff explicitly states it is not asserting pre-suit willfulness at this time Compl. ¶18, fn. 1

VII. Analyst's Conclusion: Key Questions for the Case

• The Specificity of Function: A primary issue across several of the asserted patents will be one of functional specificity. The case will likely test whether Intel's general-purpose, system-level optimization technologies (e.g., FIVR for power management, SmartVID for thermal compensation, Thread Director for scheduling) perform the specific, multi-step methods recited in the claims, which were patented to solve discrete, well-defined problems. The court will need to determine if there is a genuine technical correspondence or a mismatch in operational method.
• The Scope of a "Module": For the '991 patent concerning temperature-based voltage scaling, a key question will be one of definitional scope. Can the term "memory module," which in the patent's context appears to refer to a primary memory component, be construed to read on the integrated memory blocks embedded within the complex logic fabric of an accused FPGA/SoC? The outcome may depend on whether evidence shows the accused voltage adjustments are targeted specifically for those memory elements.
• Hardware vs. Software Implementation: For the '266 patent concerning power-down protocols, the dispute may center on the meaning of "routine." A central question will be whether a hardware-based safety feature, such as an under-voltage lockout circuit, can satisfy a claim limitation that arguably implies a software or firmware-based sequence of instructions. This will likely be a key issue for claim construction.