Redstone Logics LLC v. Apple Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Redstone Logics LLC (Texas)
  • Defendant: Apple Inc. (California)
  • Plaintiff's Counsel: Russ August & Kabat
• Case Identification: 7:25-cv-00183, W.D. Tex., 07/14/2025
• Venue Allegations: Plaintiff alleges venue is proper because Defendant transacts business in the district and maintains regular and established places of business in Austin, Texas.
• Core Dispute: Plaintiff alleges that Defendant's Apple M-series and A-series Systems on a Chip (SoCs) infringe a patent related to methods for managing power and communication between different groups of cores in a multi-core processor.
• Technical Context: The technology addresses heterogeneous computing architectures, where processors use a mix of high-performance and high-efficiency cores to balance computational power with energy consumption, a critical design consideration for modern mobile and portable devices.
• Key Procedural History: The filing is a First Amended Complaint. The complaint does not mention any prior litigation, licensing history, or post-grant proceedings related to the patent-in-suit.

Case Timeline

Date	Event
2010-02-26	'339 Patent Priority Date
2013-10-01	'339 Patent Issue Date
2025-07-14	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

• Patent Identification: U.S. Patent No. 8,549,339 ("Processor core communication in multi-core processor"), issued October 1, 2013 (the "'339 Patent").

The Invention Explained

• Problem Addressed: The patent addresses the inefficiency of conventional multi-core processors where all cores generally share the same supply voltage and clock signal, which limits opportunities for granular power management '339 Patent, col. 1:7-14
• The Patented Solution: The invention describes a multi-core processor architecture where cores are grouped into different sets (termed "stripes" in an embodiment) '339 Patent, col. 2:23-26 Each set can operate with its own independent supply voltage and an independent clock signal from a dedicated phase-lock loop (PLL) '339 Patent, col. 7:52-8:1 This allows, for example, one set of cores to run at high frequency and voltage for demanding tasks while another set runs at a lower, more power-efficient state for background tasks '339 Patent, col. 2:51-60 An "interface block" is used to manage communication between these different voltage and clock domains '339 Patent, col. 8:2-7
• Technical Importance: This approach enables more sophisticated dynamic voltage and frequency scaling (DVFS) at a sub-processor level, improving power efficiency without sacrificing peak performance, which is crucial for battery-powered devices.

Key Claims at a Glance

• The complaint asserts independent claim 1 Compl. ¶10
• The essential elements of independent claim 1 are:
  • A first set of processor cores configured to dynamically receive a first supply voltage and a first output clock signal from a first PLL.
  • A second set of processor cores configured to dynamically receive a second supply voltage and a second output clock signal from a second PLL, where the first supply voltage and first clock signal are independent from the second.
  • An interface block coupled to both sets of cores, configured to facilitate communication between them.
• The complaint notes that claims 1, 5, 8, 9, 10, 14, and 21 are infringed Compl. Ex. 2, p. 2, reserving the right to assert the listed dependent claims.

III. The Accused Instrumentality

Product Identification

• The Accused Instrumentalities are certain Apple products containing one or more Systems on a Chip (SoCs) that implement "Firestorm and Icestorm architecture (or similar architecture)," including the Apple M-series SoCs (M1-M4) and Apple A-series SoCs (A10-A18) Compl. ¶8 Compl. Ex. 2, p. 2

Functionality and Market Context

• The complaint alleges that the accused SoCs feature a heterogeneous architecture with two distinct sets of cores: high-performance cores ("p-cores," e.g., Firestorm) and high-efficiency cores ("e-cores," e.g., Icestorm) Compl. Ex. 2, p. 3
• It is alleged that these core sets are grouped into clusters that operate at variable and different frequencies to balance performance and power consumption Compl. Ex. 2, p. 7 The complaint alleges, on information and belief, that these separate clusters receive independent supply voltages and are driven by independent PLLs Compl. Ex. 2, p. 5 Compl. Ex. 2, p. 8
• The complaint identifies Apple's "Unified Memory Architecture" and its "Dispatch" (Grand Central Dispatch) software framework as the "interface block" that facilitates communication between the p-cores and e-cores Compl. Ex. 2, pp. 11-13 The complaint includes a screenshot from an Apple presentation describing the "Unified memory architecture" as accessible to the entire SoC Compl. Ex. 2, p. 12

IV. Analysis of Infringement Allegations

• Claim Chart Summary: The complaint provides a claim chart in Exhibit 2, which maps elements of claim 1 to the functionality of the Accused Instrumentalities Compl. ¶10

'339 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a first set of processor cores... configured to dynamically receive a first supply voltage and a first output clock signal of a first phase lock loop (PLL)...	The "efficiency cores" (e-cores) of the Icestorm architecture, which are alleged to be configured in a set to receive a variable frequency and, on information and belief, a variable first supply voltage from a first PLL.	¶8; Ex. 2, p. 5	col. 2:25-31
a second set of processor cores... configured to dynamically receive a second supply voltage and a second output clock signal of a second PLL... wherein the first supply voltage is independent from the second supply voltage, and the first clock signal is independent from the second clock signal	The "performance cores" (p-cores) of the Firestorm architecture, which are alleged to be configured in a separate set to receive a variable frequency and, on information and belief, an independent second supply voltage from a second PLL. A screenshot from an Apple video highlights the "4 high-performance cores" Compl. Ex. 2, p. 9	¶8; Ex. 2, p. 8	col. 2:25-31
an interface block coupled to the first set of processor cores and also coupled to the second set of processor cores, wherein the interface block is configured to facilitate communication between the first set of processor cores and the second set of processor cores	Apple's Unified Memory Architecture, which provides shared data access, in combination with its "Dispatch" (Grand Central Dispatch) software framework, which manages concurrent code execution across the different cores.	¶8; Ex. 2, pp. 11-13	col. 2:8-12

• Identified Points of Contention:
  • Scope Questions: A central question may be whether the claimed "interface block" can be construed to cover the combination of a hardware memory architecture and a software-based task scheduler (Grand Central Dispatch) as alleged by the Plaintiff Compl. Ex. 2, pp. 11-13 The patent's specification describes hardware embodiments for the interface block, such as level shifters and synchronizers '339 Patent, Figs. 2-3, which may suggest a narrower, purely hardware-based construction.
  • Technical Questions: The complaint's allegations regarding independent supply voltages and dedicated PLLs for each core set are made "on information and belief," with the acknowledgment that the "precise mechanism... is proprietary information of Apple" Compl. Ex. 2, p. 5 Compl. Ex. 2, p. 8 A key point of contention will likely be whether discovery can produce evidence that the accused SoCs actually implement the specific, independent power and clocking architecture required by the claim.

V. Key Claim Terms for Construction

• The Term: "interface block"

• Context and Importance: The definition of this term is critical. If construed narrowly to require a specific hardware structure like those disclosed in the patent's embodiments, the Plaintiff's infringement theory, which relies on a combination of hardware memory and system-level software, may face challenges. If construed broadly based on its function-"to facilitate communication"-the Plaintiff's theory may be more viable. Practitioners may focus on this term because of the potential mismatch between the patent's hardware-centric examples and the complaint's allegations of a hardware-software combination.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The claim language itself is functional: "an interface block... configured to facilitate communication" '339 Patent, col. 8:2-7 This language does not, on its face, limit the structure of the block.
  • Evidence for a Narrower Interpretation: The specification provides specific hardware examples, stating that the interface block may have a "level shifter" or a "synchronizer" to manage signals between different voltage or clock domains '339 Patent, col. 3:31-33 '339 Patent, col. 4:5-8 A defendant could argue these embodiments define the scope of the term.

• The Term: "set of processor cores"

• Context and Importance: The patent's primary embodiment describes these "sets" as "stripes" that correspond to physical "rows" in a 2-D processor array '339 Patent, col. 2:23-26 The accused products group cores by function (performance vs. efficiency) into "clusters" Compl. Ex. 2, p. 7 The case may depend on whether Apple's functional grouping of cores qualifies as a "set" under the claim.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The claim uses the general term "set" rather than the more specific term "stripe" or "row" used in the detailed description, which may support a construction not limited to a specific physical layout.
  • Evidence for a Narrower Interpretation: A defendant may argue that the consistent use of "stripes" and "rows" to describe the core groupings in the specification '339 Patent, col. 2:23-40 limits the term "set" to the physical arrangements disclosed.

VI. Other Allegations

• Indirect Infringement: The complaint makes a conclusory allegation of indirect infringement but does not provide specific factual support, such as identifying specific instructions or actions by Apple that would induce its customers or developers to infringe Compl. ¶5
• Willful Infringement: The complaint does not contain allegations of willful infringement, such as asserting that Apple had pre-suit knowledge of the '339 Patent. The prayer for relief includes a request for a finding that the case is "exceptional" under 35 U.S.C. § 285, which is the standard for awarding attorney's fees Compl., Prayer for Relief ¶E

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the term "interface block," which the patent illustrates with specific hardware like level shifters and synchronizers, be construed to encompass the accused combination of a hardware Unified Memory Architecture and a system-level software scheduler like Grand Central Dispatch?
• A second key issue will be evidentiary: can the plaintiff prove, through discovery, its "information and belief" allegations that Apple's functionally distinct performance and efficiency core clusters are in fact powered by independent supply voltages and clocked by separate PLLs, as strictly required by the language of the asserted claim? The outcome of this factual inquiry may be decisive for the infringement analysis.