Redstone Logics LLC v. Apple Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Redstone Logics LLC (Texas)
  • Defendant: Apple Inc. (California)
  • Plaintiff's Counsel: Russ August & Kabat
• Case Identification: 7:25-cv-00183, W.D. Tex., 07/14/2025
• Venue Allegations: Plaintiff alleges venue is proper because Defendant has transacted business in the district and maintains regular and established places of business at two specified addresses in Austin, Texas.
• Core Dispute: Plaintiff alleges that Defendant's M-series and A-series multi-core processors infringe a patent related to methods for managing communication between processor core groups that operate with independent power and clock signals.
• Technical Context: The patent addresses technologies for power management in multi-core processors, a critical design consideration for mobile and battery-powered devices where balancing high performance with energy efficiency is essential.
• Key Procedural History: The complaint does not specify any prior litigation, licensing history, or other procedural events relevant to the patent-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,549,339 - "Processor core communication in multi-core processor,"

• Issued: October 1, 2013 (the "'339 Patent")

The Invention Explained

• Problem Addressed: The patent's background describes a challenge in conventional multi-core processors where all processor cores generally share the same supply voltage and clock signal '339 Patent, col. 1:7-10 This architecture limits the effectiveness of dynamic power management, where different parts of a processor should be able to operate at lower power and clock speeds when computing requirements are reduced '339 Patent, col. 1:10-14
• The Patented Solution: The invention proposes a multi-core processor architecture divided into distinct "regions" or "stripes" of processor cores '339 Patent, col. 2:21-26 Each region can be powered by an independent supply voltage and driven by an independent clock signal, allowing for more granular power and performance control '339 Patent, col. 2:26-31 To manage the complexities of communication between these independently operating regions, the patent describes an "interface block" situated between them, which can include components like level shifters to translate different voltage levels and synchronizers to handle different clock frequencies '339 Patent, abstract '339 Patent, col. 3:26-32 '339 Patent, col. 4:1-6
• Technical Importance: This approach facilitates more advanced power-saving techniques in complex processors by allowing high-demand tasks to run on high-power core groups while low-demand tasks run on energy-efficient core groups, without disrupting communication between them.

Key Claims at a Glance

• The complaint asserts independent claim 1 Compl. ¶10
• The essential elements of independent claim 1 are:
  • A first set of processor cores configured to dynamically receive a first supply voltage and a first output clock signal from a first Phase Lock Loop (PLL).
  • A second set of processor cores configured to dynamically receive a second supply voltage and a second output clock signal from a second PLL.
  • The first supply voltage is "independent from" the second supply voltage.
  • The first clock signal (input to the first PLL) is "independent from" the second clock signal (input to the second PLL).
  • An "interface block" coupled between the first and second sets of processor cores, configured to "facilitate communication" between them. '339 Patent, col. 7:51-col. 8:5

III. The Accused Instrumentality

Product Identification

The complaint identifies the "Accused Instrumentalities" as products comprising Apple's M-series and A-series System on Chip (SoC) processors Compl. ¶8

Functionality and Market Context

The complaint alleges that these SoCs contain "two or more sets of processors implementing the Firestorm and Icestorm architecture (or similar architecture)" Compl. ¶8 This architecture is publicly understood to be a heterogeneous computing design, where "Firestorm" cores are high-performance and "Icestorm" cores are high-efficiency. The complaint alleges these SoCs directly infringe the '339 Patent Compl. ¶8 These processors are central to Apple's product lines, including iPhones, iPads, and Mac computers, and are a key element of its market position.

IV. Analysis of Infringement Allegations

The complaint states that a claim chart comparing independent claim 1 to the accused products is attached as Exhibit 2, but this exhibit was not provided Compl. ¶10 The narrative infringement theory suggests that Apple's SoCs map to the claims of the '339 Patent as follows: the high-performance "Firestorm" cores constitute the "first set of processor cores," while the high-efficiency "Icestorm" cores constitute the "second set of processor cores." Plaintiff alleges these distinct core sets operate with the independent, dynamically managed supply voltages and clock signals recited in the claims. The on-chip fabric or interconnect that enables communication between these performance and efficiency core clusters is presumably the alleged "interface block."

No probative visual evidence provided in complaint.

Identified Points of Contention

• Scope Questions: A potential dispute may arise over whether Apple's on-chip interconnect fabric, which facilitates communication between its heterogeneous core clusters, meets the definition of the claimed "interface block." The construction of this term will be a central issue.
• Technical Questions: Claim 1 requires that the input clock signal for the first set of cores be "independent from" the input clock signal for the second set '339 Patent, col. 7:62-col. 8:1 A key technical question will be whether the clock signals for Apple's different core clusters are derived from truly independent sources, or if they originate from a common master clock and are subsequently divided or multiplied. The latter scenario could support a non-infringement argument.

V. Key Claim Terms for Construction

Term: "interface block"

• Context and Importance: This term is the structural and functional link between the two sets of processor cores. Its scope is critical, as it must read on the componentry within the accused Apple SoCs that manages communication between the high-performance and high-efficiency cores for infringement to be found.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim itself defines the term functionally as being "configured to facilitate communication between the first set of processor cores and the second set of processor cores" '339 Patent, col. 8:2-5 This broad, functional language may support an interpretation that covers any hardware structure performing that role.
  • Evidence for a Narrower Interpretation: The specification discloses specific embodiments of the "interface block" that contain "level shifters" '339 Patent, col. 3:29-32 or "synchronizers" '339 Patent, col. 4:1-6 '339 Patent, Fig. 3 A defendant may argue that the term should be construed to require these specific components or their equivalents, potentially narrowing its scope.

Term: "independent" (as applied to the first and second clock signals)

• Context and Importance: This term is a key technical limitation that distinguishes the patented invention from prior art that might use a common clock source. Whether the clocking architecture in the accused SoCs meets this "independent" requirement will be a primary focus of the technical infringement analysis.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: Plaintiff may argue that "independent" simply means the resulting clock domains for the two sets of cores can operate at different, non-related frequencies and can be changed without reference to one another, regardless of their ultimate hardware source.
  • Evidence for a Narrower Interpretation: The claim recites "a first clock signal" and "a second clock signal" that are "independent" from each other, which are then fed into separate PLLs '339 Patent, col. 7:56-57 '339 Patent, col. 7:62-col. 8:1 This language may support a narrower interpretation requiring physically separate clock generators or sources, rather than two signals derived from a single common source.

VI. Other Allegations

• Indirect Infringement: The complaint does not plead specific facts to support a claim for either induced or contributory infringement.
• Willful Infringement: The complaint does not allege that Defendant had pre-suit knowledge of the '339 Patent or otherwise plead facts that would typically support a claim for willful infringement. The prayer for relief includes a request for a finding that the case is "exceptional" under 35 U.S.C. § 285, but the factual basis for this request is not detailed in the complaint body Compl. p. 4

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the term "interface block," as described in the patent, be construed broadly enough to read on the complex, integrated interconnect fabric used in Apple's modern heterogeneous SoCs to manage communication between performance and efficiency cores?
• A key evidentiary question will be one of technical specificity: does the complaint's theory of infringement withstand scrutiny on the claim limitation requiring that the input clock signals for the different core clusters be "independent"? The case may turn on whether Apple's architecture relies on a common clock source, which could create a significant hurdle for proving literal infringement of claim 1.