3D Surfaces LLC v. Dell Tech Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: 3D Surfaces, LLC (California)
  • Defendant: Dell Technologies Inc. and Dell Inc. (Delaware)
  • Plaintiff's Counsel: FEINBERG DAY KRAMER ALBERTI LIM TONKOVICH & BELLOLI LLP
• Case Identification: 6:21-cv-01107, W.D. Tex., 10/25/2021
• Venue Allegations: Venue is alleged to be proper in the Western District of Texas because Defendant Dell has a principal place of business and maintains a regular and established place of business in the district.
• Core Dispute: Plaintiff alleges that Defendant's computers, laptops, and tablets that support DirectX 11 and higher graphics technology infringe two patents related to real-time 3D graphics tessellation.
• Technical Context: The technology concerns specialized hardware units within Graphics Processing Units (GPUs) that can efficiently render complex, curved 3D surfaces in real-time, a foundational process for modern video games and professional graphics applications.
• Key Procedural History: The complaint alleges that Plaintiff provided Defendant with pre-suit notice of infringement of the '299 Patent as early as December 23, 2009, and of the '534 Patent as early as September 7, 2011, which may be relevant to claims of willful infringement.

Case Timeline

Date	Event
2000-07-28	Earliest Priority Date ('299 and '534 Patents)
2007-07-17	U.S. Patent No. 7,245,299 Issued
2009-12-23	Alleged pre-suit notice to Dell regarding '299 Patent
2011-07-12	U.S. Patent No. RE42,534 Issued
2011-09-07	Alleged pre-suit notice to Dell regarding '534 Patent
2021-10-25	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,245,299 ("Bicubic Surface Real-Time Tesselation Unit"), issued July 17, 2007

The Invention Explained

• Problem Addressed: The patent describes the inefficiency of prior art graphics systems that tessellated (subdivided) complex curved surfaces into triangles "off-line" on the main processor (CPU) '299 Patent, col. 2:50-54 This created a fixed number of triangles, which was inefficient for objects at varying distances, and the process of sending this large volume of triangle data from the CPU to the GPU created a significant data bus bottleneck '299 Patent, col. 3:5-9
• The Patented Solution: The invention proposes a new GPU architecture that includes a dedicated hardware "tessellate unit" positioned between the "transform unit" and "lighting unit" '299 Patent, Fig. 3 Instead of receiving pre-tessellated triangles, this GPU receives high-level descriptions of surfaces (e.g., as bicubic control points) and performs the tessellation into triangles in real-time '299 Patent, abstract This process can be adaptive, generating more or fewer triangles based on the object's appearance on screen, which provides an "automatic level of detail" '299 Patent, col. 5:15-19
• Technical Importance: Moving tessellation from an off-line, CPU-bound task to a real-time, GPU-bound one enabled the rendering of far more complex and dynamic 3D scenes by dramatically reducing bus traffic and allowing for adaptive levels of detail.

Key Claims at a Glance

• The complaint asserts independent claim 11.
• Claim 11 is a system claim with the following key structural and functional elements:
  • A "processor" and a "graphics processing unit (GPU)" coupled to it.
  • The GPU comprises a "transform unit", a "lighting unit", a "renderer unit", and a "tessellate unit" that is "coupled between the transform unit and the lighting unit".
  • The processor "transmits objects to be rendered to the GPU as control points".
  • The "transform unit" transforms the control points.
  • The "tessellate unit" executes instructions for "tessellating both rational and non-rational object surfaces in real-time".
  • The "lighting unit" lights the vertices of the resulting triangles.
  • The "renderer unit" renders the triangles by executing a second set of instructions.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Reissue Patent No. RE42,534 ("Bicubic Surface Real-Time Tesselation Unit"), issued July 12, 2011

The Invention Explained

• Problem Addressed: As a member of the same patent family, the '534 Patent addresses the same problems as the '299 Patent: the performance and bandwidth limitations of off-line, CPU-based tessellation for 3D graphics '534 Patent, col. 2:60-65
• The Patented Solution: The patented solution is a method for real-time graphics processing that utilizes a GPU architecture with an integrated "tessellate unit" '534 Patent, abstract The method involves receiving high-level graphic objects (e.g., control points), transforming them, tessellating them into triangles in real-time, and then lighting the resulting vertices for rendering '534 Patent, cl. 15
• Technical Importance: The method provides a more efficient pipeline for rendering complex surfaces by moving the computationally intensive tessellation task onto the specialized hardware of the GPU.

Key Claims at a Glance

• The complaint asserts independent claim 15.
• Claim 15 is a method claim with the following key steps:
  • "providing a tessellation unit coupled between a transform unit and a lighting unit".
  • "receiving graphic objects to be rendered by a graphics processing unit".
  • "transforming the graphic objects into transformed objects using said transform unit".
  • "tessellating the transformed objects using said tessellation unit".
  • "lighting vertices of triangles resultant from said tessellat[ion] using said lighting unit".
• The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are a broad range of Dell computers, including laptops, tablets, and desktops from lines such as Alienware, XPS, Latitude, and Inspiron, that "support DirectX 11 and higher 3D graphics technology" Compl. ¶14

Functionality and Market Context

The complaint alleges that the accused functionality resides in the graphics processing pipelines of the accused products, specifically within integrated or discrete GPUs that are compliant with the DirectX 11 (or higher) API Compl. ¶17 Compl. ¶41 These GPUs, such as Intel Core processors from the 4th generation onward, allegedly contain the hardware architecture and perform the steps required to carry out real-time tessellation Compl. ¶18 The complaint uses a diagram of an Intel Gen9 integrated graphics processor to illustrate the on-die coupling of the CPU and GPU Compl. ¶18 Compl. p. 5 The products are marketed for, among other things, high-performance gaming, which relies heavily on advanced 3D graphics capabilities like tessellation Compl. ¶17

IV. Analysis of Infringement Allegations

'299 Patent Infringement Allegations

Claim Element (from Independent Claim 11)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a processor; and a graphics processing unit (GPU) coupled to the processor...	The accused products are computers with a microprocessor (CPU) that includes an integrated GPU on the same die, connected by an on-die bus.	¶18	col. 7:1-3
...the GPU comprising a transform unit, a lighting unit, a renderer unit, and a tessellate unit coupled between the transform unit and the lighting unit...	The GPU's DirectX 11 pipeline allegedly comprises a Vertex Shader (transform unit), Hull/Tessellator/Domain Shaders (tessellate unit), Rasterizer/Pixel Shader (lighting unit), and Output Merger (renderer unit), which are functionally coupled in sequence.	¶¶19-25	col. 7:4-8
...the processor transmits objects to be rendered to the GPU as control points...	The CPU runs an application (e.g., a game) and transmits objects to be rendered (primitives) to the GPU as control points.	¶¶26-27	col. 7:10-12
...the transform unit transforms the control points...	The Vertex Shader stage of the pipeline transforms the incoming control points of a patch into transformed control objects.	¶22; ¶28	col. 7:12-13
...the tessellate unit executes a first set of instructions for tessellating both rational and non-rational object surfaces in real-time...	The pipeline's tessellation stages (Hull, Tessellator, and Domain Shaders) perform real-time tessellation of surfaces like Bezier patches.	¶29	col. 7:14-16
...the lighting unit lights vertices of the triangles...	The Rasterizer and Pixel Shader stages light the vertices of the triangles generated by the tessellation stages.	¶31	col. 7:16-17
...the renderer unit renders the triangles by executing a second set of instructions.	The Output Merger stage generates the final rendered pixel color, thereby rendering the triangles.	¶32	col. 7:17-19

'534 Patent Infringement Allegations

Claim Element (from Independent Claim 15)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
providing a tessellation unit coupled between a transform unit and a lighting unit;	The accused products provide a GPU with a DirectX 11 pipeline where the tessellation stages are functionally coupled between the Vertex Shader (transform unit) and Rasterizer/Pixel Shader (lighting unit).	¶42; ¶44	col. 7:5-8
receiving graphic objects to be rendered by a graphics processing unit;	The GPU receives graphic objects (primitives) transmitted from the CPU over an interconnect bus.	¶45	col. 15:13-15
transforming the graphic objects into transformed objects using said transform unit;	The Vertex Shader stage takes control points as input and transforms them into transformed control objects. A diagram illustrates this transformation of control points.	¶43; ¶46; Compl. p. 22	col. 15:16-18
tessellating the transformed objects using said tessellation unit;	The tessellation stages of the pipeline (Hull, Tessellator, Domain Shader) perform real-time tessellation of surfaces. A diagram shows how the tessellator divides a patch into triangles.	¶47; Compl. p. 24	col. 15:19-20
lighting vertices of triangles resultant from said tessellating using said lighting unit.	The Rasterizer and Pixel Shader stages light the triangles based on data from the preceding tessellation stages. A diagram illustrates the position of the lighting unit in the pipeline.	¶48; Compl. p. 30	col. 16:1-3

• Identified Points of Contention:
  • Scope Questions: The case may turn on whether the standardized functional blocks of the DirectX 11 pipeline (e.g., "Vertex Shader," "Hull Shader," "Tessellator") meet the definitions of the patent's more generically named "units" (e.g., "transform unit", "tessellate unit"). A potential issue is whether the combination of the Hull, Tessellator, and Domain shaders, as alleged, constitutes a single "tessellate unit" as claimed.
  • Technical Questions: A key question is whether the tessellation performed by the accused products is technically equivalent to that disclosed in the patents. The patents describe a specific approach to subdivision based on screen-space curvature criteria '299 Patent, col. 5:8-19 The complaint alleges infringement by citing to DirectX 11 functionality Compl. ¶23 Compl. ¶29, raising the question of whether the methods are operationally identical or if there is a material technical distinction.

V. Key Claim Terms for Construction

• The Term: "tessellate unit"

• Context and Importance: This term is the central component of the invention. Its construction will determine whether the accused DirectX 11-compliant hardware falls within the scope of the claims. The dispute will likely center on whether the term should be given a broad, functional meaning or a narrower meaning tied to the specific algorithms and embodiments described in the specification.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The abstract broadly defines the term as "a tessellate unit for tessellating both rational and non-rational object surfaces in real-time" '299 Patent, abstract Claim 1 of the '299 patent uses similar functional language.
  • Evidence for a Narrower Interpretation: The detailed description repeatedly references a specific method of subdivision from a parent patent, stating the method works by subdividing "only two orthogonal curves of the surface" '299 Patent, col. 5:4-9 A defendant may argue this language limits the scope of the "tessellate unit" to one that employs this particular algorithm.

• The Term: "coupled between the transform unit and the lighting unit"

• Context and Importance: This limitation defines the architectural placement of the "tessellate unit". The infringement analysis depends on whether the alleged sequence of shader stages in the accused DirectX 11 pipeline satisfies this "coupled between" requirement.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: Figure 3 of the patents depicts a simple block diagram showing the Tesselate unit positioned sequentially between the Transform and Light units, suggesting a functional data flow relationship '299 Patent, Fig. 3 The complaint presents several pipeline diagrams from third-party sources showing a similar sequential flow Compl. p. 9 Compl. p. 15
  • Evidence for a Narrower Interpretation: A defendant might argue that the term implies a more specific hardware-level coupling than the logical pipeline flow of a programmable shader architecture. The patent contrasts its solution with prior art GPUs, which could be used to argue the claim requires a fixed-function hardware unit arrangement distinct from the programmable stages in modern GPUs.

VI. Other Allegations

• Indirect Infringement: The complaint alleges Dell induced infringement by advertising the accused products and providing instruction materials, training, and support services that encourage and instruct customers to use the products in an infringing manner Compl. ¶33 Compl. ¶49
• Willful Infringement: Willfulness is alleged based on pre-suit knowledge of the patents. The complaint claims Dell was notified of the '299 Patent in 2009 and the '534 Patent in 2011 and, with this awareness, made a business decision to "efficiently infringe" rather than take a license Compl. ¶35 Compl. ¶51

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the term "tessellate unit", which is described in the patent specification with reference to specific subdivision algorithms, be construed broadly enough to read on the standardized, programmable tessellation stages (Hull, Tessellator, and Domain Shaders) of the DirectX 11 graphics API as implemented in the accused products?
• A second central question will be one of technical mapping: assuming a favorable claim construction for the plaintiff, does the operation of the accused DirectX 11-compliant GPUs align with the functional requirements of the claims? The case may require a detailed technical comparison between the patented method of adaptive tessellation and the actual methods for determining tessellation factors and generating vertices within the accused hardware.