VLSI Technology LLC v. Intel Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: VLSI Technology LLC (Delaware)
  • Defendant: Intel Corporation (Delaware)
  • Plaintiff's Counsel: Mann | Tindel | Thompson
• Case Identification: 6:19-cv-00254, W.D. Tex., 04/11/2019
• Venue Allegations: Venue is asserted based on Defendant Intel Corporation maintaining a regular and established place of business within the Western District of Texas and having committed alleged acts of infringement in the district.
• Core Dispute: Plaintiff alleges that certain Intel processors, including the Ivy Bridge and Skylake families, infringe three U.S. patents related to dynamic power and performance management techniques in microprocessors.
• Technical Context: The technologies at issue concern methods for optimizing processor power consumption by dynamically adjusting memory size, voltage levels, and clock speeds, which are foundational techniques for balancing performance and energy efficiency in modern computing devices.
• Key Procedural History: The complaint alleges that Intel had pre-suit knowledge of U.S. Patent No. 7,725,759 due to its assertion in a prior lawsuit, VLSI Technology LLC v. Intel Corp, filed in the District of Delaware on March 1, 2019. The complaint also references Intel's alleged corporate policy of forbidding employees from reading non-Intel patents as a basis for willful blindness.

Case Timeline

Date	Event
2005-06-29	U.S. Patent No. 7,725,759 Priority Date
2006-08-30	U.S. Patent No. 7,523,373 Priority Date
2009-01-27	U.S. Patent No. 8,156,357 Priority Date
2009-04-21	U.S. Patent No. 7,523,373 Issue Date
2010-05-25	U.S. Patent No. 7,725,759 Issue Date
2012-04-10	U.S. Patent No. 8,156,357 Issue Date
2019-03-01	Delaware Complaint asserting U.S. Patent No. 7,725,759 filed
2019-04-11	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,156,357 - "Voltage-based memory size scaling in a data processing system"

• Patent Identification: U.S. Patent No. 8,156,357, "Voltage-based memory size scaling in a data processing system," issued April 10, 2012 (the '357 Patent). Compl. ¶8

The Invention Explained

• Problem Addressed: The patent's background describes an inefficiency in data processing systems where the minimum operating voltage (Vmin) is fixed at a level required by the most voltage-sensitive components, typically memory. This prevents the system from operating at lower, more power-efficient voltages that other components could tolerate, leading to a "loss of functionality and/or efficiency." '357 Patent, col. 1:40-53 Compl. ¶12
• The Patented Solution: The invention proposes a method for dynamically scaling the size of a memory, such as a processor cache, in response to changes in supply voltage. As the voltage is lowered, sections of the memory (e.g., specific "ways" in a set-associative cache) that become unreliable or non-functional are identified and deactivated. The system continues to operate with a smaller but still functional memory. When the voltage is increased, these deactivated sections can be identified as functional again and brought back into use, restoring the memory to its full size. '357 Patent, col. 1:53-66 Compl. ¶13
• Technical Importance: This technique enables more aggressive power management by allowing a processor to operate at lower voltages than would otherwise be possible, thereby saving power while retaining partial memory functionality. '357 Patent, col. 2:7-14

Key Claims at a Glance

• The complaint asserts at least independent claim 1. Compl. ¶15
• The essential elements of Claim 1 include:
  • A method of using a cache with multiple ways, starting with accessing it at a first power supply voltage.
  • Reducing the power supply voltage to a second, lower value.
  • Identifying a set of ways as non-functional, where this non-functionality is caused by the reduced voltage, by "retrieving information that correlates non-functional ways... with values of the power supply voltage."
  • Accessing the cache exclusive of the non-functional ways while at the second voltage.
  • Increasing the power supply voltage to a third value.
  • Identifying a set of ways that is now functional at the third voltage.
  • Accessing the cache including this newly functional set of ways.
• The complaint does not explicitly reserve the right to assert dependent claims, though this is standard practice.

U.S. Patent No. 7,523,373 - "Minimum memory operating voltage technique"

• Patent Identification: U.S. Patent No. 7,523,373, "Minimum memory operating voltage technique," issued April 21, 2009 (the '373 Patent). Compl. ¶37

The Invention Explained

• Problem Addressed: The patent explains that due to manufacturing variations, the minimum operating voltage for a memory can differ from one integrated circuit (IC) to another. Using a single, worst-case Vmin for all parts is inefficient because it prevents chips capable of operating at lower voltages from realizing potential power savings. '373 Patent, col. 2:17-27 Compl. ¶41
• The Patented Solution: The invention describes a method where each IC is individually tested to determine its unique minimum memory operating voltage. This specific value is then stored permanently on the IC itself in a "non-volatile memory location," such as fuses or a register. This stored information can then be used by the chip's internal controller to make more precise power management decisions, ensuring the chip operates at its true optimal voltage. '373 Patent, abstract '373 Patent, col. 2:27-36 Compl. ¶42
• Technical Importance: This on-chip storage of per-unit characterization data allows for part-specific voltage optimization (a practice known as "binning"), enabling each individual processor to achieve maximum power efficiency beyond what a one-size-fits-all approach would allow. '373 Patent, col. 9:16-30

Key Claims at a Glance

• The complaint asserts at least independent claim 16. Compl. ¶44
• The essential elements of Claim 16 include:
  • A method involving an integrated circuit with a memory and a separate "functional circuit."
  • Testing the memory to determine its minimum operating voltage and storing this value in a non-volatile manner.
  • Providing a first regulated voltage to the functional circuit and a second, greater regulated voltage.
  • When the first regulated voltage is at or above the stored minimum, providing the first regulated voltage as the memory's operating voltage.
  • When the first regulated voltage is below the stored minimum, providing the second regulated voltage as the memory's operating voltage, while the first regulated voltage is provided to the functional circuit.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,725,759 (Multi-Patent Capsule) - "System and method of managing clock speed in an electronic device"

• Patent Identification: U.S. Patent No. 7,725,759, "System and method of managing clock speed in an electronic device," issued May 25, 2010 (the '759 Patent). Compl. ¶69
• Technology Synopsis: The patent addresses the need for an improved method of controlling clock frequency to selectively deliver faster clock speeds for better performance while managing power consumption. Compl. ¶73 The disclosed method involves monitoring multiple "master devices" (e.g., processor cores) on a bus and allowing a device to request a change in clock frequency based on a predefined change in its performance (e.g., increased workload). A controller then provides the new clock frequency to other master devices and the bus itself. '759 Patent, abstract Compl. ¶¶74, 81, 85-87
• Asserted Claims: The complaint asserts at least independent claim 1. Compl. ¶76
• Accused Features: The complaint alleges that Intel's "Hardware-Controlled Performance States ('HWP' or 'Speed Shift') technology," as found in its Skylake processors, infringes the '759 Patent. Compl. ¶75 Compl. ¶77

III. The Accused Instrumentality

Product Identification

The complaint accuses specific families of Intel processors. The '357 and '373 Patents are asserted against "Intel Ivy Bridge processors" that allegedly use "dynamic cache shrink technology" and store minimum voltage information. Compl. ¶¶16, 45 The '759 Patent is asserted against "Intel Skylake processors" that allegedly use "Hardware-Controlled Performance States (HWP or 'Speed Shift') technology." Compl. ¶75 Compl. ¶77

Functionality and Market Context

• The complaint alleges that the "Dynamic Cache Shrink Feature" in Ivy Bridge processors operates by flushing and deactivating a subset of the processor's cache ways (e.g., shrinking from 16 active ways to 2) when the system detects a low activity workload, which improves the minimum operating voltage. Compl. ¶17 An Intel presentation slide illustrates this feature, showing the cache ways being reduced during a "Sleep" state. Compl. ¶17, Figure
• The "Speed Shift" technology in Skylake processors is described as a feature that "delivers dramatically quicker responsiveness... by allowing the processor to more quickly select its best operating frequency and voltage for optimal performance and power efficiency." Compl. ¶77 An Intel product brief table highlights this as a key feature of its 6th Generation Core processors. Compl. ¶77, Figure

IV. Analysis of Infringement Allegations

'357 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A method of using a cache having a plurality of ways, comprising:	Intel Ivy Bridge processors operate using a cache organized in 16 ways.	¶17	col. 2:1-2
accessing the cache with a power supply voltage applied to the cache at a first value;	Ivy Bridge processors operate with the cache having a power supply voltage at a nominal, first value.	¶18	col. 1:48-53
reducing the power supply voltage to a second value;	The Dynamic Cache Shrink Feature reduces the power supply to the cache by 30 mV to a second, reduced voltage.	¶19	col. 1:53-56
identifying a first set of ways...as being non-functional... wherein the step of identifying... comprises: retrieving information that correlates non-functional ways of the cache with values of the power supply voltage;	Processors identify ways with "defects" as non-functional at the reduced voltage, with the relationship between cache size (ways) and minimum voltage shown in a graph.	¶¶20-21	col. 4:20-24
accessing the cache exclusive of the first set of ways, wherein the step of accessing the cache exclusive of the first set of ways is performed with the power supply voltage at the second value;	The processor's Power Control Unit (PCU) puts a subset of ways (e.g., ways 3-16) to sleep, and these ways are not accessed while the processor is in this low-power mode.	¶¶22-25	col. 5:10-14
increasing the power supply voltage to a third value;	When the PCU detects high activity, it returns to normal operation, which involves increasing the voltage from the reduced second value.	¶27	col. 6:2-5
identifying a second set of ways...that is functional with the power supply being applied at the third value; and	When returning to normal operation, the processor expands back to the full set of 16 ways, all of which are functional at the nominal (third) voltage.	¶26	col. 8:1-5
accessing the cache including the second set of ways.	In normal operation, the processor accesses the full cache, including the ways that were previously non-functional at the lower voltage.	¶27	col. 8:15-19

• Identified Points of Contention:
  • Scope Question: A primary issue may be the interpretation of "retrieving information that correlates non-functional ways... with values of the power supply voltage." The complaint points to a graph showing a relationship between cache size and Vmin benefit (Compl. ¶19, Figure), while the patent's embodiment describes storing this data in "mapping registers 45" ('357 Patent, col. 4:1-5). The court may need to decide if an algorithmic determination of this relationship meets the "retrieving information" limitation, or if a pre-characterized, stored lookup table is required.
  • Technical Question: A key factual question will be one of causation. Claim 1 requires that the ways become "non-functional" because the voltage is reduced. The complaint alleges Intel's feature is triggered by "low activity workload" Compl. ¶17 The analysis will likely focus on whether the ways are turned off simply to save power due to low activity, or if they are turned off because the lower voltage actually renders them functionally unreliable, as the claim requires.

'373 Patent Infringement Allegations

Claim Element (from Independent Claim 16)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
providing an integrated circuit...; testing the memory to determine...a minimum operating voltage; storing, in a non-volatile manner, the value...;	Intel Ivy Bridge processors test and store the minimum operating voltage for different cache configurations in a non-volatile manner, accessible after reboots.	¶¶46-47	col. 2:27-33
providing a functional circuit on the integrated circuit exclusive of the memory;	The Ivy Bridge processor includes cores (the functional circuit) which are separate from the last level cache (the memory).	¶¶49-50	col. 5:19-21
providing a first regulated voltage to the functional circuit;	The processor cores are powered by a regulated voltage (the "first voltage") via a power gate.	¶¶51-52	col. 3:5-9
providing a second regulated voltage, wherein the second regulated voltage is greater than the first regulated voltage;	The processor is powered by a "core power rail," VCC (the "second voltage"), which is greater than the gated core voltage when the gate is partially closed.	¶¶53-54	col. 3:24-27
providing the first regulated voltage as the operating voltage of the memory when the first regulated voltage is at least the value of the minimum operating voltage;	When the core voltage (first voltage) is above the memory's minimum, the power gate is fully open, making the first and second voltages the same; this voltage is provided to the memory.	¶57	col. 3:30-36
providing the second regulated voltage as the operating voltage of the memory when the first regulated voltage is less than the value of the minimum operating voltage...	The LLC memory is "ungated" and always receives the second voltage (VCC). When the first voltage is below the minimum, this second voltage serves as the memory's operating voltage.	¶¶56, 58-59	col. 3:36-41

• Identified Points of Contention:
  • Technical Question: The complaint alleges the LLC memory is "ungated," meaning it is always supplied with the "second regulated voltage" (VCC) Compl. ¶56 This raises a significant question of technical and factual accuracy regarding the claim limitation that requires "providing the first regulated voltage as the operating voltage of the memory" under certain conditions. The infringement analysis will likely turn on whether the accused architecture ever actually supplies the first regulated voltage to the memory array, or if it is permanently wired to the second voltage rail. A diagram in the complaint shows the LLC as "Ungated - Purple," distinct from the "Gated - Green" Core. Compl. ¶50, Figure
  • Scope Question: The court may examine whether Intel's alleged architecture, with a gated core voltage and an ungated LLC voltage, is functionally equivalent to the patent's disclosed architecture, which features a "power supply selector" that actively chooses between two different voltage supplies for the memory array. '373 Patent, Fig. 1

V. Key Claim Terms for Construction

For the '357 Patent:

• The Term: "retrieving information that correlates non-functional ways of the cache with values of the power supply voltage"
• Context and Importance: This term is central to the "identifying" step of claim 1. The outcome of the case may depend on whether Intel's alleged use of an algorithm or a functional relationship (as depicted in a graph) to manage cache ways constitutes "retrieving information." Practitioners may focus on this term because it distinguishes between a dynamic, on-the-fly calculation and a system that relies on pre-characterized, stored data.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A plaintiff may argue that the term's plain meaning is broad and not limited to a specific implementation. The specification states that "mapping registers 45" "may provide" the correlating information, suggesting this is one possible but not exclusive embodiment. '357 Patent, col. 4:20-24
  • Evidence for a Narrower Interpretation: A defendant may argue that the only embodiment disclosed in the patent for performing this function is the use of "mapping registers 45", which implies a pre-stored lookup table. '357 Patent, Fig. 2 This could support a narrower construction limited to retrieving data from a stored table rather than deriving it algorithmically.

For the '373 Patent:

• The Term: "providing the first regulated voltage as the operating voltage of the memory"
• Context and Importance: This term is critical because the complaint itself suggests the accused memory (LLC) is "ungated" and always receives the "second regulated voltage" (VCC) Compl. ¶56 Infringement of this claim step appears to be a central point of dispute.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A plaintiff may argue that when the power gate for the core is fully open, the first and second voltages become the same Compl. ¶57, and thus the first voltage is functionally "provided" to the memory. The patent's focus is on the functional outcome of ensuring the memory receives a sufficient voltage.
  • Evidence for a Narrower Interpretation: A defendant may argue that "providing" implies an active selection and delivery, as embodied by the "power supply selector 21" in the patent's diagram, which explicitly switches the memory's input between "VDDlogic" (first voltage) and "VDDmem" (second voltage) '373 Patent, Fig. 1 If the accused memory is physically hardwired to the second voltage rail, it could be argued that the first voltage is never "provided" to it as its operating voltage.

VI. Other Allegations

• Indirect Infringement: For all three patents, the complaint alleges induced infringement, stating that Intel provides documentation, datasheets, and developer's manuals that instruct customers on how to use the accused products in an infringing manner Compl. ¶29 Compl. ¶61 Compl. ¶91 The complaint also pleads contributory infringement, alleging the accused processors are a material part of the invention and not staple articles of commerce suitable for substantial noninfringing use Compl. ¶30 Compl. ¶62 Compl. ¶92
• Willful Infringement: The complaint alleges that Intel had knowledge of the patents at least as of the filing of the complaint Compl. ¶28 Compl. ¶60 For the '759 Patent, knowledge is alleged from the filing of a prior lawsuit in Delaware on March 1, 2019 Compl. ¶90 The complaint further alleges willful blindness based on Intel's purported corporate policy of prohibiting engineers from reading third-party patents to avoid infringement liability Compl. ¶28

VII. Analyst's Conclusion: Key Questions for the Case

1. A core issue will be one of claim construction: Can the term "retrieving information", in the context of the '357 Patent, be construed to cover an algorithmic relationship between voltage and functionality, or is it limited to a pre-characterized, stored lookup table as described in the patent's embodiment? Similarly, for the '373 Patent, can an "ungated" memory always connected to one voltage rail satisfy claim limitations that require it to be provided with two different regulated voltages under different operating conditions?

2. A key evidentiary question will be one of causation and function: For the '357 Patent, does the evidence show that Intel's "Dynamic Cache Shrink" deactivates cache ways because lower voltage renders them non-functional, as the claim requires, or are they simply powered down based on low system activity to conserve energy? For the '373 Patent, the case may turn on evidence of the accused processor's actual circuit-level operation and whether the "first regulated voltage" is ever, in fact, supplied as the operating voltage to the LLC memory array.