VLSI Technology LLC v. Intel Corp

I. Executive Summary and Procedural Information

• Case Name: VLSI Technology LLC v. Intel Corporation
• Parties & Counsel:
  • Plaintiff: VLSI Technology LLC (Delaware)
  • Defendant: Intel Corporation (Delaware)
  • Plaintiff's Counsel: Mann | Tindel | Thompson
• Case Identification: 6:19-cv-00254, W.D. Tex., 04/11/2019
• Venue Allegations: Venue is based on Defendant Intel maintaining a regular and established place of business in the Western District of Texas and allegedly committing acts of infringement within the district.
• Core Dispute: Plaintiff alleges that certain Intel processors, including the "Ivy Bridge" and "Skylake" families, infringe three U.S. patents related to dynamic power and performance management techniques in microprocessors.
• Technical Context: The technologies at issue concern methods for optimizing power consumption in integrated circuits by dynamically scaling memory size, adjusting clock speeds, and managing operating voltages based on workload and device-specific characteristics.
• Key Procedural History: The complaint alleges that Intel was willfully blind to the asserted patents due to a corporate policy of forbidding employees from reading patents held by outside companies. For U.S. Patent No. 7,725,759, the complaint notes that it was previously asserted against Intel in a separate action filed in the District of Delaware on March 1, 2019.

Case Timeline

Date	Event
2005-06-29	U.S. Patent No. 7,725,759 Priority Date
2006-08-30	U.S. Patent No. 7,523,373 Priority Date
2009-01-27	U.S. Patent No. 8,156,357 Priority Date
2009-04-21	U.S. Patent No. 7,523,373 Issued
2010-05-25	U.S. Patent No. 7,725,759 Issued
2012-04-10	U.S. Patent No. 8,156,357 Issued
2019-03-01	Delaware complaint asserting U.S. Patent No. 7,725,759 filed
2019-04-11	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,156,357 - "Voltage-based memory size scaling in a data processing system"

• Patent Identification: U.S. Patent No. 8,156,357, "Voltage-based memory size scaling in a data processing system", issued April 10, 2012 Compl. ¶8

The Invention Explained

• Problem Addressed: The patent's background section describes that when a fixed minimum supply voltage (Vmin) is set for a data processing system, a loss of functionality or efficiency may occur when operating at voltages below that fixed value, even if some components could function at lower voltages Compl. ¶12 '357 Patent, col. 1:48-53
• The Patented Solution: The invention proposes a method to dynamically scale the size of a memory, such as a cache, based on its operating voltage. As the supply voltage is reduced, sections of the memory (e.g., cache "ways") that become non-functional are identified and disabled, allowing the rest of the memory to continue operating in a reduced-capacity state. When the voltage is increased, these sections can be re-enabled and brought back into use Compl. ¶13 '357 Patent, abstract '357 Patent, col. 1:53-66
• Technical Importance: This technique allows a system to achieve greater power savings by operating at lower voltages than would be possible if the entire memory array were required to remain functional at all times Compl. ¶13

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶15
• The essential elements of independent claim 1 include:
  • Accessing a cache with a plurality of ways at a first power supply voltage.
  • Reducing the power supply voltage to a second value.
  • Identifying a first set of ways as non-functional at the second voltage by retrieving information that correlates non-functional ways with power supply voltage values.
  • Accessing the cache exclusive of the identified non-functional ways while at the second voltage.
  • Increasing the power supply voltage to a third value.
  • Identifying a second set of ways from the first set that is now functional at the third value.
  • Accessing the cache including the re-identified functional ways.
• The complaint alleges infringement of "one or more claims" of the '357 Patent Compl. ¶14

U.S. Patent No. 7,523,373 - "Minimum memory operating voltage technique"

• Patent Identification: U.S. Patent No. 7,523,373, "Minimum memory operating voltage technique", issued April 21, 2009 Compl. ¶37

The Invention Explained

• Problem Addressed: The patent explains that the minimum operating voltage for a memory can vary between individual integrated circuits (ICs) due to manufacturing variations. Setting a universal minimum voltage based on a worst-case scenario prevents ICs with more robust characteristics from operating at lower, more power-efficient voltages Compl. ¶41 '373 Patent, col. 2:17-27
• The Patented Solution: The invention describes a method where each IC is tested to determine the specific minimum operating voltage for its memory. This unique value is then stored in a non-volatile location on the IC itself (e.g., a non-volatile register or fuses). This stored information is subsequently used by the IC to inform power management decisions, such as determining when to switch to an alternative power supply to ensure the memory's minimum voltage is met Compl. ¶42 '373 Patent, abstract '373 Patent, col. 2:27-37
• Technical Importance: This method enables per-chip power optimization, allowing each device to be "binned" and operated according to its actual capabilities rather than a generic worst-case specification, thereby improving power efficiency Compl. ¶42 '373 Patent, col. 2:35-37

Key Claims at a Glance

• The complaint asserts at least independent claim 16 Compl. ¶44
• The essential elements of independent claim 16 include:
  • Testing a memory on an integrated circuit (IC) to determine its minimum operating voltage and storing that value in a non-volatile manner.
  • Providing a functional circuit on the IC exclusive of the memory.
  • Providing a first regulated voltage to the functional circuit and a second, greater regulated voltage.
  • When the first regulated voltage is at least the value of the stored minimum operating voltage, providing that first regulated voltage as the operating voltage of the memory.
  • When the first regulated voltage is less than the stored minimum operating voltage, providing the second regulated voltage as the operating voltage of the memory, while the first regulated voltage continues to be provided to the functional circuit.
• The complaint alleges infringement of "one or more claims" of the '373 Patent Compl. ¶43

U.S. Patent No. 7,725,759 - "System and method of managing clock speed in an electronic device"

• Patent Identification: U.S. Patent No. 7,725,759, "System and method of managing clock speed in an electronic device", issued May 25, 2010 Compl. ¶69
• Technology Synopsis: The patent addresses the need for an improved system to control clock frequency in an electronic device Compl. ¶73 '759 Patent, col. 1:22-24 The invention discloses a method of managing clock speeds by monitoring multiple "master devices" (e.g., CPU cores) on a bus, and in response to a request from one device triggered by a change in its performance, selectively increasing the clock frequency of the bus and other devices to enhance system responsiveness '759 Patent, abstract Compl. ¶74
• Asserted Claims: The complaint asserts at least independent claim 1 Compl. ¶76
• Accused Features: The complaint accuses Intel's "Hardware-Controlled Performance States ('HWP' or 'Speed Shift')" technology, as found in Intel Skylake processors, of infringement Compl. ¶75 Compl. ¶77

III. The Accused Instrumentality

Product Identification

• The complaint identifies "Intel Ivy Bridge processors" as infringing the '357 and '373 Patents and "Intel Skylake processors" as infringing the '759 Patent Compl. ¶16 Compl. ¶45 Compl. ¶77

Functionality and Market Context

• The complaint alleges that Intel's Ivy Bridge processors incorporate a "Dynamic Cache Shrink Feature" Compl. ¶17 Compl. ¶19 This feature allegedly reduces the active last-level cache (LLC) size from 16 ways to 2 ways during periods of low activity to enable operation at a lower minimum voltage (VccMin). When high activity is detected, the cache is expanded back to the full 16 ways Compl. ¶17 A slide referenced in the complaint shows this feature reducing a 16-way cache to 2 ways to improve VccMin Compl. ¶17
• The complaint alleges that Intel's Skylake processors implement "Hardware-Controlled Performance States" (HWP), also known as "Speed Shift" technology Compl. ¶75 This feature is described as allowing the processor to autonomously and quickly select its optimal operating frequency and voltage for performance and power efficiency Compl. ¶77 The complaint alleges that individual processor cores monitor their own workload and request performance state (P-state) changes from a central "Package Control Unit" (PCU), which then controls the frequency for all cores on the device Compl. ¶82 A diagram from an Intel presentation depicts this PCU architecture monitoring multiple cores connected by a ring interconnect bus Compl. ¶79

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,156,357 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A method of using a cache having a plurality of ways...	Intel Ivy Bridge processors operate using a cache organized in 16 ways.	¶17	col. 2:6-7
accessing the cache with a power supply voltage applied to the cache at a first value;	The accused processors operate at a nominal voltage during high activity. A slide depicts this as an "Active" state with 16 ways.	¶18	col. 5:52-53
reducing the power supply voltage to a second value;	The Dynamic Cache Shrink feature is alleged to reduce the power supply voltage by 30 mV during low activity. A graph in the complaint shows Vmin benefit correlated with cache size reduction.	¶19	col. 6:2-3
identifying a first set of ways... as being non-functional... wherein the step of identifying... comprises: retrieving information that correlates non-functional ways of the cache with values of the power supply voltage;	The accused processors allegedly identify ways that include "defects" as non-functional at the reduced voltage, with the complaint citing a presentation that notes cache Vmin is limited by "bad cells" or defects.	¶¶20-21	col. 4:48-52
accessing the cache exclusive of the first set of ways, wherein the step of accessing... is performed with the power supply voltage at the second value;	The Power Control Unit (PCU) allegedly flushes and puts 14 of the 16 ways to "sleep," leaving only two ways active for access at the reduced voltage.	¶¶22-24	col. 6:59-62
increasing the power supply voltage to a third value;	When the PCU detects high activity, the processor returns to normal operation at the nominal (non-reduced) operating voltage.	¶26	col. 7:45-48
identifying a second set of ways... that is functional with the power supply being applied at the third value; and accessing the cache including the second set of ways.	The processor allegedly expands the cache back to the full set of 16 ways, all of which are functional and accessible at the nominal voltage.	¶¶26-27	col. 7:52-58

• Identified Points of Contention:
  • Scope Question: A central question may be whether the accused "Dynamic Cache Shrink" feature performs the claimed step of "retrieving information that correlates non-functional ways" with specific voltage values. The analysis may focus on whether disabling a fixed portion of the cache (e.g., 14 of 16 ways) in a generic low-power mode is equivalent to the patent's teaching of identifying and disabling specific ways based on stored data about their individual voltage failure points.
  • Technical Question: The infringement allegation hinges on the claim's requirement that ways are identified as "non-functional" because of the reduced voltage. A point of contention could be whether the accused feature disables cache ways to save power regardless of their functional status at that voltage, or whether it specifically disables them because they are known to be operationally unreliable at that voltage, as the claim requires.

U.S. Patent No. 7,523,373 Infringement Allegations

Claim Element (from Independent Claim 16)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
testing the memory to determine the operating voltage... that is a minimum operating voltage; storing, in a non-volatile manner, the value...	Intel Ivy Bridge processors allegedly store the minimum operating voltage for different last-level cache configurations in a non-volatile manner, accessible after reboot. A graph cited shows "Vmin Benefit with Cache Size."	¶¶46-47	col. 2:27-34
providing a functional circuit on the integrated circuit exclusive of the memory;	The processor cores are alleged to be the functional circuit, while the last-level cache (LLC) is the memory. A diagram shows these as distinct power planes ("Core (Gated - Green)" vs. "LLC (Ungated - Purple)").	¶¶49-50	col. 2:40-44
providing a first regulated voltage to the functional circuit;	The core is powered via a power gate, which regulates the voltage supplied to it.	¶¶51-52	col. 2:60-62
providing a second regulated voltage, wherein the second regulated voltage is greater than the first regulated voltage;	The processor is powered by a "core power rail," VCC, which is alleged to be the second, greater voltage.	¶¶53-54	col. 3:20-21
providing the first regulated voltage as the operating voltage of the memory when the first regulated voltage is at least the value of the minimum operating voltage;	When the core voltage (first voltage) is above the memory's minimum, the power gate is fully open, making the first and second voltages the same, and the first voltage is provided to the memory.	¶¶55, 57	col. 3:30-35
providing the second regulated voltage as the operating voltage of the memory when the first regulated voltage is less than the value of the minimum operating voltage...	The LLC memory is alleged to be "ungated," meaning it is always provided with VCC (the second voltage). When the core voltage (first voltage) is below the minimum, the LLC is still provided with the second voltage.	¶¶58-59	col. 3:35-40

• Identified Points of Contention:
  • Technical Question: The claim recites a conditional power delivery scheme: provide the first voltage when it is high enough, and provide the second voltage when the first is too low. The complaint alleges the accused LLC is "ungated" and "is always provided with VCC, the second voltage" Compl. ¶56 This raises the question of whether a memory that is always powered by the higher (second) voltage can be found to practice the claim's conditional logic of sometimes being powered by the first voltage.
  • Scope Question: The analysis will likely scrutinize what constitutes "storing... the value of the minimum operating voltage." The court may need to determine if the data presented in the complaint, which shows a general relationship between cache size and voltage benefit, is sufficient evidence of the accused products storing a specific, per-chip minimum voltage value as taught by the patent.

V. Key Claim Terms for Construction

'357 Patent, Claim 1

• The Term: "retrieving information that correlates non-functional ways of the cache with values of the power supply voltage"
• Context and Importance: This term defines the mechanism for identifying which cache ways to disable. The infringement case rests on whether the accused "Dynamic Cache Shrink" feature performs an equivalent act. Practitioners may focus on this term to dispute whether Intel's feature is merely a pre-set low-power mode versus a system that relies on stored, granular failure data.
• Intrinsic Evidence for a Broader Interpretation: The specification suggests the information can be "pre-programmed," which could support an argument that any pre-defined mapping between a voltage level and a set of active ways falls within the claim scope '357 Patent, col. 4:48-50
• Intrinsic Evidence for a Narrower Interpretation: The patent's abstract describes disabling "portions of the memory that include non-functional bits," and Figure 4 depicts per-line valid/lock bits that vary with voltage '357 Patent, abstract '357 Patent, Fig. 4 This could support a narrower construction requiring the "retrieved information" to be specific to known faulty bits or lines, not just a wholesale disabling of entire ways.

'373 Patent, Claim 16

• The Term: "providing the first regulated voltage as the operating voltage of the memory when..." and "providing the second regulated voltage as the operating voltage of the memory when..."
• Context and Importance: This pair of limitations is central to the claimed invention, defining a dynamic voltage selection for the memory based on a comparison. The infringement allegation appears to conflict with the complaint's own description of the accused product, making the construction of this conditional language critical.
• Intrinsic Evidence for a Broader Interpretation: A party could argue the language should be read functionally, covering any system architecture where the memory is effectively powered by one of two different voltage regimes depending on the system's operational state, without requiring a literal switching component.
• Intrinsic Evidence for a Narrower Interpretation: The patent's Figure 1 explicitly shows a "power supply selector 21" that chooses between VDDmem and VDDlogic to power the "memory array 22" '373 Patent, Fig. 1 This supports an interpretation requiring an active selection mechanism that provides one of two different voltages to the memory array, which may conflict with the allegation that the accused memory is always powered by a single, "ungated" voltage source Compl. ¶56

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement for all three patents. Inducement is based on Intel allegedly providing documentation, datasheets, and developer manuals that instruct customers on using the accused features Compl. ¶29 Compl. ¶61 Compl. ¶91 Contributory infringement is based on allegations that the accused processors are a material part of the inventions and are not staple articles of commerce suitable for substantial non-infringing use Compl. ¶30 Compl. ¶62 Compl. ¶92
• Willful Infringement: Willfulness is alleged for all three patents. The allegations are based on knowledge at least from the date of the complaint's filing, as well as willful blindness stemming from Intel's purported corporate policy of prohibiting employees from reading third-party patents Compl. ¶28 Compl. ¶60 Compl. ¶90 For the '759 Patent, the complaint alleges actual knowledge from a prior lawsuit filed in Delaware Compl. ¶90 For the '357 and '373 Patents, the complaint asserts that Intel knew or should have known of the patents due to prior litigation involving other patents from the same original assignee (NXP) and inventors Compl. ¶28 Compl. ¶60

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue for the '357 Patent will be one of functional equivalence: does Intel's "Dynamic Cache Shrink," which disables a fixed number of cache ways in a low-power mode, perform the same function as the claim's requirement to "retrieve information" that specifically "correlates non-functional ways" with particular voltage levels?
• A key question for the '373 Patent will be one of technical implementation: does the accused processor, which allegedly uses an "ungated" memory array consistently powered by a high voltage rail, practice the claim's explicit conditional logic of selecting between a "first" and "second" regulated voltage to power the memory based on a comparison to a stored minimum value?
• A central legal question for all asserted patents will be willful infringement: can the plaintiff establish egregious conduct by relying on a theory of willful blindness based on Intel's alleged internal policy against reading external patents, especially for patents where no direct pre-suit notice is alleged?