Mila US Inc v. Apple Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Mila US Inc, (Texas)
  • Defendant: Apple Inc., (California)
  • Plaintiff's Counsel: BC LAW GROUP, P.C.
• Case Identification: Mila US Inc v. Apple Inc., 1:26-cv-02107, W.D. Tex., 07/29/2026
• Venue Allegations: Plaintiff alleges venue is proper because Apple is registered to do business in Texas, has transacted business in the district, and maintains multiple "regular and established places of business" within the Western District of Texas.
• Core Dispute: Plaintiff alleges that Defendant's System-on-Chips (SoCs) and products containing them, including certain Mac and iPhone models, infringe four patents related to image processing, memory architecture, and data transmission.
• Technical Context: The technologies at issue concern methods for efficiently processing, storing, and transmitting image and system data, which are fundamental to the performance and power management of modern consumer electronics like smartphones and computers.
• Key Procedural History: The complaint states that Plaintiff sent a notice letter to Defendant on August 27, 2024, identifying the patents-in-suit and alleging infringement by Apple's A-series and M-series chips. Defendant is alleged to have responded on September 17, 2024, stating it would investigate the allegations.

Case Timeline

Date	Event
2005-03-17	'282 Patent Priority Date
2005-11-11	'499 Patent Priority Date
2007-02-20	'296 Patent Priority Date
2007-12-28	'436 Patent Priority Date
2010-10-12	'282 Patent Issue Date
2011-04-12	'296 Patent Issue Date
2011-06-21	'436 Patent Issue Date
2011-09-13	'499 Patent Issue Date
2024-08-27	Plaintiff sends notice letter to Defendant
2024-09-17	Defendant responds to notice letter
2026-07-29	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,924,296 - "System and method for DMA controlled image processing"

• Patent Identification: U.S. Patent No. 7,924,296, "System and method for DMA controlled image processing," issued on April 12, 2011 Compl. ¶8

The Invention Explained

• Problem Addressed: The patent's background describes that conventional image processing systems, particularly for tasks like alpha blending two images, require significant external memory buffers to store intermediate, scaled, or color-converted versions of the images, leading to increased power consumption and processing time '296 Patent, col. 2:39-51
• The Patented Solution: The invention proposes a system using a Direct Memory Access (DMA) fetching module that retrieves portions, or "tiles," of source images directly from memory '296 Patent, col. 6:18-19 This data is processed on-the-fly (e.g., scaled, color-converted, and blended) to generate a final combined image without requiring a separate, intermediate frame buffer to store the processed source images '296 Patent, abstract '296 Patent, col. 6:7-22
• Technical Importance: This on-the-fly architecture reduces memory bandwidth and storage requirements for complex image composition, a critical factor for improving performance and power efficiency in multimedia devices '296 Patent, col. 2:52-62

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶10
• The essential elements of independent claim 1 include:
  • A system for direct memory access (DMA) controlled image processing.
  • A DMA fetching module with a DMA master and multiple DMA channels configured to fetch "image tiles" of pixel data from multiple image sources.
  • At least one processor coupled to the DMA module to generate a combined image.
  • The image sources are of different resolution, orientation, and/or color space.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,966,436 - "Data transmitter having high and low speed transmission units"

• Patent Identification: U.S. Patent No. 7,966,436, "Data transmitter having high and low speed transmission units," issued on June 21, 2011 Compl. ¶19

The Invention Explained

• Problem Addressed: The patent identifies the inefficiency of using a single communication interface to transmit both large volumes of pixel data and small amounts of control data between a host processor and a display device, noting that a high-speed interface is wasteful for small data transfers ʼ436 Patent, col. 1:39-50
• The Patented Solution: The invention describes a data transmitter with two distinct operational modes: a "high-speed mode" for sending large "primary data" (such as image data) and a "low-speed mode" for smaller "secondary data" (such as control signals) ʼ436 Patent, abstract ʼ436 Patent, col. 2:1-7 This allows the system to select a power-appropriate mode based on the type of data being transmitted, as illustrated in the patent's Figure 2 ʼ436 Patent, Fig. 2
• Technical Importance: This dual-mode architecture optimizes power consumption for data communication in portable devices, which is a significant design constraint for battery-powered electronics ʼ436 Patent, col. 1:21-27

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶21
• The essential elements of independent claim 1 include:
  • A data transmitter disposed between a data processor and a display device.
  • A packetization unit to receive and packetize primary data.
  • A high-speed transmission unit to transmit the data packet in a high-speed mode.
  • A low-speed transmission unit to transmit secondary data and receive backward data in a low-speed mode.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,814,282 - "Memory share by a plurality of processors"

• Patent Identification: U.S. Patent No. 7,814,282, "Memory share by a plurality of processors," issued on October 12, 2010 Compl. ¶30
• Technology Synopsis: The patent addresses the "bottleneck problem" arising when multiple processors attempt to access a shared main memory simultaneously '282 Patent, col. 2:39-42 The proposed solution is a memory architecture where a main control unit and a sub-control unit are coupled to the main memory via independent buses, with a third bus for communication between the control units, thereby preventing processing slowdowns '282 Patent, abstract
• Asserted Claims: Independent claim 1 Compl. ¶32
• Accused Features: The complaint accuses iPhone products incorporating A-series SoCs that use a "unified memory architecture ('UMA')" Compl. ¶31

U.S. Patent No. 8,018,499 - "Image processing method and device using different clock rates for preview and capture modes"

• Patent Identification: U.S. Patent No. 8,018,499, "Image processing method and device using different clock rates for preview and capture modes," issued on September 13, 2011 Compl. ¶41
• Technology Synopsis: The patent addresses delays and conflicts in processing high-resolution images by proposing a system that uses different clock rates for different operational modes '499 Patent, col. 3:43-47 It uses a lower "first processing clock rate" for a device's "preview mode" and a higher "second processing clock rate" for its "capture mode," allowing for rapid encoding of a high-resolution image upon command without being disrupted by data from subsequent frames '499 Patent, abstract
• Asserted Claims: Independent claim 1 Compl. ¶43
• Accused Features: The complaint accuses iPhone products that incorporate an A-series SoC and a camera with "preview" functionality Compl. ¶¶42, 45

III. The Accused Instrumentality

Product Identification

• The complaint identifies two main categories of accused products:
  1. Mac products that incorporate Apple's M1 System-on-Chip (SoC) or later versions containing a "Display Coprocessor (DCP)" Compl. ¶9
  2. iPhone products that incorporate Apple's A14 SoC or later versions, which are alleged to implement MIPI DSI functionality and a unified memory architecture ("UMA") Compl. ¶¶20, 31, 42

Functionality and Market Context

• The complaint alleges that these SoCs contain specialized hardware and architectural features that perform the functions claimed by the asserted patents. The functionality includes DMA-based image processing via an IOMMU Compl. ¶12, dual-mode data transmission to the display Compl. ¶20, a unified memory architecture for shared access by multiple processors Compl. ¶31, and a camera system with distinct preview and capture modes Compl. ¶45
• The complaint references an Apple security guide page that states the accused products include an Input/Output Memory Management Unit (IOMMU) for each DMA agent in the system Compl. ¶12 As evidence for the infringement allegations concerning the '282 Patent, the complaint points to an Apple developer guide that describes a "unified memory model" Compl. ¶34 For the '436 Patent, the complaint cites an Apple support page describing the "Super Retina XDR display" functionality in accused iPhones Compl. ¶23
• The complaint does not provide specific allegations regarding the products' commercial importance, but identifies them as Apple's core Mac and iPhone product lines.

IV. Analysis of Infringement Allegations

The complaint references claim chart exhibits that were not provided with the filing. Therefore, the infringement allegations are summarized in prose based on the narrative of the complaint.

The complaint alleges that Apple's M-series and A-series SoCs directly infringe the asserted patents. For the '296 Patent, the infringement theory centers on the Display Coprocessor (DCP) and its associated Input/Output Memory Management Unit (IOMMU) found in M1 and later SoCs Compl. ¶¶9, 12 Plaintiff alleges this hardware performs DMA-controlled, on-the-fly image composition, such as for the "Picture in Picture" feature, which it argues maps to the elements of claim 1 of the '296 Patent Compl. ¶12

For the '436 Patent, the complaint alleges that iPhone products with A14 or later SoCs implement MIPI DSI functionality for communicating with the display Compl. ¶20 The theory is that this system uses separate high-speed and low-speed transmission protocols for different data types (e.g., image data vs. control data), allegedly corresponding to the "high-speed mode" and "low-speed mode" recited in claim 1 of the '436 Patent Compl. ¶¶23-24

V. Key Claim Terms for Construction

• Term ('296 Patent): "image tiles"
• Context and Importance: Claim 1 of the '296 Patent requires the DMA module to fetch "a plurality of image tiles of pixel data." The definition of this term is critical because the core of the invention is processing image portions to avoid full-frame buffering. The infringement analysis may depend on whether the data units processed by Apple's Display Coprocessor are considered "tiles" as contemplated by the patent.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the process as fetching a "portion of the source images (tiling)" '296 Patent, col. 6:18-19, language that may support a broader construction covering various methods of piecemeal data fetching.
  • Evidence for a Narrower Interpretation: The repeated use of the phrase "image tiles of pixel data" and the general context of DMA descriptors pointing to specific data locations could suggest that a "tile" is a discrete, formally structured block of data, not just any arbitrary portion of an image stream '296 Patent, col. 9:19-20
• Term ('436 Patent): "high-speed mode" and "low-speed mode"
• Context and Importance: Claim 1 of the '436 Patent requires distinct high-speed and low-speed transmission units and modes. The dispute may turn on whether the accused MIPI DSI interface, as used by Apple, operates with two separately defined "modes" or uses a single, variably-rated protocol that does not map onto the patent's specific dual-mode architecture.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent defines the modes in relation to the data they carry-"primary data" for high-speed and "secondary data" for low-speed-which could support an argument that any system differentiating transmission characteristics based on data type infringes ('436 Patent, col. 2:1-7).
  • Evidence for a Narrower Interpretation: The specification links the modes to distinct physical layer characteristics, including different clock signal frequencies and swing levels '436 Patent, col. 6:15-16 '436 Patent, col. 6:64-67 A defendant could argue that infringement requires proof of these specific, physically distinct operational states.

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement for all four asserted patents. The inducement claims are based on allegations that Apple provides instructions, developer documentation, and user guides that actively encourage and instruct end-users and developers to use the accused products in an infringing manner Compl. ¶12 Compl. ¶23 Compl. ¶34 Compl. ¶45 The contributory infringement claims allege that the accused SoCs and their specific internal components are a material part of the inventions, are especially made or adapted for infringement, and are not staple articles of commerce Compl. ¶¶13, 24, 35, 46
• Willful Infringement: The complaint alleges willful infringement for all asserted patents. The basis for this claim is alleged pre-suit knowledge stemming from a notice letter sent to Apple on August 27, 2024, as well as continued infringement after the filing of the complaint Compl. ¶¶16, 27, 38, 49

VII. Analyst's Conclusion: Key Questions for the Case

• A central technical question will be one of architectural mapping: does the functionality of Apple's highly integrated SoCs-specifically its Display Coprocessor, MIPI DSI interface, and Unified Memory Architecture-map directly onto the specific functional units and modes described in the asserted patents, or do Apple's modern implementations represent a technologically distinct, non-infringing alternative?
• A critical legal question will revolve around claim construction: how will the court define foundational terms like "image tiles" ('296 Patent) and the distinct "high-speed mode" versus "low-speed mode" ('436 Patent)? The scope given to these terms may determine whether Apple's current system architecture falls within the boundaries of patents from an earlier technological period.
• Given the plaintiff's documented pre-suit notice, an evidentiary issue will concern the adequacy and effect of knowledge: did the August 2024 letter provide Apple with knowledge of infringement sufficient to support a finding of willfulness, and how will the court view Apple's alleged continued infringement after receiving notice?