WeCrevention Inc v. Dell Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: WeCrevention, Inc. (Texas)
  • Defendant: Dell Inc. and Dell Technologies, Inc. (Delaware)
  • Plaintiff's Counsel: Fabricant LLP
• Case Identification: 1:26-cv-01958, E.D. Tex., 10/10/2025
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas based on Dell's purported regular and established places of business within the district. These allegedly include a secured Dell facility in Flower Mound, the homes of numerous remote field employees, the physical locations of partners in the Dell Partner Program, and retail locations of authorized sellers.
• Core Dispute: Plaintiff alleges that Defendant's laptop computers containing LPDDR5 and LPDDR5x DRAM infringe five patents related to reconfigurable memory interfaces, power management in DRAM, and high-speed data bus architectures.
• Technical Context: The lawsuit concerns the architecture and operation of high-speed memory subsystems in modern electronics, a field critical to balancing performance, power consumption, and battery life in devices like laptops.
• Key Procedural History: The complaint alleges that Defendant has previously admitted or not contested personal jurisdiction in the Eastern District of Texas in prior, unrelated litigation.

Case Timeline

Date	Event
2011-10-11	Priority Date for '834 and '942 Patents
2012-07-17	Priority Date for '017, '098, and '652 Patents
2015-10-20	'942 Patent Issued
2015-12-01	'834 Patent Issued
2019-09-01	Alleged First Infringing Sales of Accused Products with LPDDR5
2021-05-04	'017 Patent Issued
2024-02-06	'098 Patent Issued
2024-11-26	'652 Patent Issued
2025-10-10	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,201,834 - "Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module"

• Patent Identification: U.S. Patent No. 9,201,834 ("Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module"), issued December 1, 2015. Compl. ¶21

The Invention Explained

• Problem Addressed: The patent's background section describes the challenges of integrating memory and logic components that are manufactured using different and increasingly advanced semiconductor processes, which can lead to issues like poor heat dissipation, power consumption, and noise interference. '834 Patent, col. 1:44-56 It notes that rigid industry standards for memory interfaces limit flexibility and optimization. '834 Patent, col. 1:35-43
• The Patented Solution: The invention proposes a memory system with a reconfigurable bus architecture. A logic unit communicates with a group of memory ICs over a "first transmission bus" that features programmable characteristics, such as data rate and signal swing. Compl. ¶34 This allows the interface to be adapted to different memory types and processor requirements, moving beyond a one-size-fits-all standard. '834 Patent, abstract '834 Patent, col. 2:5-20
• Technical Importance: This reconfigurable approach provides flexibility to optimize power and performance when integrating memory and logic chips from different technology generations or for different applications. '834 Patent, col. 2:35-48

Key Claims at a Glance

• The complaint asserts independent claim 21. Compl. ¶34
• The essential elements of claim 21 include:
  • An electronics system device comprising an application-specific integrated circuit (ASIC) processor;
  • A type of memory cell array group comprising multiple memory cell array ICs;
  • A first transmission bus coupled to the memory group, having a first programmable data rate and signal swing corresponding to firmware or software in the ASIC processor;
  • A logic unit coupled to the first transmission bus for accessing the memory group; and
  • A second transmission bus coupled between the logic unit and the ASIC processor, having a second programmable data rate and signal swing associated with the firmware or software in the ASIC processor.

U.S. Patent No. 10,998,017 - "Dynamic random access memory applied to an embedded display port"

• Patent Identification: U.S. Patent No. 10,998,017 ("Dynamic random access memory applied to an embedded display port"), issued May 4, 2021. Compl. ¶22

The Invention Explained

• Problem Addressed: The patent's background explains that while panel self-refresh (PSR) in embedded display port (eDP) systems can save power by turning off the graphics processor, it requires a frame buffer (like a DRAM) that itself consumes power, partially offsetting the savings. '017 Patent, col. 1:35-62 Standard DRAMs operate at voltages defined by industry standards that are not optimized for such low-power use cases. '017 Patent, col. 3:20-28
• The Patented Solution: The patent discloses a DRAM architecture designed for lower power consumption by operating its internal circuits at reduced voltages. The invention claims a DRAM where both the "DRAM core cell" and a "peripheral circuit" are supplied by voltages lower than 1.1V, in contrast to higher standard operating voltages. '017 Patent, abstract '017 Patent, col. 2:1-8
• Technical Importance: By enabling DRAM to operate at lower voltages, the invention aims to reduce the power consumption of frame buffers, thereby enhancing the effectiveness of power-saving features like PSR and extending the battery life of portable devices. '017 Patent, col. 2:20-34

Key Claims at a Glance

• The complaint asserts independent claim 1. Compl. ¶50
• The essential elements of claim 1 include:
  • A DRAM comprising a DRAM core cell supplied with a first voltage lower than 1.1V;
  • A peripheral circuit electrically connected to the DRAM core cell, supplied with a second voltage lower than 1.1V;
  • The DRAM core cell and peripheral circuit are formed on a single chip, with the peripheral circuit being external to the DRAM core cell; and
  • The first and second voltages are capable of making the DRAM applicable to an embedded display port (eDP).

U.S. Patent No. 11,894,098 - "Dynamic random access memory applied to an embedded display port"

• Patent Identification: U.S. Patent No. 11,894,098 ("Dynamic random access memory applied to an embedded display port"), issued February 6, 2024. Compl. ¶23
• Technology Synopsis: This patent, a continuation of the '017 Patent's family, further refines the low-power DRAM concept. It specifically claims a DRAM where the core cell and an external peripheral circuit are supplied by different voltages, with both voltages being lower than 1.1V. This differentiation enables more granular power management by tailoring voltages to the specific needs of the memory array versus its supporting logic. Compl. ¶64 '098 Patent, abstract
• Asserted Claims: The complaint asserts at least claim 1. Compl. ¶64
• Accused Features: The LPDDR5 DRAM in the Accused Products is alleged to infringe by using distinct, low-voltage power rails (e.g., VDD2H and VDD2L) for the core and peripheral circuits, respectively. Compl. ¶¶66-69

U.S. Patent No. 12,154,652 - "Dynamic random access memory applied to an embedded display port"

• Patent Identification: U.S. Patent No. 12,154,652 ("Dynamic random access memory applied to an embedded display port"), issued November 26, 2024. Compl. ¶24
• Technology Synopsis: Also in the same family as the '017 Patent, this patent targets power savings in the data interface of a DRAM. It claims a DRAM where the core cell and the input/output (I/O) circuit operate on different voltages (a "first voltage" and a "third voltage," respectively), both of which are below 1.1V. This allows for independent power optimization of the I/O circuitry. Compl. ¶77 '652 Patent, abstract
• Asserted Claims: The complaint asserts at least claim 1. Compl. ¶77
• Accused Features: The complaint alleges that the LPDDR5 DRAM in Dell's products infringes by using separate and different power rails for the memory core (e.g., VDD2H/VDD2L) and the I/O buffer (e.g., VDDQ), with all relevant voltages being below 1.1V. Compl. ¶¶79-84

U.S. Patent No. 9,164,942 - "High speed memory chip module and electronics system device with a high speed memory chip module"

• Patent Identification: U.S. Patent No. 9,164,942 ("High speed memory chip module and electronics system device with a high speed memory chip module"), issued October 20, 2015. Compl. ¶25
• Technology Synopsis: Related to the '834 Patent, this invention describes a memory architecture for optimizing data throughput. It claims a system where a logic unit accesses memory ICs over a wide parallel bus (the "first transmission bus") and converts that data into a "second set of parallel data" of a different bit width for the main processor. This bus-width conversion allows for efficient data handling between components with different interface requirements. Compl. ¶92 '942 Patent, abstract
• Asserted Claims: The complaint asserts at least claim 19. Compl. ¶92
• Accused Features: The complaint alleges that the Integrated Memory Controller (IMC) in Dell's products acts as the claimed "logic unit," communicating with the LPDDR5 DRAM module over a wide bus and converting the data to a different width for the processor cores, thus infringing the patent. Compl. ¶¶97-101

III. The Accused Instrumentality

Product Identification

• The complaint identifies Dell products that include LPDDR5 DRAM and LPDDR5x DRAM technology, sold since September 2019. Compl. ¶28 Specific product lines named are the XPS, Dell Plus, Latitude, and Precision series, with the Dell XPS 13 Plus 9320 used as a representative example. Compl. ¶¶28, 35

Functionality and Market Context

• The accused products are laptops that incorporate Intel "Alder Lake" processors and LPDDR5 DRAM modules. Compl. ¶¶35-37 The complaint focuses on the technical operation of the memory subsystem, alleging it uses features that map to the patent claims. These include Dynamic Voltage and Frequency Scaling (DVFS) to adjust memory speed and voltage, the use of multiple distinct voltage rails (VDD2H, VDD2L, VDDQ) for different parts of the DRAM chip, an Integrated Memory Controller (IMC) that manages memory access, and an internal "ring interconnect" for on-chip data transfer. (Compl. ¶38; Compl. ¶39; Compl. ¶40; Compl. ¶41; Compl. ¶42).
• The complaint's technical allegations are supported by references to public documentation for the Intel Alder Lake processor and the JEDEC LPDDR5 standard. Compl. ¶36 Compl. ¶39 A product information table for the Dell XPS 13 Plus 9320 is included to identify key components like the Core i7 processor and 16 GB of LPDDR5 RAM. Compl. p. 13, table

IV. Analysis of Infringement Allegations

U.S. Patent No. 9,201,834 Infringement Allegations

The complaint includes a diagram showing the accused Alder Lake processor's memory subsystem and its support for various DRAM types, including LPDDR5. Compl. p. 14, fig. It also provides a diagram illustrating the "Alder Lake Interconnect," which is alleged to function as the claimed second transmission bus. Compl. p. 19, fig.

Claim Element (from Independent Claim 21)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
an application-specific integrated circuit (ASIC) processor	The Intel Core i7 "Alder Lake" processor included in the Accused Products.	¶36	col. 2:5-6
a type of memory cell array group, wherein the type of memory cell array group comprises multiple memory cell array ICs	The 16GB LPDDR5 DRAM module, which is comprised of multiple memory ICs.	¶37	col. 3:39-44
a first transmission bus coupled to the type of memory cell array group having a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing corresponding to firmware or software comprised in the ASIC processor	The memory bus connecting the Alder Lake processor's Integrated Memory Controller (IMC) to the LPDDR5 DRAM module. Programmability is alleged to be provided by Dynamic Voltage and Frequency Scaling (DVFS), which is controlled by the processor.	¶¶38-40	col. 4:5-24
a logic unit coupled to the first transmission bus for accessing the type of memory cell array group through the first transmission bus	The Integrated Memory Controller (IMC) located within the Alder Lake processor.	¶41	col. 4:1-4
a second transmission bus coupled between the logic unit and the ASIC processor having a second programmable transmitting or receiving data rate, a second programmable transmitting or receiving signal swing associated to the firmware or the software comprised in the ASIC processor	The "ring interconnect" within the Alder Lake processor, which connects the IMC to the processor cores. Programmability is alleged based on dynamic frequency changes and power state management (C-States) controlled by the processor.	¶42	col. 2:1-4

• Identified Points of Contention:
  • Scope Questions: A central question will be whether the integrated architecture of the accused Alder Lake processor fits the claimed structure. The court may need to decide if the term "ASIC processor" can read on a general-purpose CPU and whether an on-die "ring interconnect" can be considered a "bus coupled between the logic unit and the ASIC processor" when the logic unit (IMC) is itself part of the same processor die.
  • Technical Questions: The analysis may focus on whether the standard, automatic power-saving features of the accused products, such as DVFS and C-States, meet the claim requirement for a "programmable" bus. The dispute may turn on whether "programmable" implies a deliberate, persistent configuration (as the patent's background suggests) or if it can encompass the dynamic, on-the-fly adjustments inherent in modern computer systems.

U.S. Patent No. 10,998,017 Infringement Allegations

The complaint provides a table from the JEDEC LPDDR5 specification showing the recommended operating voltages for various power rails, including VDD2H and VDD2L, are typically below 1.1V. Compl. p. 24, table A diagram from a JEDEC workshop is also used to illustrate the architectural separation of the "DRAM Core" and the "Peri[pheral]" circuits. Compl. p. 25, fig.

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a DRAM core cell...supplied with a first voltage...wherein the first voltage is lower than 1.1V	The core cells of the LPDDR5 DRAM, which are allegedly supplied by the VDD2H or VDD2L power rails. The complaint cites JEDEC standards showing these voltages are typically 1.05V or 0.9V.	¶¶52-53	col. 6:1-4
a peripheral circuit...supplied with a second voltage...wherein the second voltage is lower than 1.1V	The buffers and other data path circuits within the LPDDR5 DRAM. These are also alleged to be supplied by the VDD2H or VDD2L rails at voltages below 1.1V.	¶54	col. 6:5-10
wherein the DRAM core cell and the peripheral circuit are formed on a single chip, and the peripheral circuit is external to the DRAM core cell	The typical monolithic construction of LPDDR5 DRAM chips, where peripheral logic is architecturally distinct from the core memory arrays but fabricated on the same piece of silicon.	¶55	col. 6:11-14
wherein the first voltage and the second voltage are capable of making the DRAM be applied to an embedded display port (eDP)	An allegation that the LPDDR5 DRAM module "may be applied to" an eDP and that the accused Dell devices use the eDP protocol for their displays.	¶56	col. 6:16-19

• Identified Points of Contention:
  • Scope Questions: A key issue may be the "capable of" limitation. The court will have to determine whether the accused DRAM's mere capability of being used in an eDP application is sufficient to infringe, particularly if its actual use in the accused laptops is as general system memory, not as a dedicated frame buffer as described in the patent's background.
  • Technical Questions: The infringement theory relies heavily on mapping the functionality described in public JEDEC standards to the specific DRAM components used by Dell. A point of contention could be whether the circuits Dell actually uses operate in the manner alleged and whether the general categories of "DRAM core cell" and "peripheral circuit" in the claim map cleanly onto the physical structures within the accused LPDDR5 chips.

V. Key Claim Terms for Construction

For the '834 Patent

• The Term: "programmable"
• Context and Importance: This term appears in the limitations for both the first and second transmission buses in claim 21. Its construction is critical because if it is interpreted narrowly to require a specific type of reconfigurability beyond standard, automatic power management, the infringement case may be weakened. Practitioners may focus on this term because the plaintiff's theory equates standard Dynamic Voltage and Frequency Scaling (DVFS) with the claimed "programmable" feature.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification discusses varying signal swings and data rates to optimize performance, which could be read to encompass any mechanism, including automatic ones like DVFS, that achieves this result. '834 Patent, col. 5:34-49
  • Evidence for a Narrower Interpretation: The patent's summary and background emphasize reconfiguring the bus to accommodate different memory standards or ASIC processes, suggesting a more fundamental, persistent configuration rather than the transient, sub-second adjustments of DVFS. '834 Patent, abstract '834 Patent, col. 2:35-48

For the '017 Patent

• The Term: "peripheral circuit"
• Context and Importance: Claim 1 requires the "peripheral circuit" to be "external to the DRAM core cell" while being "formed on a single chip." The definition of this term and its boundary with the "DRAM core cell" is central to the infringement analysis. A defendant might argue that the circuits identified by the plaintiff are functionally integral to the core, not "external" in the manner contemplated by the patent.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent's main figure depicts a clear block diagram with a distinct "memory core unit" (102) and "peripheral circuit unit" (104), suggesting the patentee intended a clear architectural division. '017 Patent, FIG. 1
  • Evidence for a Narrower Interpretation: The specification provides little explicit definition of the boundary between the core and peripheral circuits. A defendant could argue that in a highly integrated modern DRAM, any such distinction is artificial and that the allegedly "peripheral" circuits are functionally inseparable from the core memory operations.

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement for all five patents-in-suit. The inducement allegations are based on Dell's affirmative acts of selling the Accused Products and providing instructions, user manuals, and technical support that allegedly encourage customers to use the products in an infringing manner. Compl. ¶¶43-44 Compl. ¶¶57-58
• Willful Infringement: Willfulness is alleged based on pre-suit and post-suit knowledge. The complaint asserts pre-suit knowledge based on Dell's position as a major technology company that monitors memory advancements. Compl. ¶29 It alternatively alleges willful blindness, claiming Dell maintains a policy of not reviewing third-party patents. Compl. ¶29 Post-suit knowledge is based on the filing of the lawsuit itself. Compl. ¶30

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of architectural mapping: can the distinct components described in the '834 and '942 patents (e.g., "logic unit," "ASIC processor," "first transmission bus," "second transmission bus") be read onto the highly integrated, on-die structures of a modern System-on-a-Chip (SoC), where functions like the memory controller, CPU cores, and internal interconnects are part of a single silicon die?
• A second key issue will be a question of functional equivalence: do the accused products' implementations of industry-standard features, such as LPDDR5's Dynamic Voltage and Frequency Scaling (DVFS), constitute the specific "programmable" reconfigurability claimed in the '834 patent or the distinct multi-voltage operations claimed in the '017, '098, and '652 patents? The outcome may depend on whether these standard features perform the functions in the manner required by the claims.
• Finally, for the '017 patent family, the case may turn on a question of capability versus use: is the mere "capability" of the accused LPDDR5 DRAM to be applied in an embedded Display Port system sufficient to satisfy the claim limitation, even if its actual implementation in the accused laptops is for general-purpose system memory?