Empire Technology Development LLC v. Intel Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Empire Technology Development LLC (Delaware)
  • Defendant: Intel Corporation (Delaware)
  • Plaintiff's Counsel: Folio Law Group PLLC
• Case Identification: 1:26-cv-00989, W.D. Tex., 04/17/2026
• Venue Allegations: Venue is alleged to be proper in the Western District of Texas because Defendant Intel maintains a regular and established place of business in the district, including a research and development facility in Austin, and has committed acts of alleged infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant's Xeon Scalable Processors, which utilize Intel's Mesh Architecture, infringe a patent related to scalable on-chip interconnection networks.
• Technical Context: On-chip interconnection networks are the communication backbone for modern multi-core processors, and their design is critical for determining overall system performance, latency, and scalability.
• Key Procedural History: Plaintiff Empire Technology Development LLC is the exclusive licensee of the patent-in-suit, which was originally assigned to the Board of Regents of the University of Texas System by its inventors. The complaint notes that Intel has previously agreed to personal jurisdiction and venue in the Western District of Texas in other patent cases.

Case Timeline

Date	Event
2008-08-26	Exclusive license granted by UT System to Plaintiff's predecessor
2009-06-19	Priority Date for U.S. Patent No. 8,307,116
2012-11-06	U.S. Patent No. 8,307,116 Issued
2017-06-05	License Agreement assigned to Plaintiff Empire
2017-07-01	Earliest alleged launch of Accused Products (Q3 2017)
2026-04-17	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,307,116 - "Scalable Bus-based On-chip Interconnection Networks"

• Patent Identification: U.S. Patent No. 8,307,116, "Scalable Bus-based On-chip Interconnection Networks," issued November 6, 2012 (the "'116 Patent").

The Invention Explained

• Problem Addressed: The patent addresses the challenge of scaling on-chip interconnection networks for multi-core processors Compl. ¶24 As the number of processing nodes (cores) grew from "dozens to hundreds," existing network topologies became inefficient '116 Patent, col. 2:21-24 They either caused high latency by routing data packets through multiple intermediate "hops" or used a large number of dedicated links, which were not easily scalable and resulted in low channel utilization '116 Patent, col. 3:1-13 Compl. ¶25
• The Patented Solution: The '116 Patent discloses a network architecture for a "multinodal array" of processing nodes that aims to improve efficiency and reduce latency Compl. ¶26 The solution involves a specific physical arrangement of communication channels, including horizontal and vertical pathways, that connect the nodes '116 Patent, Fig. 5 A key aspect of the invention is the configuration of these channels to allow data to be routed from a source node to any other node in the array using a "maximum of two hops" '116 Patent, col. 6:55-61 The architecture also contemplates channels that can route data from one source to multiple destinations simultaneously, acting as a shared bus '116 Patent, col. 5:62-65
• Technical Importance: This approach sought to provide a more efficient and scalable on-chip communication fabric, a foundational element for improving the performance of high-core-count processors used in high-throughput computing Compl. ¶27

Key Claims at a Glance

• The complaint asserts at least independent claim 1 of the '116 Patent Compl. ¶32
• The essential elements of independent claim 1 are:
  • A "multinodal array" with a plurality of nodes.
  • A "plurality of physical communication channels" arranged in a specific topology, extending along horizontal and vertical rows of nodes, where the number of nodes in a row is equal to the number of channels extending along that row.
  • The channels are configured to connect the nodes, with a "first physical communication channel" connecting a first node to "at least two" other nodes.
  • The first channel is configured to route data from the first node to those "at least two" nodes.
  • The plurality of channels are arranged to route data between the first node and "any" of the other nodes "using a maximum of two hops."
• The complaint does not explicitly reserve the right to assert dependent claims but notes its infringement example is non-limiting and preliminary Compl. ¶34

III. The Accused Instrumentality

Product Identification

• The complaint identifies "certain processors including the Xeon Scalable Processors" and other processors containing similar structures as the "Accused Products" Compl. ¶2

Functionality and Market Context

• The complaint alleges that the Accused Products incorporate "Intel® Mesh Architecture," which it describes as a "breakthrough CPU design" that replaced Intel's prior "Ring Architecture" Compl. ¶37 This architecture is characterized as a "mesh network of nodes" for data communication between multiple processing cores Compl. ¶36
• The complaint presents a diagram from Intel's marketing materials that contrasts the older Ring Architecture with the newer Mesh Architecture, highlighting benefits of the mesh design such as maximized performance, consistent low latencies, and optimized data sharing Compl. ¶37 A technical diagram from Intel's literature shows the mesh architecture as a grid of cores and other components connected by a network of vertical and horizontal communication paths Compl. ¶44
• The complaint alleges that this mesh architecture allows for data traversal from one core to another via a "shortest path," which it defines as a "hop on vertical path to correct row, and hop across horizontal path to correct column" Compl. ¶44

IV. Analysis of Infringement Allegations

'116 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
[a] a multinodal array having a plurality of nodes, including a first node;	The Accused Products allegedly comprise a "multinodal array" in the form of a "mesh network of nodes" with multiple processing cores (Compl. ¶38). Intel's documentation describes the architecture as an array of cores and other agents on a mesh interconnect (Compl. ¶39).	¶38	col. 3:36-39
[b] a plurality of physical communication channels extending along a first row of nodes in a horizontal direction of the array and along a second row of nodes in a vertical direction of the array so as to form a plurality of rows of physical communication channels, a first number of nodes... located along the first row being equal to a number of rows of physical communication channels that extend along the first row... and a second number of nodes... located along the second row being equal to a number of rows of physical communication channels that extend along the second row...	The Accused Products allegedly include "vertical and horizontal communication paths" that form a plurality of communication channels (Compl. ¶40). The complaint alleges the number of nodes in a row/column equals the number of communication channels along that row/column (Compl. ¶41; Compl. ¶42).	¶¶40-42	col. 6:20-41
...the plurality of physical communication channels configured to connect the plurality of nodes, including a first physical communication channel connecting the first node with at least two of the plurality of nodes;	The horizontal and vertical paths are allegedly configured to connect the nodes/cores (Compl. ¶43). The complaint alleges a first physical channel (e.g., a horizontal path) connects a source node with at least two other nodes (Compl. ¶43).	¶43	col. 5:62-65
[c] wherein the first physical communication channel is configured to route the data from the first node to the at least two of the plurality of nodes;	The complaint alleges that a source node routes data to other nodes in the mesh network (Compl. ¶46). It further alleges that Intel's architecture allows a node to have a direct connection with at least two other nodes in the mesh (Compl. ¶46).	¶¶45-46	col. 8:35-39
[d] wherein the plurality of physical communication channels are arranged to route data between the first node and any of the plurality of nodes, including nodes other than the at least two of the plurality of nodes, using a maximum of two hops on the plurality of physical communication channels.	The Accused Products are alleged to route data between a source node and any destination node using a maximum of two hops Compl. ¶47 The complaint characterizes this as "(1) hop on vertical path to correct row, and further (2) hop across horizontal path to correct column" (Compl. ¶47; Compl. ¶48).	¶¶47-48	col. 6:57-61

Identified Points of Contention:

• Scope & Technical Question: A central issue may be the interpretation of "using a maximum of two hops." The claim requires this for routing between a first node and "any" of the plurality of other nodes. The complaint's theory appears to be that Intel's X-Y routing (one vertical move, one horizontal move) satisfies this limitation Compl. ¶47 The court may need to determine what constitutes a "hop" as contemplated by the patent and whether the accused architecture meets this performance requirement under all conditions.
• Scope Question: The claim recites a very specific topological constraint: that the number of nodes along a row equals the number of communication channels extending along that row Compl. ¶33 The infringement analysis may hinge on whether the physical layout of Intel's Mesh Architecture satisfies this precise structural limitation, which could be a significant point of dispute.
• Technical Question: The claim requires a "first physical communication channel" that is configured to route data from a source node to "at least two" other nodes. The complaint alleges this is met Compl. ¶45, but the evidence provided focuses on point-to-point "shortest path" traversal Compl. ¶44 The ability to function as a multi-drop bus, as this limitation suggests, may require further evidence beyond what is presented.

V. Key Claim Terms for Construction

• The Term: "using a maximum of two hops"

• Context and Importance: This functional limitation appears in the final clause of claim 1 and sets a strict performance requirement for the entire network. Its definition is critical to the infringement analysis, as it dictates the required efficiency of the routing scheme. Practitioners may focus on this term because it is a quantitative limit that could be dispositive if the accused products are shown not to meet it for "any" node pair.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The specification provides an example: "data...may be routed from node 104(1) to node 104(16) in two hops using shared communication channels 507 and 509" '116 Patent, col. 6:57-61 This could be argued as illustrative, allowing for different definitions of a "hop" (e.g., a change in direction in an X-Y routing scheme) rather than strictly traversing two channel segments.
  • Evidence for a Narrower Interpretation: The background section uses the term "hop" to describe data passing through "intermediate routing devices" between "point-to-point network connection[s]" '116 Patent, col. 3:4-6 This context may support a narrower definition where a "hop" is the traversal of a link between two adjacent routers or nodes.

• The Term: "a first number of nodes ... being equal to a number of rows from the plurality of rows of physical communication channels that extend along the first row"

• Context and Importance: This term defines a precise, quantitative relationship between the number of processing nodes in a row and the number of parallel communication channels serving that row. The infringement case rests on whether Intel's mesh physically embodies this specific 1:1 structural correspondence.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: A party might argue this language should be interpreted functionally, requiring only a sufficient number of channels to service the nodes in a row, rather than a strict numerical equality. The overall goal is scalability, which this feature supports.
  • Evidence for a Narrower Interpretation: The language is highly specific and appears to be definitional. The patent states, "the array 102 may also contain four nodes 104 in each horizontal row...and...four rows of communication channels along each horizontal row" '116 Patent, col. 6:42-49, providing a clear example that reinforces a literal, one-to-one interpretation.

VI. Other Allegations

• Indirect Infringement: The complaint does not provide sufficient detail for analysis of indirect infringement. It does not plead specific facts to support active inducement or contributory infringement.
• Willful Infringement: The complaint does not provide sufficient detail for analysis of willful infringement. It does not allege pre-suit knowledge of the '116 Patent or its infringement.

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the specific and dense topological language of claim 1, which requires a precise numerical equality between nodes and channels in a given row, be read to cover the physical implementation of Intel's Mesh Architecture?
• A key evidentiary question will be one of functional performance: does Intel's "shortest path" X-Y routing scheme ensure that data can be routed between "any" two nodes in the array "using a maximum of two hops," as the claim requires, and how will the term "hop" be construed in this technical context?
• A third central question will concern structural equivalence: does the accused architecture, which is described as enabling point-to-point traversal, also contain a "physical communication channel" configured to route data from a single source to "at least two" other nodes, as required by a separate limitation in the claim?