DCT
1:26-cv-00936
Flex Loading Tech LLC v. Gowin Semiconductor Corp
Key Events
Complaint
Table of Contents
complaint Intelligence
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Flex Loading Technologies, LLC (Delaware)
- Defendant: Gowin Semiconductor Corporation (China)
- Plaintiff's Counsel: Daignault Iyer LLP
- Case Identification: 1:26-cv-00936, W.D. Tex., 04/14/2026
- Venue Allegations: Venue is alleged to be proper because the Defendant is a foreign corporation, which may be sued in any judicial district. The complaint further supports venue by alleging Defendant transacts business in the district and has employees located in Austin, Texas.
- Core Dispute: Plaintiff alleges that Defendant's Field-Programmable Gate Array (FPGA) products and associated software tools infringe a patent directed to methods for flexibly and efficiently loading hardware behaviors onto reconfigurable computing resources.
- Technical Context: The technology relates to reconfigurable computing, specifically the dynamic allocation of resources within FPGAs, which are semiconductor devices that can be configured by a customer or a designer after manufacturing.
- Key Procedural History: The complaint alleges that Plaintiff provided Defendant with pre-suit notice of infringement via a letter and draft complaint on or about January 6, 2025, followed by additional correspondence.
Case Timeline
| Date | Event |
|---|---|
| 2009-08-18 | '212 Patent Priority Date |
| 2012-05-08 | '212 Patent Issue Date |
| 2025-01-06 | Pre-suit notice letter allegedly sent to Defendant |
| 2025-02-07 | Defendant's counsel allegedly responded to notice letter |
| 2025-03-11 | Parties allegedly exchanged additional correspondence |
| 2025-03-17 | Plaintiff's counsel allegedly sent an email to Defendant's counsel |
| 2025-04-03 | Plaintiff's counsel allegedly sent a follow-up email to Defendant's counsel |
| 2026-04-14 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 8,176,212 - "Method and System for Hierarchical and Joinable Behavior Containers for Reconfigurable Computing"
The Invention Explained
- Problem Addressed: The patent describes a problem in reconfigurable computing where hardware resources (like FPGAs) are partitioned into fixed-size regions for loading different software tasks, or "behaviors" ʼ212 Patent, col. 1:33-41 This static partitioning can be inefficient; a small task might waste space in a large, pre-defined region, while a large task might be unable to run if no single region is big enough, leading to a condition called "thrashing" ʼ212 Patent, col. 6:41-49
- The Patented Solution: The invention proposes a method for more flexible resource allocation using "hierarchical behavior containers" ʼ212 Patent, abstract Instead of fixed-size regions, the system defines a hierarchy of nested containers of various sizes. When a new hardware behavior needs to be loaded, a hierarchical process selects the "smallest hierarchical behavior container available" that can accommodate the task ʼ212 Patent, col. 13:1-7 This dynamic sizing aims to improve the efficiency and utilization of the reconfigurable computing resource ʼ212 Patent, col. 12:18-24 The decision process is illustrated in a flowchart that shows a search starting at the smallest container size and moving up the hierarchy as needed ʼ212 Patent, FIG. 5
- Technical Importance: This approach addresses a fundamental challenge in maximizing the utility of expensive and complex reconfigurable hardware by enabling more granular and on-demand resource allocation than a static partitioning scheme allows ʼ212 Patent, col. 12:18-24
Key Claims at a Glance
- The complaint asserts at least independent claim 1 Compl. ¶26
- The essential elements of independent claim 1 include:
- defining a configuration of hierarchical behavior container regions on a reconfigurable computer resource according to allowable electrical boundary limitations;
- selecting a hierarchical behavior container to load a hardware behavior according to a hierarchical process, wherein the behavior is loaded into the smallest hierarchical behavior container available; and
- loading the hardware behavior into the selected container.
- The complaint does not explicitly reserve the right to assert dependent claims.
III. The Accused Instrumentality
Product Identification
The accused instrumentalities are Defendant's LittleBee FPGA product family (e.g., GW1N, GW1NR, GW1NS, etc.) and the associated hardware and software components, collectively referred to as the "Defendant's System" Compl. ¶7 Compl. ¶10
Functionality and Market Context
The complaint describes the LittleBee FPGAs as flash-based, non-volatile devices containing arrays of Configurable Logic Units (CLUs) Compl. ¶8 Compl. p. 14 The "Defendant's System" includes the Gowin YunYuan Software, a hardware development environment used to synthesize hardware description language, manage placement and routing, and generate the bitstream files that configure the FPGA Compl. ¶29 Compl. p. 11 The complaint alleges these products are used for applications requiring low power and instant-on programmable computing Compl. ¶8 A screenshot from a product datasheet shows an architectural overview of a GW1NS-4C device, identifying core components like CLUs, Block SRAM, and a Cortex-M3 processor Compl. p. 9
IV. Analysis of Infringement Allegations
'212 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| defining a configuration of hierarchical behavior container regions on said reconfigurable computer resource according to allowable electrical boundary limitations of said reconfigurable computer resource; | Defendant's Gowin YunYuan software is allegedly used to create a "hierarchical coded design" that is synthesized into "hierarchical Configurable Logic Sections (CLSs)." The "allowable electrical boundary limitations" are allegedly met by using the Gowin Power Analyzer to estimate and constrain power dissipation. | ¶¶28-30 | col. 12:63-67 |
| selecting a hierarchical behavior container on said reconfigurable computer resource to load said hardware behavior according to a hierarchical process wherein said hardware behavior is loaded into the smallest hierarchical behavior container available in a configuration of hierarchical behavior container regions on said reconfigurable computer resource; | The accused hierarchical process is the selection and combination of one or more CLSs to implement a logic function. The complaint alleges this corresponds to forming different sized look-up tables (LUTs) from a variable number of CLSs, which is presented as selecting the "smallest" available container for the application. | ¶31 | col. 13:1-7 |
| loading said hardware behavior into said selected hierarchical behavior container. | This is alleged to be the process of loading the bitstream data into the selected CLS(s) on the LittleBee FPGA, thereby configuring the device's logic. | ¶32 | col. 13:8-9 |
- Identified Points of Contention:
- Scope Questions: The infringement theory raises a question of temporal scope. The '212 Patent appears to describe a dynamic, run-time resource management system ʼ212 Patent, FIG. 5, whereas the complaint's allegations focus on a design-time synthesis and place-and-route process using the Gowin YunYuan software Compl. ¶29 A central dispute may be whether a process performed at design-time to generate a static configuration can infringe a claim that describes a dynamic, run-time selection process.
- Technical Questions: A key technical question is whether the accused functionality of combining "Configurable Logic Sections (CLSs)" to form larger logic blocks Compl. ¶31 is equivalent to the patent's "hierarchical process" of selecting the "smallest hierarchical behavior container available" ʼ212 Patent, col. 13:3-5 The complaint presents a screenshot showing how developers can control hierarchy during synthesis using a "syn_hier" attribute, which may support its theory of a defined hierarchical configuration Compl. p. 11 However, it raises the question of whether this design-time directive equates to the patent's run-time selection algorithm. Another screenshot shows the Gowin Power Analyzer is used to estimate power dissipation, which the complaint links to the "electrical boundary limitations" element Compl. p. 13
V. Key Claim Terms for Construction
The Term: "hierarchical behavior container regions"
- Context and Importance: This term is the central object of the claimed method. The outcome of the case may depend on whether Defendant's "hierarchical Configurable Logic Sections (CLSs)," which are created during a design-time synthesis process Compl. ¶29, are construed to be the same as the patent's "hierarchical behavior container regions."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent describes the containers abstractly as a hierarchy of nested rectangles, which could be argued to cover any logical partitioning scheme that is hierarchical in nature ʼ212 Patent, FIG. 3A ʼ212 Patent, col. 9:1-13
- Evidence for a Narrower Interpretation: The specification repeatedly links these containers to a dynamic, run-time process. It states that lower hierarchical levels "are created (and recreated during operation as needed)" and that the selection process is initiated by a "loadable behavior requested by an application process," suggesting these are not static, pre-compiled structures ʼ212 Patent, col. 10:27-29 ʼ212 Patent, col. 11:45-48
The Term: "smallest hierarchical behavior container available"
- Context and Importance: This phrase defines the core optimization criterion of the claimed selection process. The dispute may focus on whether the accused system performs this specific type of optimized selection.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: This could be argued to encompass any resource allocation process that attempts to use logic resources efficiently, without necessarily following a specific algorithm.
- Evidence for a Narrower Interpretation: The patent's flowchart in Figure 5 and the accompanying description detail a specific search algorithm: "The sequence begins at the smallest sized containers, known as the 'leaf' level of the hierarchy, and proceeds by considering... each container... at that level" before moving to a higher level ʼ212 Patent, FIG. 5 ʼ212 Patent, col. 11:45-51 This suggests a specific, structured search process, not just a general goal of efficiency.
VI. Other Allegations
- Indirect Infringement: The complaint alleges that Defendant "provides the method for defining a configuration" Compl. ¶28, "provides the method for selecting a hierarchical behavior container" Compl. ¶31, and "provides the method for loading" Compl. ¶32 This language, which focuses on Defendant enabling or providing a method for others to use, suggests a basis for a claim of induced infringement under 35 U.S.C. § 271(b), although the complaint's first count is formally for direct infringement under § 271(a) Compl. ¶33
- Willful Infringement: The complaint alleges willful infringement on the basis of pre-suit knowledge. It claims that Defendant was put on notice of the '212 Patent and the infringement allegations via a letter and draft complaint sent on or about January 6, 2025, and that Defendant continued its accused activities despite this knowledge Compl. ¶¶34-40
VII. Analyst's Conclusion: Key Questions for the Case
- A core issue will be one of temporal application: can the patent's method, which describes a dynamic, run-time process for selecting and loading hardware behaviors based on an application's request, be construed to cover Defendant's accused system, which appears to involve a design-time process where a hierarchical logic structure is defined and synthesized before the FPGA is ever programmed?
- A related, dispositive question will be one of definitional equivalence: do Defendant's "hierarchical Configurable Logic Sections," which are artifacts of a hardware description language and synthesis toolchain, constitute the "hierarchical behavior container regions" described in the patent, which are portrayed as flexible entities managed at run-time by a host system?
- An evidentiary question will be one of functional operation: what evidence will show that the accused system actually performs the claimed step of selecting the "smallest... container available" according to the hierarchical process detailed in the patent, as opposed to simply implementing a user-defined design that happens to be structured hierarchically?
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