DCT

1:26-cv-00259

Vervain LLC v. SK Hynix Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:26-cv-00259, W.D. Tex., 02/03/2026
  • Jurisdiction: The complaint pleads subject-matter jurisdiction under 28 U.S.C. §§ 1331 and 1338(a) and 35 U.S.C. §§ 271 et seq. Compl. ¶21 It separately pleads personal jurisdiction under the Due Process Clause and the Texas Long-Arm Statute, Tex. Civ. Prac. & Rem. Code §§ 17.041 et seq., based on Defendants doing business in Texas, recruiting Texas residents, committing acts of patent infringement in Texas and the District, and placing the Accused Products into the stream of commerce Compl. ¶22
  • Venue Allegations: Plaintiff alleges venue is proper because Defendants have committed acts of infringement in the district and maintain regular and established places of business, including offices and sales and technical staff in Austin, Texas, to serve major customers such as Dell Technologies.
  • Jury Demand & Division: The complaint is brought in the Austin Division of the Western District of Texas and demands a jury trial.
  • Core Dispute: Plaintiff alleges that Defendant's flash memory products, including solid-state drives (SSDs), infringe seven patents related to methods for managing data between high-endurance single-level cell (SLC) and high-density multi-level cell (MLC) memory to improve device lifetime and performance.
  • Technical Context: The technology addresses a fundamental trade-off in flash memory design between the high cost and endurance of SLC memory and the lower cost and endurance of MLC memory, a critical issue for the SSD market.
  • Key Procedural History: The complaint notes that many of the asserted patents have been asserted in prior or pending litigation against Phison, Kingston, Micron, and Western Digital. It also alleges that Defendants were aware of several of the patents-in-suit as early as July 2020 due to a standstill agreement between the parties, an allegation that may be significant for Plaintiff's willfulness claims.

Case Timeline

Date Event
2011-07-19 Earliest Priority Date for all Asserted Patents ('298, '385, '240, '300, '546, '054, '005)
2014-11-18 U.S. Patent No. 8,891,298 Issues
2015-11-24 U.S. Patent No. 9,196,385 Issues
2018-06-12 U.S. Patent No. 9,997,240 Issues
2020-07-08 Vervain and SK hynix execute a standstill agreement identifying the '298, '385, and '240 patents
2021-03-16 U.S. Patent No. 10,950,300 Issues
2023-11-28 U.S. Patent No. 11,830,546 Issues
2024-10-15 U.S. Patent No. 12,119,054 Issues
2025-02-11 U.S. Patent No. 12,224,005 Issues
2026-02-03 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,891,298

  • Patent Identification: U.S. Patent No. 8,891,298 ("Lifetime Mixed Level Non-Volatile Memory System"), issued November 18, 2014 (the "'298 Patent"). Compl. ¶29

The Invention Explained

  • Problem Addressed: The patent addresses the trade-off in non-volatile memory systems between single-level cell (SLC) memory, which is fast and durable but expensive, and multi-level cell (MLC) memory, which is denser and cheaper but has a shorter lifespan and slower performance Compl. ¶47 This creates a challenge for designing cost-effective, high-performance, and reliable storage devices like SSDs '298 Patent, col. 2:29-67
  • The Patented Solution: The invention describes a memory system with a controller that manages both MLC and SLC memory modules '298 Patent, abstract The controller is designed to perform a data integrity test after writing to the less-reliable MLC memory; if the test fails, it remaps that data to the more-reliable SLC memory '298 Patent, FIG. 3A-3B The controller also tracks block access frequency to identify "hot" data (frequently written) and allocates it to the high-endurance SLC module, thereby extending the overall life of the memory system '298 Patent, col. 6:24-65
  • Technical Importance: This hybrid management technique allows a storage system to achieve a balance of performance, cost, and longevity by strategically using small amounts of expensive, high-endurance memory for critical or failure-prone data Compl. ¶47

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 Compl. ¶58
  • Claim 1 of the '298 Patent recites a system comprising:
    • At least one MLC non-volatile memory module;
    • At least one SLC non-volatile memory module; and
    • A controller coupled to the modules and adapted to:
      • (a) maintain an address map for the MLC and SLC modules;
      • (b) determine if a range of addresses in the MLC module fails a data integrity test, and if so, remap the entry to the SLC module;
      • (c) determine which blocks are accessed most frequently by maintaining a count; and
      • (d) allocate blocks with the most frequent writes to the SLC module. Compl. ¶59
  • The complaint reserves the right to assert additional claims Compl. ¶58

U.S. Patent No. 9,196,385

  • Patent Identification: U.S. Patent No. 9,196,385 ("Lifetime Mixed Level Non-Volatile Memory System"), issued November 24, 2015 (the "'385 Patent"). Compl. ¶30

The Invention Explained

  • Problem Addressed: The patent addresses the same technical problem as the parent '298 Patent: managing the trade-off between MLC and SLC flash memory to optimize for cost, performance, and endurance Compl. ¶47
  • The Patented Solution: The solution is nearly identical to that of the '298 Patent but is described in the context of a "flash translation layer" (FTL) that performs the controller's logic '385 Patent, abstract The FTL maintains an address map, performs data integrity tests on MLC writes and remaps failed writes to SLC memory, and allocates frequently written data to the SLC module to extend the system's lifetime '385 Patent, col. 5:20-44
  • Technical Importance: As with the '298 Patent, this approach provides a method to create hybrid storage devices that balance the competing demands of cost, speed, and reliability in the market Compl. ¶47

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 Compl. ¶103
  • Claim 1 of the '385 Patent recites a system comprising:
    • At least one MLC non-volatile memory module;
    • At least one SLC non-volatile memory module; and
    • A flash translation layer (FTL) adapted to perform the same four functions as the controller in claim 1 of the '298 Patent: (a) maintaining an address map, (b) performing an integrity test and remapping on failure, (c) determining block access frequency via a count, and (d) allocating frequent writes to the SLC module. Compl. ¶104
  • The complaint reserves the right to assert additional claims Compl. ¶103

Multi-Patent Capsule: U.S. Patent No. 9,997,240

  • Patent Identification: U.S. Patent No. 9,997,240 ("Lifetime Mixed Level Non-Volatile Memory System"), issued June 12, 2018 (the "'240 Patent"). Compl. ¶31
  • Technology Synopsis: The '240 Patent continues the theme of the patent family, describing a controller that manages hybrid MLC/SLC memory. It adds the concepts of allocating frequent writes to SLC as "hot blocks" and infrequent writes to MLC as "cold blocks," and transferring the contents of blocks to SLC on a periodic basis when a "predetermined count value" is reached Compl. ¶121
  • Asserted Claims: At least claim 6 (independent system claim) Compl. ¶120
  • Accused Features: The complaint alleges that the Accused Products' controllers allocate frequently written blocks to SLC memory and move infrequently written data to MLC memory through processes like garbage collection Compl. ¶126

Multi-Patent Capsule: U.S. Patent No. 10,950,300

  • Patent Identification: U.S. Patent No. 10,950,300 ("Lifetime Mixed Level Non-Volatile Memory System"), issued March 16, 2021 (the "'300 Patent"). Compl. ¶32
  • Technology Synopsis: The '300 Patent describes a system where the controller performs a data integrity test by comparing data stored in an MLC element with a copy of that data retained in random access volatile memory (e.g., DRAM) after a write operation. A failure of this test results in remapping the data to a different physical address range to achieve enhanced endurance '300 Patent, abstract Compl. ¶137
  • Asserted Claims: At least claim 1 (independent system claim) Compl. ¶136
  • Accused Features: The complaint alleges the Accused Products' controllers perform data integrity tests by comparing data stored in flash with data retained in RAM Compl. ¶148 The complaint provides a diagram from Phison showing a "RAM Cache" used in conjunction with NAND flash as evidence Compl. ¶147 Compl. Ex. HHH, p. 69

Multi-Patent Capsule: U.S. Patent No. 11,830,546

  • Patent Identification: U.S. Patent No. 11,830,546 ("Lifetime Mixed Level Non-Volatile Memory System"), issued November 28, 2023 (the "'546 Patent"). Compl. ¶33
  • Technology Synopsis: The '546 Patent is substantially similar to the '300 Patent. It claims a system where a controller uses its own associated memory to retain a copy of data during a write to an MLC element, then performs an integrity test by comparing the data in its memory to the data written to the MLC element '546 Patent, abstract Compl. ¶162
  • Asserted Claims: At least claim 1 (independent system claim) Compl. ¶161
  • Accused Features: The allegations for the '546 Patent mirror those for the '300 Patent, focusing on the use of RAM to cache data during write operations to flash memory Compl. ¶169

Multi-Patent Capsule: U.S. Patent No. 12,119,054

  • Patent Identification: U.S. Patent No. 12,119,054 ("Lifetime Mixed Level Non-Volatile Memory System"), issued October 15, 2024 (the "'054 Patent"). Compl. ¶34
  • Technology Synopsis: The '054 Patent claims a system where a controller performs a data integrity test during a read operation. If the test fails on data read from an MLC element, the controller remaps the corresponding address entry to an available SLC element '054 Patent, abstract Compl. ¶181 This differs from prior family members that focus on integrity tests after a write.
  • Asserted Claims: At least claim 1 (independent system claim) Compl. ¶180
  • Accused Features: The complaint alleges that the controllers in the Accused Products perform data integrity tests and data refresh/remapping operations in response to data integrity problems, which can include moving data from MLC to SLC Compl. ¶186

Multi-Patent Capsule: U.S. Patent No. 12,224,005

  • Patent Identification: U.S. Patent No. 12,224,005 ("Lifetime Mixed Level Non-Volatile Memory System"), issued February 11, 2025 (the "'005 Patent"). Compl. ¶35
  • Technology Synopsis: The '005 Patent describes an apparatus where, if a first group of physical memory cells (e.g., MLC) fails a data integrity test, the controller writes the information to a second group of cells, writing only a single bit of information per cell (i.e., in SLC mode). The logical address range is then mapped to this second group '005 Patent, abstract Compl. ¶195
  • Asserted Claims: At least claim 1 (independent apparatus claim) Compl. ¶194
  • Accused Features: The complaint alleges the Accused Products' controllers write data to SLC in response to data integrity errors in MLC, citing features like SLC write buffers and SLC caching technology Compl. ¶199

III. The Accused Instrumentality

  • Product Identification: The "Accused Products" are a broad category of SK hynix and Solidigm flash memory products, including numerous solid-state drives (SSDs) such as the "SK hynix Silver S32," "SK hynix Gold P42," and "Solidigm P44 Pro," as well as embedded flash products like eMMC and UFS Compl. ¶¶10, 51-52
  • Functionality and Market Context:
    • The Accused Products are managed by controller chips, which include proprietary SK hynix/Solidigm designs (e.g., "Aries," "Cepheus") as well as third-party controllers from Phison and Silicon Motion Compl. ¶¶10, 51
    • The complaint alleges these products implement a hybrid memory architecture, using Multi-Level Cell (MLC, including TLC and QLC) memory for bulk storage and Single-Level Cell (SLC) memory as a high-performance cache or buffer Compl. ¶¶11, 61 This functionality is marketed with terms like "SLC Caching," "Direct-to-TLC," and "pseudo-SLC cache" to improve write speeds and endurance Compl. ¶¶61, 64 Compl. Ex. HH, Compl. ¶p. 21 A diagram from a Phison blog cited in the complaint illustrates this architecture, showing a "Host" writing data to an "SLC buffer" before an "Internal copy back" to "TLC mode" memory Compl. ¶61 Compl. Ex. EE, p. 19
    • The complaint positions SK as a "top tier semiconductor supplier" and the "second-largest DRAM and NAND supplier globally," with its products used by major electronics manufacturers like Apple, Dell, and Lenovo Compl. ¶¶9, 13

IV. Analysis of Infringement Allegations

'298 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A system for storing data comprising: at least one MLC non-volatile memory module...; at least one SLC non-volatile memory module... The Accused Products are flash storage systems (SSDs) that allegedly contain both MLC (e.g., TLC, QLC) and SLC memory, the latter often used as a "pseudo-SLC cache" or "SLC buffer." ¶¶60-64 col. 7:8-12
a controller coupled to the at least one MLC non-volatile memory module and the at least one SLC non-volatile memory module The Accused Products contain controllers (e.g., from Phison, Silicon Motion, or proprietary SK designs) that are coupled to and manage the MLC and SLC memory. ¶65 col. 7:13-15
a) maintain an address map of at least one of the MLC and SLC non-volatile memory modules... The controllers in the Accused Products allegedly use a mapping table, such as a logical-to-physical (L2P) table, to track the relationship between logical blocks and physical addresses in flash memory. A diagram from a Phison blog cited in the complaint shows an L2P table used to turn logical addresses into physical locations Compl. ¶67 Compl. Ex. KK, p. 23 ¶¶66-67 col. 7:16-25
b) determine if a range of addresses listed by an entry...fails a data integrity test, and, in the event of such a failure, the controller remaps the entry to the...SLC non-volatile memory module; The complaint alleges that the controllers use defect and error management technology, such as Phison's "SmartRefresh," to test for data integrity. Upon failure, it is alleged that the firmware remaps degraded data to the next available location, which may include moving data from MLC to SLC. ¶¶74-78 col. 7:26-33
c) determine which of the blocks...are accessed most frequently by maintaining a count of the number of times each one of the blocks is accessed; The controllers allegedly employ block counting, such as tracking program/erase counts or valid page counts, to determine which blocks are accessed most frequently. Phison controllers are alleged to use "erase count" data to select blocks. ¶¶83-85 col. 8:1-5
d) allocate those blocks that receive the most frequent writes by transferring the respective contents of those blocks to the at least one SLC non-volatile memory module. The complaint alleges that controllers move frequently accessed data to SLC NAND. For example, Phison's "double rotation" scheme and copyback schemes are alleged to move data to SLC blocks. A diagram from a Solidigm patent application cited in the complaint shows a process for caching "most frequently accessed data (hot data) in fast media (for example, SLC NAND)" Compl. ¶95 Compl. Ex. III, p. 46 ¶¶88-91; ¶95 col. 8:6-9

'385 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A system for storing data comprising... at least one MLC... at least one SLC... The Accused Products are flash storage systems containing both MLC and SLC memory, as described in Section III. ¶105; ¶106; ¶107 col. 7:13-17
a flash translation layer (FTL); wherein the FTL is adapted to: The Accused Products include an FTL, which is alleged to be the component that provides mapping between logical and physical addresses. A Phison marketing document is cited showing an image of a "NAND Flash Translation Layer" Compl. ¶108 Compl. Ex. SS, p. 51 ¶108 col. 7:18-19
a) maintain an address map... The FTL allegedly maintains an L2P table to map logical to physical addresses, as described for the '298 Patent. ¶109 col. 7:20-29
b) determine if a range of addresses...fails a data integrity test, and...remaps the entry to the...SLC non-volatile memory module; The FTL is alleged to incorporate data integrity functions and remap data to SLC memory upon failure of a data integrity test. ¶110 col. 7:30-37
c) determine which of the blocks...are accessed most frequently by maintaining a count...; and The FTL allegedly uses block counting mechanisms to identify frequently accessed blocks. ¶111 col. 7:38-42
d) allocate those blocks that receive the most frequent writes by transferring the respective contents...to the...SLC non-volatile memory module. The FTL allegedly allocates frequently written blocks to SLC and transfers their contents. ¶112 col. 8:1-4
  • Identified Points of Contention:
    • Technical Questions: A primary question for the court may be one of causation and effect. The patents require specific actions (e.g., remapping to SLC) to be triggered by specific events (e.g., a "data integrity test failure"). The complaint alleges the Accused Products perform data integrity checks and also remap data, but a potential point of dispute is whether the evidence shows that the specific failure of a data integrity test, as defined by the patent, is the direct trigger for the remapping to SLC, as opposed to other controller functions like wear-leveling or SLC write caching. For instance, the complaint points to a Solidigm patent application flowchart showing a "Write User Data to SLC" step after a "Readback Error" Compl. ¶82 Compl. Ex. AAA, p. 36, which may support the plaintiff's theory.
    • Scope Questions: The infringement case relies heavily on public documentation for third-party controllers (Phison, Silicon Motion) and on SK's/Solidigm's own patent applications, rather than direct analysis of the Accused Products' firmware. A key question will be whether the functionality described in these high-level or analogous documents is actually implemented in the specific Accused Products and whether that functionality meets the precise limitations of the asserted claims. For example, does "wear leveling" based on "erase counts" Compl. ¶84 Compl. Ex. UU, p. 39 constitute "maintain[ing] a count of the number of times each one of the blocks is accessed" for the purpose of identifying "most frequent writes" as required by claim 1 of the '298 patent?

V. Key Claim Terms for Construction

For U.S. Patent No. 8,891,298

  • The Term: "fails a data integrity test" (Claim 1)

  • Context and Importance: This phrase defines the specific trigger for remapping data from the MLC module to the more robust SLC module. Its construction is critical because it determines what type of error or condition constitutes an infringing event. A narrow definition could significantly limit the scope of infringement, while a broad one could cover a wider range of standard error-handling procedures in SSDs.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The complaint may argue that any error detection mechanism, such as those in Phison's "SmartRefresh" technology which monitors "Dynamic Error Bit Monitoring" Compl. ¶75 Compl. Ex. QQ, p. 28, constitutes a "data integrity test." The term itself is not explicitly defined in the patent, which may support an argument for its plain and ordinary meaning, potentially covering various error states.
    • Evidence for a Narrower Interpretation: The specification's detailed embodiment and flowcharts describe a specific sequence: data is written to NAND, read back into the controller, and then compared to the data retained in the controller's memory 298 Patent, FIG. 3A-3B, steps 110-116 The patent states, "if the retained data does not match the newly stored data...the method executes step 120" which begins the remapping process '298 Patent, col. 6:12-44 This suggests the "test" is a specific post-write, read-and-compare verification, not a general background scan for bit errors.

  • The Term: "maintaining a count of the number of times each one of the blocks is accessed" (Claim 1)

  • Context and Importance: This limitation defines the mechanism for identifying the "most frequently" accessed blocks that are candidates for allocation to the SLC module. Practitioners may focus on this term because the complaint alleges this is met by general wear-leveling techniques that use "program/erase counts" Compl. ¶¶84-85, and the dispute will center on whether such metrics are equivalent to a "count" of "accesses" as claimed.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The claim language is "maintaining a count," which could be argued to encompass any numerical metric that tracks usage, including erase cycles, as this is a proxy for how often a block has been accessed for writes.
    • Evidence for a Narrower Interpretation: The claim requires a count of "accesses," which could be interpreted more narrowly to mean each individual read or write operation, rather than the more coarse metric of erase cycles used for wear-leveling. The patent itself states the controller could "simply maintain a count of those blocks that are accessed (written to) most frequently" '298 Patent, col. 6:30-62, which could be read to imply a direct count of write accesses, distinct from an erase count which applies to the entire block after many writes.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges that Defendants induce infringement by selling the Accused Products to downstream computer manufacturers like Dell, Apple, and Lenovo, and providing them with "direction, instruction, documentation, and other information" that suggests using the products in an infringing manner Compl. ¶97 Compl. ¶115
  • Willful Infringement: The willfulness allegation is based on alleged pre-suit knowledge. The complaint asserts that SK hynix was aware of the '298, '385, and '240 patents "as early as July 8, 2020, when Vervain and SK executed a standstill agreement specifically identifying" these patents Compl. ¶99 The continuation of allegedly infringing activities after this date is cited as evidence of willful, wanton, and deliberate infringement Compl. ¶99

VII. Analyst's Conclusion: Key Questions for the Case

  • A central issue will be one of evidentiary proof and technical operation: Does the evidence, largely drawn from marketing materials and patent applications, demonstrate that the accused third-party and proprietary controllers perform the specific, ordered steps required by the claims? In particular, does remapping data to the SLC module occur because a specific data integrity test failed, or is it part of a more general SLC caching or wear-leveling algorithm that operates independently of such a test?
  • A second key issue will be one of claim scope and definition: How will the court construe the term "fails a data integrity test"? Will it be interpreted broadly to cover any error-correction or data-refresh mechanism that detects bit errors, as suggested by Plaintiff's allegations regarding "SmartRefresh" and "IntelligentScan," or will it be limited to the specific post-write, read-and-compare verification process detailed in the patents' embodiments?
  • Finally, a critical question for damages will be one of willfulness: Given the complaint's specific allegation of a 2020 standstill agreement that identified several of the patents-in-suit, the court will need to determine if Defendants' conduct after that date constituted an objectively high and knowing risk of infringement, which could expose them to enhanced damages.
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