DCT

1:25-cv-01623

ThroughPuter Inc v. Amazon Web Services Inc

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Amended Complaint
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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-01623, W.D. Tex., 09/09/2026
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant has a regular and established place of business in the district, including an office in Austin, and has committed the alleged acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s AWS Nitro System, including its Nitro Cards, infringes five U.S. patents related to parallel computing architectures, resource management, and task switching in multi-core processor environments.
  • Technical Context: The technology concerns methods for efficiently managing shared hardware resources in multi-core and cloud computing systems to simultaneously increase processing speed for individual applications and optimize overall system utilization.
  • Key Procedural History: The complaint notes that the patented technology was developed starting in 2010 and was presented by the inventor at industry conferences beginning in 2012. It also states that Defendant AWS acquired Annapurna Labs, a microelectronics company involved in designing the accused Nitro hardware, in 2015.

Case Timeline

Date Event
2010-01-01 Approximate start of technology development mentioned in complaint
2011-09-27 Priority Date for U.S. Patent No. 8,561,078
2011-11-04 Priority Date for U.S. Patent No. 8,789,065
2011-11-04 Priority Date for U.S. Patent No. 10,133,599
2011-11-04 Priority Date for U.S. Patent No. 10,310,902
2011-11-04 Priority Date for U.S. Patent No. 10,318,353
2012-01-01 Inventor began speaking at high performance and cloud computing conferences
2013-10-15 Issue Date for U.S. Patent No. 8,561,078
2014-07-22 Issue Date for U.S. Patent No. 8,789,065
2015-01-01 AWS acquired Annapurna Labs
2018-11-20 Issue Date for U.S. Patent No. 10,133,599
2019-06-04 Issue Date for U.S. Patent No. 10,310,902
2019-06-11 Issue Date for U.S. Patent No. 10,318,353
2024-02-08 Inter Partes Review Certificate issued for U.S. Patent No. 10,318,353
2026-09-09 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,561,078 - "Task Switching and Inter-Task Communications for Multi-Core Processors"

The Invention Explained

  • Problem Addressed: The patent's background describes the challenge of dynamically updating processing tasks on a multi-core processor to achieve high throughput without significant overhead from the operating system U.S. 8,561,078, col. 1:29-53 The complaint frames this as a tension between maximizing single-application speed and maximizing multi-application resource utilization Compl. ¶¶20-22
  • The Patented Solution: The invention proposes a hardware-based solution for managing tasks on a multi-core processor. It uses a "hardware logic based controller" to repeatedly assign tasks to specific cores and a "cross-connect" to transfer task memory images between the cores and task-specific memory segments U.S. 8,561,078, abstract This hardware-automated approach is designed to minimize the need for a software-based operating system to manage these functions, thereby reducing overhead and increasing efficiency U.S. 8,561,078, col. 2:3-23
  • Technical Importance: This approach aimed to make cloud computing more economically feasible for performance-intensive applications by enabling both accelerated processing speeds and optimized resource utilization in a shared hardware environment Compl. ¶¶27-28

Key Claims at a Glance

  • The complaint asserts infringement of at least Claim 1 of the ’078 Patent Compl. ¶49
  • The essential elements of independent Claim 1 are:
    • A data processing system comprising: an array of processing cores, a hardware logic controller, a memory with task-specific segments, and a hardware logic cross-connect.
    • The controller repeatedly assigns individual processing cores to process individual tasks of software programs.
    • The cross-connect connects the array of processing cores and the task-specific memory segments.
    • The controller configures the cross-connect to use either a task-specific multiplexer to connect a core to a memory segment for the same task, or a core-specific multiplexer to connect a memory segment to a specific core Compl. ¶50
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent but makes a general reservation for all asserted patents Compl. ¶84 Compl. ¶95

U.S. Patent No. 8,789,065 - "System and Method for Input Data Load Adaptive Parallel Processing"

The Invention Explained

  • Problem Addressed: As with the '078 patent, this patent addresses the need for a new parallel computing architecture that can simultaneously increase the speed of individual applications and improve the utilization of shared computing resources U.S. 8,789,065, col. 2:25-40
  • The Patented Solution: The invention describes a system for "input data load adaptive processing" on a manycore processor shared by multiple software programs U.S. 8,789,065, abstract The system uses logic subsystems to dynamically manage data flow by demultiplexing incoming data packets to program-specific hardware buffers based on overhead information in the packet, monitoring the volume of data in those buffers, and assigning processing cores based on that monitored volume U.S. 8,789,065, col. 4:45-61
  • Technical Importance: This load-adaptive approach allows processing resources to be allocated dynamically based on real-time data flow, improving efficiency in environments with unpredictable workloads Compl. ¶105

Key Claims at a Glance

  • The complaint asserts infringement of at least Claim 1 of the ’065 Patent Compl. ¶100
  • The essential elements of independent Claim 1 are:
    • A system for input data load adaptive processing, comprising: a collection of shared hardware input data ports, an array of program-instance-specific hardware buffers, and several logic subsystems.
    • A logic subsystem for demultiplexing input data packets from the ports to the specific buffers based on a "destination program instance indication" in the packet's overhead.
    • A logic subsystem for monitoring data volumes at the buffers and periodically assigning processing cores to program instances based on the monitored volumes.
    • A logic subsystem for multiplexing data packets from the buffers to the assigned processor cores Compl. ¶101
  • The complaint makes a general reservation of rights to assert additional claims Compl. ¶137

U.S. Patent No. 10,318,353 - "Concurrent Program Execution Optimization"

  • Technology Synopsis: The patent describes a system for optimizing the execution of concurrent programs by organizing tasks into a plurality of processing stages U.S. 10,318,353, abstract It uses multiplexers to manage inter-task communication (ITC) data between these stages, with at least one multiplexer being a dedicated hardware resource for a local task, and assigns tasks to cores for a specific period of time U.S. 10,318,353, col. 2:29-45 This creates a pipelined processing architecture. An Inter Partes Review Certificate was issued on February 8, 2024, cancelling claims 1 and 2 but finding claims 8-14 and 21-24 patentable (U.S. 10318353 K1).
  • Asserted Claims: Claim 3 (dependent on cancelled Claim 1) Compl. ¶154
  • Accused Features: The complaint alleges the Nitro Cards' sequential, pipeline operations for packet processing constitute the claimed "plurality of processing stages" Compl. ¶159 The passing of data between these stages is alleged to be the "inter-task communications," managed by the mesh network's multiplexers Compl. ¶¶165-166

U.S. Patent No. 10,133,599 - "Application Load Adaptive Multi-stage Parallel Data Processing Architecture"

  • Technology Synopsis: The patent discloses a system for dynamic resource management of a pool of processing resources U.S. 10,133,599, abstract It uses a first subsystem to periodically allocate processing units among application programs based on demand and quotas. A second subsystem selects the highest priority instances of each program, and a third subsystem assigns these instances to the allocated processing units, prioritizing placement based on the type of processing unit demanded U.S. 10,133,599, col. 27:35-30:2
  • Asserted Claims: Claim 1 Compl. ¶210
  • Accused Features: The complaint maps the live-updating of firmware on the Nitro Cards to the "first subsystem" that allocates resources Compl. ¶216 The enforcement of packet-per-second allowances is mapped to the "second subsystem" that selects high-priority instances Compl. ¶219 The hardware that directs packet flows to different processing unit types (Arm cores vs. ASICs) is mapped to the "third subsystem" Compl. ¶¶223-225

U.S. Patent No. 10,310,902 - "System and Method for Input Data Load Adaptive Parallel Processing"

  • Technology Synopsis: This patent describes a system for hosting application programs that uses subsystems to manage core allocation and data access U.S. 10,310,902, abstract A first subsystem allocates cores based on data volume in input buffers and quotas. A second subsystem assigns cores to different program instances based on data availability. A third subsystem establishes "direct data access" from the input buffers to the assigned cores U.S. 10,310,902, col. 2:1-40
  • Asserted Claims: Claim 1 Compl. ¶263
  • Accused Features: The live updating of firmware is alleged to be the "first subsystem" allocating cores Compl. ¶270 The hashing hardware that routes packets to buffers for processing by specific cores is alleged to be the "second subsystem" Compl. ¶272 The mesh network (CMN) that provides physical connections from buffers to cores is alleged to be the "third subsystem" establishing direct data access Compl. ¶279

III. The Accused Instrumentality

Product Identification

  • The accused products are the AWS Nitro System and its components, including the "Nitro Cards," such as the Nitro Card for VPC, the Nitro Card for EBS, and the Nitro Card for Local NVMe Storage Compl. ¶¶34, 37

Functionality and Market Context

  • The complaint alleges the AWS Nitro System is a foundational technology for Amazon's EC2 service, designed to offload networking, storage, and security functions from the main server CPU to dedicated hardware cards Compl. ¶17 Compl. ¶37 These Nitro Cards are described as systems-on-a-chip (SoCs) containing an array of "Nitro cores" (identified as Arm cores) and specialized ASICs Compl. ¶37 Compl. ¶39 Compl. ¶42 The cores are allegedly arranged in a mesh network (e.g., Arm CMN-600) and perform pipelined data packet processing, handling tasks like firewall evaluation, network address translation (NAT), and load balancing Compl. ¶41 Compl. ¶42 Data packets are received from the host via a PCIe interface or the network via an Ethernet interface and are routed to specific cores for processing based on flow characteristics Compl. ¶38 Figure 3-1 on page 20 depicts a single crosspoint (XP), described as a hardware switch or router logic module that connects devices like memory and cores Compl. ¶63

IV. Analysis of Infringement Allegations

8,561,078 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A data processing system comprising: an array of processing cores for processing a set of software programs... The accused Nitro Card is a data processing system with an array of "Nitro cores" (Arm cores) that process data packets according to software programs that define the tasks to be performed. ¶51; ¶53; ¶54 col. 4:18-29
a hardware logic module, referred to as a controller, for repeatedly assigning individual processing cores...to process individual tasks... Specialized hardware on the Nitro Card processes packet headers and directs packets to flow-specific buffers, which are polled by Nitro cores. This assignment is alleged to be "repeatedly" occurring as new packet flows initiate and old ones terminate. ¶55; ¶56 col. 4:30-36
a memory providing task-specific memory segments; The shared system-level cache on the Nitro Card is segmented into input buffers (queues), with each buffer allegedly being specific to a particular processing task required for a given packet flow. ¶57; ¶58 col. 4:37-39
a hardware logic module, referred to as a cross-connect, for connecting the array of processing cores and the task-specific memory segments...wherein the controller configures at least one of the following: (a) at least one given task-specific multiplexer... or (b) at least one given core-specific multiplexer... The Arm core mesh network (e.g., CMN-600) on the Nitro Card is alleged to be the cross-connect. Its crosspoints (XPs) are alleged to be multiplexers that connect task-specific memory segments (input buffers) to specific cores, configured by the controller hardware. ¶59; ¶60; ¶62; ¶67 col. 4:40-66

8,789,065 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A system for input data load adaptive processing...comprising: a collection of hardware input data ports...where each port...is shared dynamically among data packets... The accused Nitro Card is a system that performs load adaptive processing. Its PCIe and Ethernet interfaces are the hardware input ports, which receive continuous streams of data packets. ¶102; ¶105; ¶107; ¶108 col. 4:45-53
an array of hardware buffers, where each buffer of the array is specific to an individual destination program instance... The Nitro Card's shared system-level cache is segmented into input buffers (queues). Each queue is alleged to be specific to a packet flow and its corresponding processing program (program instance). ¶109; ¶110 col. 4:54-57
a logic subsystem for dynamically, at individual packet granularity, demultiplexing input data packets from said input ports to said destination program instance specific buffers based on a destination program instance indication...by overhead information... Specialized packet processing hardware on the Nitro Card executes a "five tuple hash" on the packet header (overhead information) to dynamically distribute individual packets to flow-specific input buffers. ¶112; ¶113 col. 4:45-53
a logic subsystem for monitoring volumes of data packets at the program instance specific buffers and for periodically assigning processing cores...based on the respective monitored volumes... Controller hardware associated with each Nitro core repeatedly polls the input buffers (monitoring volumes) and assigns cores to handle the packet flow. The assignment is based in part on congestion control and fair queuing algorithms. ¶114; ¶115 col. 4:58-61
a logic subsystem for multiplexing data packets dynamically from the destination program instance specific buffers to the processor cores... The mesh network on the Nitro Card provides multiplexed connections from the input buffers to the assigned Nitro processor cores, managed by the Nitro Card's control hardware. ¶116; ¶117; ¶118 col. 4:62-68
  • Identified Points of Contention:
    • Scope Questions: A central issue may be whether the general-purpose components of the accused AWS Nitro System, such as the Arm CMN-600 mesh network and its associated crosspoint (XP) switches, meet the specific definitions of the claimed "controller," "cross-connect," and "logic subsystems." For instance, for the '078 Patent, the analysis raises the question of whether an industry-standard mesh interconnect performs the specific function of the claimed "cross-connect" configured by a "controller" to connect specific cores to specific memory segments, or if it is simply a general data fabric.
    • Technical Questions: The complaint's theory of infringement often relies on mapping claimed functions to the natural operation of a packet-processing system. For the '078 patent, the allegation of "repeatedly assigning" cores is supported by the fact that packet flows begin and end over time Compl. ¶56 This raises the evidentiary question of whether this passive turnover of work constitutes the active "assigning" function required by the claim, which may imply a more deliberate scheduling and resource allocation role for the "controller."

V. Key Claim Terms for Construction

U.S. Patent No. 8,561,078

  • The Term: "hardware logic module, referred to as a controller"
  • Context and Importance: This term is critical because its definition determines what entity must perform the "repeatedly assigning" of cores. The complaint identifies this as "Specialized hardware...on the accused Nitro Card [that] processes the 5-tuple data packet headers and directs data packets to flow-specific buffers" Compl. ¶56 The case may turn on whether this packet-routing function constitutes "assigning...cores" or if the claim requires a higher-level resource scheduler.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the controller in functional terms, such as being responsible for "repeatedly i) allocating cores... and ii) according to such allocating, assigning tasks... for processing by the cores" U.S. 8,561,078, col. 2:5-11, which might support an interpretation covering any hardware that directs work to cores.
    • Evidence for a Narrower Interpretation: The patent's abstract describes the controller as managing "task memory images," and the detailed description discusses its role in a "task switchover" U.S. 8,561,078, abstract U.S. 8,561,078, col. 4:29-34 This context could support a narrower interpretation where the controller is not just a packet router but a stateful manager of task execution contexts.

U.S. Patent No. 8,789,065

  • The Term: "logic subsystem for monitoring volumes of data packets"
  • Context and Importance: The infringement allegation for this element hinges on the idea that controller hardware "sequentially and repeatedly poll[s]" input buffers Compl. ¶115 Practitioners may focus on whether "polling" a buffer to see if it contains data is equivalent to "monitoring volumes."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent states that core allocation is based "at least in part based on the respective monitored volumes of packets" U.S. 8,789,065, Claim 1 This "at least in part" language may allow for a broad definition of monitoring, where even a simple check for data presence qualifies.
    • Evidence for a Narrower Interpretation: The term "volumes" suggests a quantitative measurement beyond a binary empty/not-empty status determined by polling. The specification discusses equalizing "aggregate task processing load" U.S. 8,789,065, col. 4:3-5, which may imply a more sophisticated volume measurement is required to achieve such load balancing.

VI. Other Allegations

  • Indirect Infringement: Plaintiff alleges that Defendant induces infringement of all asserted patents. The allegations state that Defendant instructs and encourages customers and developers to use the accused AWS Nitro System in an infringing manner through materials such as "development kits, development Amazon Machine Images, tutorials, presentations, webinars, guidelines, videos, manuals, [and] white papers" Compl. ¶88 Compl. ¶141 Compl. ¶198 Compl. ¶251 Compl. ¶303
  • Willful Infringement: For all asserted patents, Plaintiff alleges willful infringement based on Defendant having "actual notice and knowledge" of the patents "by no later than the filing of this Complaint" Compl. ¶74 Compl. ¶128 Compl. ¶184 Compl. ¶237 Compl. ¶289 The complaint also pleads willful blindness Compl. ¶76

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can standard data center hardware components, such as Arm's Coherent Mesh Network (CMN) and its associated crosspoint switches, be construed to meet the specific claim terms like "hardware logic module, referred to as a controller" and "cross-connect"? The case may depend on whether the patents describe and claim a novel, purpose-built architecture or a new way of using existing, general-purpose interconnects.
  • A key evidentiary question will be one of functional operation: does the accused system's alleged activity—such as routing packets based on 5-tuple hashes or observing the natural turnover of network flows—perform the specific, active functions required by the claims, such as a controller "repeatedly assigning" cores or a logic subsystem "monitoring volumes of data"? The dispute may center on whether the accused system's inherent operational characteristics are sufficient to meet limitations that imply a more deliberate, managed scheduling and allocation process.
  • A third question relates to claim validity in light of subsequent review: for U.S. Patent 10,318,353, where the asserted independent claim was cancelled during an Inter Partes Review, the court will have to address the viability of the infringement claim, which is now asserted under a dependent claim. This raises immediate questions about whether the accused system includes the additional limitations of the surviving dependent claim and the overall strength of an assertion based on a narrowed patent.