Mila US Inc v. NVIDIA Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Case Name: Mila US Inc v. Nvidia Corporation
  • Plaintiff: Mila US Inc (Texas)
  • Defendant: Nvidia Corporation (Delaware)
  • Plaintiff's Counsel: BC LAW GROUP, P.C.
• Case Identification: 1:25-cv-01359, W.D. Tex., 09/25/2025
• Venue Allegations: Plaintiff alleges venue is proper because Nvidia is registered to do business in Texas, has regular and established places of business in the Western District of Texas, has transacted business in the district, and has committed the alleged acts of infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant's Graphics Processing Units (GPUs) and System-on-Chip (SoC) products infringe six U.S. patents related to image processing, data processor memory interfaces, sequencer control, and system-level error correction.
• Technical Context: The asserted patents relate to fundamental technologies in GPU and SoC architecture, including methods for efficient image composition, data broadcasting between processing units, task scheduling, and boot-up reliability, all of which are critical for high-performance and mobile computing.
• Key Procedural History: The complaint alleges that Plaintiff provided Defendant with notice of infringement via letters dated December 3, 2024, and March 13, 2025. It further alleges that for one of the patents-in-suit, U.S. Patent No. 8,275,975, Nvidia had notice as of at least June 20, 2014, through a Non-Final Rejection issued by the U.S. Patent and Trademark Office against an unrelated Nvidia patent application.

Case Timeline

Date	Event
2005-04-29	Earliest Priority Date (U.S. 7,924,296, U.S. 7,805,578, U.S. 7,757,048 Patents)
2005-12-09	Priority Date (U.S. 8,151,136 Patent)
2007-12-28	Priority Date (U.S. 7,966,436 Patent)
2008-01-25	Priority Date (U.S. 8,275,975 Patent)
2010-07-13	Issue Date (U.S. 7,757,048)
2010-09-28	Issue Date (U.S. 7,805,578)
2011-04-12	Issue Date (U.S. 7,924,296)
2011-06-21	Issue Date (U.S. 7,966,436)
2012-04-03	Issue Date (U.S. 8,151,136)
2012-09-25	Issue Date (U.S. 8,275,975)
2014-06-20	Alleged notice of U.S. 8,275,975 to Nvidia via USPTO Office Action
2024-12-03	Plaintiff's first notice letter to Nvidia
2025-03-13	Plaintiff's second notice letter to Nvidia
2025-04-15	Nvidia's response letter to Plaintiff
2025-09-25	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,924,296 - "System and method for DMA controlled image processing," Issued April 12, 2011

The Invention Explained

• Problem Addressed: The patent's background describes the challenge of performing complex image blending (e.g., alpha blending of two images) on systems with limited resources, such as mobile devices. It notes that using a traditional display storage frame buffer for such operations can be costly, consume significant power, and lack flexibility for handling images of different resolutions and color spaces. '296 Patent, col. 1:21-42
• The Patented Solution: The invention proposes a system that processes images "on the fly" without a full frame buffer. It uses a Direct Memory Access (DMA) fetching module to retrieve portions, or "tiles," of multiple source images from memory. '296 Patent, abstract A DMA master, configured by descriptors, controls the fetching order, allowing the system to blend these tiles to create a combined final image for display, thereby reducing memory requirements and power consumption. '296 Patent, col. 2:56-67
• Technical Importance: This tile-based DMA approach was significant for enabling sophisticated, layered graphics on power- and memory-constrained devices by avoiding the need to store and process entire image frames at once.

Key Claims at a Glance

• The complaint asserts independent claim 21. Compl. ¶10
• The essential elements of claim 21 are:
  • A method for processing image data from a plurality of images.
  • transferring each of a plurality of images to one of a plurality of DMA channels.
  • fetching a plurality of image tiles of pixel data in a certain fetching order by utilizing each of the plurality of DMA channels.
  • blending the fetched plurality of image tiles to generate a combined image.
  • wherein the plurality of images are of different resolution, orientation, and/or color space.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 7,805,578 - "Data processor apparatus and memory interface," Issued September 28, 2010

The Invention Explained

• Problem Addressed: The patent identifies inefficiencies in parallel processing architectures that use a dedicated "broadcast bus" to send the same data to multiple processor units. These buses can create routing congestion on the chip or, if simplified (e.g., bit-serial), can be slow. An alternative-storing the data locally in each processor unit-is described as wasting memory. '578 Patent, col. 1:59 - col. 2:19
• The Patented Solution: The invention proposes an apparatus that eliminates the dedicated broadcast bus by reusing the existing memory bus. An array controller transmits "broadcast data" intended for multiple processor units to a shared memory. The controller then directs the individual processor units to read that data from the memory. '578 Patent, abstract '578 Patent, col. 2:27-34 This design aims to reduce chip area and routing complexity.
• Technical Importance: This architectural approach offered a way to improve the scalability and efficiency of System-on-Chip (SoC) designs by reducing the need for dedicated, wide broadcast buses, a significant concern in increasingly complex multi-processor systems.

Key Claims at a Glance

• The complaint asserts independent claim 1. Compl. ¶21
• The essential elements of claim 1 are:
  • An apparatus comprising a plurality of memories and a plurality of processing units respectively coupled to them.
  • An interface coupled to the memories by a plurality of buses (at least one being a data bus).
  • The interface is configured to control access to the memories using an identifier to identify memory locations.
  • An array controller coupled to the processing units by a control bus for sending instructions and commands.
  • The array controller is configured to provide broadcast data to a memory location via the interface and data bus.
  • The controller then controls the corresponding processing unit to receive the broadcast data from that memory location.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

Multi-Patent Capsule: U.S. Patent No. 7,757,048

• Patent Identification: U.S. Patent No. 7,757,048, "Data processor apparatus and memory interface," Issued July 13, 2010. Compl. ¶30
• Technology Synopsis: This patent, related to the '578 patent, describes a data processor apparatus that avoids a dedicated broadcast bus. A controller sends data intended for multiple processor units to a shared memory and then directs the processor units to retrieve that data from memory, thereby reducing chip complexity and routing congestion. '048 Patent, abstract
• Asserted Claims: The complaint asserts independent claim 1. Compl. ¶32
• Accused Features: The complaint accuses Nvidia's "Tensor Core" GPU architectures (e.g., Hopper, Blackwell) and combined CPU-GPU products (e.g., Grace Hopper) of infringement. Compl. ¶31

Multi-Patent Capsule: U.S. Patent No. 8,275,975

• Patent Identification: U.S. Patent No. 8,275,975, "Sequencer controlled system and method for controlling timing of operations of functional units," Issued September 25, 2012. Compl. ¶41
• Technology Synopsis: The patent describes a sequencer-controlled system for managing operations on an SoC. A dedicated sequencer, not the main processor, uses registers and status information (e.g., resource availability) to trigger operations across various hardware units based on a pre-programmed waiting pattern, aiming to offload the main processor from intermediate status monitoring. '975 Patent, abstract
• Asserted Claims: The complaint asserts independent claim 1. Compl. ¶43
• Accused Features: The complaint accuses Nvidia products supporting "Multi-Instance GPU" (MIG) technology, such as the A100, H100, and Blackwell series GPUs. Compl. ¶42

Multi-Patent Capsule: U.S. Patent No. 7,966,436

• Patent Identification: U.S. Patent No. 7,966,436, "Data transmitter having high and low speed transmission units," Issued June 21, 2011. Compl. ¶53
• Technology Synopsis: The patent discloses a data transmitter that uses separate modes for different data types. It proposes a high-speed, unidirectional mode for transmitting primary data (e.g., image data) and a low-speed, bidirectional mode for secondary data (e.g., control and feedback data), optimizing power and efficiency for interfaces like MIPI DSI. '436 Patent, abstract
• Asserted Claims: The complaint asserts independent claim 1. Compl. ¶55
• Accused Features: The complaint accuses Nvidia products that incorporate a Display Serial Interface (DSI), including the Tegra X1, Jetson TX1, Jetson TX2, and Jetson Nano products. Compl. ¶54

Multi-Patent Capsule: U.S. Patent No. 8,151,136

• Patent Identification: U.S. Patent No. 8,151,136, "Method and device for correcting code data error," Issued April 3, 2012. Compl. ¶64
• Technology Synopsis: The invention describes a method and device for robustly booting a digital processor. It involves a nonvolatile memory with a primary code data area and a backup area. If an error is found in the primary code data during boot, the system uses an error-corrected version or the data from the backup area to continue the boot process, thereby improving system reliability. '136 Patent, abstract
• Asserted Claims: The complaint asserts independent claim 1. Compl. ¶66
• Accused Features: The complaint accuses Nvidia's Jetson AGX Orin Series System-on-Module, which includes an Orin Series SoC and features a redundant "A/B Slot Layout" for its bootloader. Compl. ¶65 Compl. ¶68

III. The Accused Instrumentality

Product Identification

• The complaint accuses two broad categories of Nvidia products.
  • For the U.S. Patent No. 7,924,296: Mobile processors and GPUs with "Multi-Plane Overlay" (MPO) functionality, including Pascal, Turing, Ampere, and Ada architecture GPUs (e.g., GTX 10 series, RTX 20/30/40 series, Quadro, Tegra). Compl. ¶9
  • For U.S. Patent Nos. 7,805,578, 7,757,048, 8,275,975, 7,966,436, and 8,151,136: A range of SoCs and GPUs, including those with "Tensor Core" (Hopper, Blackwell), "Multi-Instance GPU" (MIG), "DSI interface" (Tegra, Jetson), and "A/B boot" (Jetson AGX Orin) functionality. Compl. ¶20 Compl. ¶42 Compl. ¶54 Compl. ¶65

Functionality and Market Context

• The accused products are central to Nvidia's business in high-performance computing, AI, and graphics. The complaint alleges that features like MPO, MIG, and the Tensor Memory Accelerator (TMA) are marketed by Nvidia as providing significant performance and efficiency benefits. Compl. ¶12 Compl. ¶23 Compl. ¶46
• The MPO functionality is alleged to allow the hardware to compose multiple image layers (e.g., video, UI, desktop) into a single frame for display. Compl. Ex. 2, p. 3 A diagram in the complaint shows how different window inputs are processed and blended by the display controller. (Compl. Ex. 2, p. 7, Figure 83: Display Controller Front End Block Diagram).
• The accused Hopper and Blackwell GPUs are alleged to use technologies like the GigaThread scheduler to manage thread blocks across Streaming Multiprocessors (SMs) and a Tensor Memory Accelerator (TMA) to move data between global and shared memory. Compl. ¶23 Compl. Ex. 10, pp. 29-30 The complaint includes a diagram illustrating the "A/B Slot Layout" in the accused Jetson products, which provides boot redundancy. Compl. Ex. 27, p. 10

IV. Analysis of Infringement Allegations

U.S. Patent No. 7,924,296 Infringement Allegations

Claim Element (from Independent Claim 21)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A method for processing image data from a plurality of images	The Accused Products support Multi-Plane Overlay (MPO), which allows the hardware to compose multiple layers of content, such as a video, the desktop, and application windows (a "plurality of images"), into a single image.	¶10; Ex. 2, p. 2	col. 1:21-26
transferring each of a plurality of images to one of a plurality of DMA channels	The Accused Products' Display Controllers contain multiple full-function display windows (e.g., A, B, C) and additional windows (D, T), each served by a dedicated memory fetch engine ("memfetch") that functions as a DMA channel.	¶10; Ex. 2, p. 5	col. 2:56-62
fetching a plurality of image tiles of pixel data in a certain fetching order by utilizing each of the plurality of DMA channels	The memfetch request engine is alleged to fetch window images from memory by translating coordinates to a memory address and steering data to a line buffer, with the ability to scan column by column for rotation, constituting a "certain fetching order."	¶10; Ex. 2, pp. 13-16	col. 4:26-33
blending the fetched plurality of image tiles to generate a combined image	The Tegra X1 display blender is alleged to have six sequential blending stages where windows are sorted by depth, and each stage combines its pixels with the previous stage to generate a final, blended output.	¶10; Ex. 2, p. 19	col. 4:34-37
wherein the plurality of images are of different resolution, orientation, and/or color space	The Accused Products are alleged to support different resolutions via scaling, different orientations via a rotation feature in the memfetch unit, and different color spaces via a Color Space Converter.	¶10; Ex. 2, pp. 21-22	col. 1:24-26

Identified Points of Contention (U.S. Patent No. 7,924,296):

• Scope Question: A potential dispute may arise over whether the "plurality of images" recited in the claim reads on the "multiple layers" or "planes of content" (e.g., UI, video, desktop) that are combined by the accused MPO functionality. The defense could argue that "layers" of a single graphical scene are not a "plurality of images" as contemplated by the patent.
• Technical Question: The infringement theory relies on mapping each display "window" to an "image" and each "memfetch engine" to a "DMA channel." A central question will be whether the technical operation of Nvidia's display pipeline, which processes data for different windows, is structurally and functionally equivalent to the patent's disclosure of fetching "tiles" from distinct source images.

U.S. Patent No. 7,805,578 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
An apparatus comprising: a plurality of memories; a plurality of processing units respectively coupled to said plurality of memories	The Accused Products are alleged to be GPUs (e.g., H100) containing multiple Streaming Multiprocessors (SMs) as "processing units" and a memory hierarchy including L1/L2 cache and HBM as a "plurality of memories."	¶21; Ex. 10, pp. 5, 22	col. 5:3-13
an interface coupled to said plurality of memories by a plurality of buses... configured to control access to said plurality of memories using an identifier	The "interface" is alleged to be the Distributed Shared Memory (DSMEM) system and SM-to-SM network, which connects the shared memories of the SMs. Access is controlled using memory addresses as "identifiers" within a global address space.	¶21; Ex. 10, pp. 30-32	col. 5:14-25
an array controller coupled to said plurality of processing units by a control bus for sending at least one of instructions and commands	The "array controller" is alleged to be the GigaThread Engine/thread scheduler, which sends instructions and commands to the SMs ("processing units") to schedule and execute thread blocks.	¶21; Ex. 10, pp. 40-42	col. 5:26-32
said array controller configured to provide broadcast data to at least said memory location via said interface and said at least one data bus by first providing said broadcast data to said interface via said broadcast bus	The complaint alleges this is met by features like the Tensor Memory Accelerator (TMA) initiating asynchronous data copies from global memory to the shared memory of multiple blocks (a multicast), which functions as providing "broadcast data."	¶21; Ex. 10, pp. 47, 53	col. 6:3-13
and control... at least one of said plurality of processing units that corresponds to said memory location to receive said broadcast data from said memory location	The GigaThread scheduler is alleged to control the SMs to execute instructions that then access the data previously copied into shared memory by the TMA, thereby receiving the "broadcast data" from memory.	¶21; Ex. 10, pp. 48-49	col. 6:14-18

Identified Points of Contention (U.S. Patent No. 7,805,578):

• Scope Question: A core issue will be whether the patent's concept of an "array controller" using the main "memory" to "broadcast" data can be mapped onto a modern GPU architecture. The defense may argue that features like the GigaThread scheduler and TMA perform fundamentally different functions than the claimed system, which was designed to replace a simple, physical broadcast bus.
• Technical Question: The infringement allegation equates an asynchronous multicast copy to shared memory (via TMA) with the patent's "broadcast data" concept. It raises the question of whether a targeted, asynchronous copy operation initiated for a specific cluster of thread blocks is functionally equivalent to the patent's disclosure of an array controller broadcasting data intended for multiple processor units.

V. Key Claim Terms for Construction

U.S. Patent No. 7,924,296: "image tiles" (Claim 21)

• Context and Importance: This term is central to the infringement allegation. The patent describes fetching "tiles" of source images. The complaint maps this to the data fetched for entire display "windows" (e.g., an application window, a video). The construction of "image tiles" will determine if fetching data for a complete, distinct graphical source like a window falls within the scope of fetching a "tile," which may imply a subdivision of a larger, single image.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent abstract describes fetching "a portion of the source images (tiling)," which suggests "tile" is simply a portion of an image, without limiting its size or nature. '296 Patent, abstract
  • Evidence for a Narrower Interpretation: The specification discusses fetching tiles in a "certain fetching order," which in the context of graphics often refers to raster-scan or other systematic ways of processing a single frame. This might support an argument that a "tile" is a geometrically defined subdivision of an image, not a functionally distinct object like a window.

U.S. Patent No. 7,805,578: "broadcast data" (Claim 1)

• Context and Importance: The patent's stated purpose is to eliminate a dedicated "broadcast bus." The meaning of "broadcast data" is therefore critical. The complaint alleges that data copied to the shared memory of multiple processor units (a "multicast") meets this limitation. The case may hinge on whether "broadcast data" requires a one-to-all or one-to-many transmission from a central controller, or if it can cover data made available in a shared resource for multiple units to access.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent summary describes the invention as transmitting "data intended for each processor unit" to memory for later retrieval. '578 Patent, col. 2:35-39 This broad language could support an interpretation that includes any data made available to multiple units.
  • Evidence for a Narrower Interpretation: The background contrasts the invention with a "broadcast bus... where all the devices connected to the bus receive all the signals broadcast." '578 Patent, col. 1:29-33 This could support a narrower definition requiring a simultaneous, controller-driven push of the same data to all targeted units, which may differ from a multicast copy to shared memory.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for all six patents, asserting that Nvidia knowingly encourages and instructs customers and end users to infringe. The allegations are supported by citations to Nvidia's technical reference manuals, developer blogs, programming guides (e.g., for CUDA), and marketing materials, which allegedly describe how to use the accused functionalities like MPO, MIG, and the A/B boot layout. Compl. ¶12 Compl. ¶23 Compl. ¶68
• Willful Infringement: The complaint alleges willful infringement for all asserted patents. For five of the patents, willfulness is primarily based on alleged pre-suit knowledge from notice letters sent starting on December 3, 2024. Compl. ¶16 Compl. ¶27 Compl. ¶38 Compl. ¶61 Compl. ¶72 For U.S. Patent No. 8,275,975, the complaint makes a more specific allegation of earlier knowledge, claiming Nvidia was aware of the patent family as of at least June 20, 2014, because it was cited as prior art in a USPTO office action against one of Nvidia's own patent applications. Compl. ¶44 Compl. ¶50

VII. Analyst's Conclusion: Key Questions for the Case

1. Architectural Analogy: A central issue spanning multiple patents (U.S. Patent Nos. 7,805,578, 7,757,048, and 8,275,975) will be one of mapping. Can the arguably simpler, more conceptual architectures claimed in these 2005-2008 priority-date patents be legitimately mapped onto the complex, highly evolved GPU and SoC architectures of Nvidia's modern products? The court will need to determine if features like a "GigaThread Engine" or "Distributed Shared Memory" are functionally equivalent to the patents' "array controller" and memory-based "broadcast" systems.
2. Definitional Scope: The dispute will likely focus on the construction of foundational technical terms. For the U.S. Patent No. 7,924,296 patent, does blending distinct graphical "layers" or "windows" (e.g., a UI over a video) meet the claim requirement of blending a "plurality of images"? For the U.S. Patent No. 8,151,136 patent, does an "A/B Slot Layout" for redundant boot firmware constitute a method for correcting "code data error" as claimed, or is it merely a redundancy mechanism that does not perform error correction?
3. Willfulness and Pre-Suit Knowledge: Beyond the technical merits, a key factual question will be the extent and timing of Nvidia's knowledge of the patents. The allegation that Nvidia was aware of the U.S. Patent No. 8,275,975 patent family as early as 2014 via a USPTO rejection presents a potentially significant issue for willfulness that is distinct from the more common basis of a recent notice letter.