Intellectual Ventures I LLC v. Lenovo Group Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Intellectual Ventures I LLC and Intellectual Ventures II LLC (Delaware)
  • Defendant: Lenovo Group Limited (China)
  • Plaintiff’s Counsel: Sorey & Hoover, LLP; Prince Lobel Tye LLP
• Case Identification: 1:25-cv-00834, W.D. Tex., 06/02/2025
• Venue Allegations: Plaintiff alleges venue is proper because a substantial part of the infringing acts occurred in the district and the defendant is a foreign entity.
• Core Dispute: Plaintiff alleges that Defendant’s computers, smartphones, and tablets infringe six patents related to processor architecture, memory calibration, and wireless communication technologies.
• Technical Context: The patents-in-suit address foundational technologies in modern computing, from efficient virtualization in processors to high-speed memory timing and standardized protocols for wireless communication.
• Key Procedural History: The complaint references prior litigation between semiconductor company Transmeta and Intel, noting that Plaintiff later acquired patents from the Transmeta portfolio. Plaintiff alleges it provided Defendant with pre-suit notice of infringement for the asserted patents through presentations and claim charts in 2022 and 2023 and via prior litigation involving some of the same patents.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,522,253 - HARDWARE SUPPORT FOR VIRTUAL MACHINE AND OPERATING SYSTEM CONTEXT SWITCHING IN TRANSLATION LOOKASIDE BUFFERS AND VIRTUALLY TAGGED CACHES

The Invention Explained

• Problem Addressed: In computers supporting virtualization, switching between different virtual machines ("world switching") or between different software processes ("context switching") conventionally required the system to flush its Translation Lookaside Buffer (TLB), a high-speed cache for memory address translations. These frequent flushes were computationally expensive and created performance inefficiencies Compl. ¶15-16
• The Patented Solution: The invention proposes a method to reduce these costly flushes by adding more granular identification to each entry in the TLB. Each entry is tagged with two separate identifiers: a first context ID for the specific software process and a second context ID for the virtual machine in which it is running ’253 Patent, Abstract Compl. ¶17 This allows the processor to differentiate between entries belonging to different processes within the same VM and entries belonging to different VMs, thereby avoiding the need to invalidate the entire TLB during many context or world switches ’253 Patent, col. 2:56-67
• Technical Importance: This approach was designed to improve processor efficiency in virtualized environments by reducing the overhead associated with managing memory address caches during frequent task switching Compl. ¶17

Key Claims at a Glance

• The complaint asserts independent claim 5 Compl. ¶78-79
• Claim 5 is a method claim with the following essential elements:
  • storing a first context ID and a second context ID in at least one entry of a translation lookaside buffer (TLB);
  • storing a virtual address tag in the entries;
  • searching the TLB, which comprises:
    • comparing the entry's first context ID with a first provided context ID;
    • comparing the entry's second context ID with a second provided context ID;
    • setting a match signal if at least one of the first or second comparisons indicates a match;
    • comparing the entry's virtual address tag with a provided virtual address tag; and
    • generating a third match signal.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 7,646,835 - METHOD AND SYSTEM FOR AUTOMATICALLY CALIBRATING INTRA-CYCLE TIMING RELATIONSHIPS FOR SAMPLING SIGNALS FOR AN INTEGRATED CIRCUIT DEVICE

The Invention Explained

• Problem Addressed: High-speed memory systems, such as Double Data Rate (DDR) memory, depend on precise timing synchronization between command signals, data signals, and sampling (strobe) signals. As clock speeds increased, minor timing variations caused by environmental factors, manufacturing differences, or component aging could lead to read/write errors and system instability, problems that manual calibration struggled to address effectively Compl. ¶22-24
• The Patented Solution: The patent describes a method for a memory controller to automatically calibrate these critical timing relationships. The controller systematically alters the phase shifts of the command, data, and sampling signals to test different timing configurations. By analyzing the results, it identifies a "valid operation range" and an optimal operating point, allowing the system to maintain reliable memory access even as operating conditions vary over time (’835 Patent, Abstract; Compl. ¶25, 55).
• Technical Importance: Automatic calibration of signal timing became essential for the development and reliable operation of successive generations of high-speed memory, enabling increased performance and greater stability in computer systems Compl. ¶25

Key Claims at a Glance

• The complaint asserts independent claim 1 Compl. ¶98, 100
• Claim 1 is a method claim with the following essential elements:
  • generating command signals to access an integrated circuit component;
  • accessing data signals to convey data for the component;
  • accessing sampling signals to control sampling of the data signals;
  • systematically altering a phase shift of the command signals, a phase shift of the data signals, and a phase shift of the sampling signals to determine a valid operation range that includes an optimal operation point.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

Multi-Patent Capsules

• Patent Identification: U.S. Patent No. 7,623,439, CYCLIC DIVERSITY SYSTEMS AND METHODS, issued November 24, 2009.

• Technology Synopsis: The patent addresses signal interference in wireless systems using multiple antennas (MIMO) and Orthogonal Frequency Division Multiplexing (OFDM). Conventional methods used "cyclic delay" to differentiate signals, but this could be confused with natural multipath delays. The invention proposes using "cyclic advancement," which shifts a portion of a symbol's data forward into its guard interval, a technique intended to allow a receiver to more easily distinguish the intentional diversity shift from environmental delays and thereby improve reception reliability Compl. ¶31-33, 59

• Asserted Claims: Independent claim 1 is asserted Compl. ¶121-122

• Accused Features: Wireless products supporting IEEE 802.11n, 802.11ac, and 802.11ax standards, which allegedly mandate a "cyclic shift diversity" feature that performs the claimed cyclic advancement Compl. ¶121, 123

• Patent Identification: U.S. Patent No. 8,594,122, TRANSMIT ANNOUNCMENT INDICATION, issued November 26, 2013.

• Technology Synopsis: The patent aims to improve wireless network efficiency by reducing transmission overhead. A device sends a first data frame containing a "transmit announcement" that signals a second frame will follow immediately (within a Short Inter-Frame Space, or SIFS). This announcement allows the second frame to be transmitted without the recipient's address, as the recipient is already expecting it, thereby reducing overhead and increasing throughput Compl. ¶37-39, 63

• Asserted Claims: Independent claim 27 is asserted Compl. ¶142-143

• Accused Features: Products supporting the IEEE 802.11ac beamforming standard, which utilizes the Very High Throughput (VHT) Sounding Protocol. This protocol is alleged to use an announcement frame followed by an address-less transmission after a SIFS, mapping to the claimed method Compl. ¶142, 144-148

• Patent Identification: U.S. Patent No. 11,700,544, COMMUNICATING OVER MULTIPLE RADIO ACCESS TECHNOLOGIES (RAT), issued July 11, 2023.

• Technology Synopsis: To meet high bandwidth demands like video streaming, this invention describes a system where a mobile device can use two different radio access technologies (e.g., 4G/LTE and 5G) simultaneously to receive a single stream of data. This differs from using one RAT as a mere fallback for the other. The system is designed to use the same packet data protocol and security keys across both connections to minimize overhead Compl. ¶43, 67, 158

• Asserted Claims: Independent claim 1 is asserted Compl. ¶161-162

• Accused Features: Mobile devices with Qualcomm chipsets that feature "dual simultaneous connectivity" or "Multi-Radio Dual Connectivity" (MR-DC), allowing for the simultaneous use of 4G/LTE and 5G NR networks as specified in 3GPP standards Compl. ¶161, 164

• Patent Identification: U.S. Patent No. 11,363,564, PAGING IN A WIRELESS NETWORK, issued June 14, 2022.

• Technology Synopsis: This patent describes a more efficient method for a cellular network to "page" or wake up a mobile device from sleep mode. Instead of sending both a small paging indicator and the larger paging message on the same, often low-bandwidth, control channel, the invention uses two channels. The device monitors a control channel for the indicator, and upon detection, is directed to a separate, high-bandwidth shared channel to receive the full paging message, which speeds up connection establishment Compl. ¶47, 71, 184

• Asserted Claims: Independent claim 1 is asserted Compl. ¶187-188

• Accused Features: Mobile devices compliant with 3GPP LTE and 5G NR standards. These standards are alleged to use a two-stage paging procedure where a device monitors a control channel (PDCCH) for a paging identity (P-RNTI) that then directs it to a shared channel (PDSCH) to receive the paging message Compl. ¶187, 192-194

III. The Accused Instrumentality

Product Identification

• The complaint identifies a broad category of accused products, including computers, desktops, tablets, smartphones, and laptops sold by Defendant Compl. ¶78, 98, 121, 142, 161, 187 Specific examples cited include the Motorola Razr+ 2024, Lenovo Yoga Slim 7x, ThinkPad T14s Gen 6 Snapdragon, Legion Tab Gen 3, Lenovo Yoga Tab Plus, and the Motorola moto g 5G family of smartphones Compl. ¶78, 98, 121, 142, 161, 187

Functionality and Market Context

• The accused functionality for each patent is tied to the use of industry-standard components and protocols within these devices. For the '253 Patent, it is the virtualization support in ARM Cortex-A78 processors Compl. ¶78 For the '835 Patent, it is the memory calibration process for LPDDR4/5 memory mandated by JEDEC standards Compl. ¶98-99 For the remaining patents, it is the implementation of features required by wireless standards such as IEEE 802.11 and 3GPP 4G/5G Compl. ¶121, 142, 161, 187 The complaint alleges Lenovo is a leading manufacturer of these devices, generating significant revenue from their sale in the United States Compl. ¶4, 8 A screenshot from an ARM technical manual describes the TLB match process, which is central to the '253 infringement allegations Compl. ¶80, p. 31 A block diagram from a Qualcomm product brief for the Snapdragon X Plus platform, used in accused laptops, illustrates the memory controller and DRAM interface relevant to the '835 allegations Compl. ¶103, p. 51

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,522,253 Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: A central question may be whether the terms "first context ID" and "second context ID," as understood in the patent, are definitionally equivalent to the "ASID" and "VMID" used in the accused ARM architecture. The defense may argue that these are distinct technical concepts from different ecosystems that do not map one-to-one.
  • Technical Questions: The claim requires setting a match signal "if at least one of" the context ID comparisons match. The complaint describes the accused logic as sometimes requiring both ASID and VMID to match Compl. ¶84 This raises the question of whether the accused product's conjunctive (AND-like) logic literally meets the claim's disjunctive (OR-like) language.

U.S. Patent No. 7,646,835 Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: A potential dispute is whether the JEDEC-standard "training" performed at device initialization qualifies as the "systematically altering... to determine a valid operation range" recited in the claim. The defense may argue the patent envisions a more dynamic or comprehensive calibration process than the standardized power-on procedure.
  • Technical Questions: The claim recites a single step of "systematically altering" the phase shifts of three distinct signal types. The complaint alleges this is met by three separate training procedures defined in the JEDEC standard Compl. ¶107 A question for the court may be whether performing these three distinct procedures constitutes infringement of the single, integrated step recited in the claim.

V. Key Claim Terms for Construction

For the ’253 Patent

• The Term: "context ID"
• Context and Importance: This term is foundational to the infringement theory against the '253 patent. The Plaintiff's case hinges on construing "first context ID" to read on the ARM architecture's Address Space Identifier (ASID) and "second context ID" to read on the Virtual Machine Identifier (VMID). The definition of this term will determine if the patent's concepts map to the accused technology.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes a context as the "stored/restored state" of a CPU for a given process and notes that context switching involves storing and restoring this state Compl. ¶15 This general, functional description could support a broad interpretation where any identifier that distinguishes between such states (like ASID and VMID) qualifies as a "context ID."
  • Evidence for a Narrower Interpretation: The detailed description explicitly refers to the two fields as a "per-process context-ID field" and a "virtual machine context-ID field" ’253 Patent, col. 3:19-25 A defendant may argue this language limits the term to this specific two-level hierarchical structure, which may differ from the way ASID and VMID are implemented and used within the ARM architecture.

For the ’835 Patent

• The Term: "systematically altering"
• Context and Importance: The infringement case for the '835 patent relies on equating the JEDEC-mandated memory "training" process with the claimed step of "systematically altering" phase shifts. The construction of this term will be critical to determining if a standardized initialization routine falls within the scope of the claimed calibration method.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent abstract describes the invention as automatically adjusting the phase relationship to "calibrate operation." The general nature of this language may support a construction where any automated, ordered process of adjustment for calibration purposes, such as the JEDEC training sequences, is "systematic."
  • Evidence for a Narrower Interpretation: The specification includes pseudo-code illustrating a calibration method that explores the parameter space by starting at the boundaries (e.g., 0% and 100%) and moving inward ’835 Patent, col. 6:1-20 A defendant could argue this teaches a specific type of exploratory search algorithm and that "systematically" should be construed to require such a search, which may differ from the predefined patterns used in standard JEDEC training.

VI. Other Allegations

• Indirect Infringement: For all six patents, the complaint alleges induced infringement based on Defendant's advertising, user manuals, and technical documentation that allegedly instruct customers on how to use the accused products in their infringing, standard-compliant modes Compl. ¶87, 109, 129, 150, 177, 198 Contributory infringement is also alleged, based on Defendant knowingly providing key components (e.g., ARM-based processors, Qualcomm chipsets, 802.11-compliant Wi-Fi modules) that are a material part of the inventions and not suitable for substantial non-infringing use Compl. ¶88, 110, 130, 151, 199
• Willful Infringement: The complaint alleges that Defendant had pre-suit knowledge of all asserted patents. This knowledge is based on a series of alleged communications, including PowerPoint presentations and claim charts sent to Lenovo in 2022 and 2023, as well as notice from prior litigation involving some of the same asserted patents. Willfulness is also alleged based on knowledge obtained from the service of the current complaint Compl. ¶89, 111, 131, 152, 178, 200

VII. Analyst’s Conclusion: Key Questions for the Case

This case presents a broad challenge to standardized technologies across the computing and telecommunications sectors. The outcome will likely depend on the court's resolution of several key, overarching questions:

• A core issue will be one of definitional scope and standards mapping: Can terms from patents developed in the early-to-mid 2000s (e.g., "context ID," "cyclic advance," "transmit announcement") be construed to cover the specific, and often more complex, implementations of similar concepts in modern, widely adopted industry standards (e.g., ARMv8's ASID/VMID, IEEE 802.11's cyclic shift, 3GPP's paging procedures)?
• A key evidentiary question will be one of functional equivalence: For each patent, does the accused standard-compliant feature perform substantially the same function, in substantially the same way, to achieve the same result as the claimed invention? For example, with respect to the '835 patent, is a one-time, power-on "training" sequence functionally equivalent to the claimed method of "systematically altering" signal phases to determine an optimal operating range?
• A critical factual question for damages will be willfulness and pre-suit knowledge: The complaint makes specific allegations of providing notice to the Defendant through presentations and prior litigation. The evidence surrounding these communications will be central to determining whether any infringement was willful, which could expose the Defendant to the possibility of enhanced damages.