DCT

1:25-cv-00834

Intellectual Ventures I LLC v. Lenovo Group Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-00834, W.D. Tex., 06/02/2025
  • Venue Allegations: Venue is alleged to be proper because the defendant is a foreign entity and a substantial part of the alleged acts of infringement occurred and continue to occur within the district.
  • Core Dispute: Plaintiff alleges that Defendant's computers, tablets, and smartphones infringe six patents related to processor virtualization, high-speed memory calibration, wireless communication diversity schemes, network overhead reduction, simultaneous use of multiple radio access technologies, and cellular paging procedures.
  • Technical Context: The asserted patents cover fundamental technologies in modern computing and wireless communications, including processor efficiency in virtualized environments, performance of high-speed DDR memory, and functions essential to Wi-Fi and 4G/5G cellular standards.
  • Key Procedural History: The complaint references a 2006 patent infringement lawsuit between Transmeta (the original assignee of several asserted patents) and Intel, which resulted in a settlement. The complaint also alleges that Plaintiff provided Defendant with notice of certain asserted patents in presentations dating back to October 2022, forming a basis for allegations of willful infringement.

Case Timeline

Date Event
2000-01-01 Transmeta launches its first product, the Crusoe processor
2000-11-07 Transmeta holds its initial public offering
2003-10-01 Transmeta launches its second processor, the Efficeon
2003-11-17 Priority Date for U.S. Patent No. 7,646,835
2004-05-20 Priority Date for U.S. Patent No. 7,623,439
2005-03-31 Priority Date for U.S. Patent No. 8,522,253
2006-01-25 Priority Date for U.S. Patent No. 8,594,122
2006-05-02 Priority Date for U.S. Patent No. 11,363,564
2006-08-11 Priority Date for U.S. Patent No. 11,700,544
2006-10-01 Transmeta sues Intel Corporation for patent infringement
2007-10-01 Transmeta and Intel settle their patent litigation
2009-01-01 Transmeta is acquired by Novafora Inc.
2009-02-01 Intellectual Ventures acquires patents from the Transmeta portfolio
2009-11-24 U.S. Patent No. 7,623,439 Issued
2010-01-12 U.S. Patent No. 7,646,835 Issued
2013-08-27 U.S. Patent No. 8,522,253 Issued
2013-11-26 U.S. Patent No. 8,594,122 Issued
2022-06-14 U.S. Patent No. 11,363,564 Issued
2022-10-01 Plaintiff allegedly presents to Defendant regarding the '253, '122, and '564 patents
2023-02-01 Plaintiff allegedly sends a PowerPoint to Defendant regarding infringement of the '253 patent
2023-07-11 U.S. Patent No. 11,700,544 Issued
2025-06-02 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,522,253 - HARDWARE SUPPORT FOR VIRTUAL MACHINE AND OPERATING SYSTEM CONTEXT SWITCHING IN TRANSLATION LOOKASIDE BUFFERS AND VIRTUALLY TAGGED CACHES

The Invention Explained

  • Problem Addressed: Conventional computers supporting multiple virtual machines (VMs) suffered from inefficiency because the processor's translation lookaside buffer (TLB)-a cache for memory address translations-had to be flushed frequently Compl. ¶16 This computationally expensive flushing occurred during both process-level "context switches" (within one VM) and VM-level "world switches" (between different VMs), leading to performance degradation Compl. ¶¶15-16
  • The Patented Solution: The invention proposes a method to reduce these flushes by tagging each entry in the TLB with two distinct identifiers: a "first context ID" for the specific process and a "second context ID" for the specific VM '253 Patent, abstract '253 Patent, col. 4:21-44 This dual-tagging system allows TLB entries for multiple processes and multiple VMs to coexist within the cache simultaneously, obviating the need to invalidate all entries during a context or world switch Compl. ¶17 Compl. ¶74
  • Technical Importance: This approach improves the operational efficiency of computer systems that rely on virtualization by reducing the computational overhead associated with managing memory address translations across different virtual environments Compl. ¶17

Key Claims at a Glance

  • The complaint asserts at least independent claim 5 Compl. ¶78
  • Claim 5 is a method claim with the following essential elements:
    • storing a first context ID and a second context ID in at least one entry of entries in a translation lookaside buffer (TLB);
    • storing a virtual address tag in the entries; and
    • searching the TLB, wherein the search comprises:
      • comparing a first context ID of an entry with a first provided context ID to generate a first match signal;
      • comparing a second context ID of the entry with a second provided context ID to generate a second match signal;
      • setting a match signal to a match state if at least one of the first match signal or the second match signal indicates a match;
      • comparing the virtual address tag of the entry with a provided virtual address tag; and
      • generating a third match signal.

U.S. Patent No. 7,646,835 - METHOD AND SYSTEM FOR AUTOMATICALLY CALIBRATING INTRA-CYCLE TIMING RELATIONSHIPS FOR SAMPLING SIGNALS FOR AN INTEGRATED CIRCUIT DEVICE

The Invention Explained

  • Problem Addressed: High-performance memory systems, such as DDR2, require extremely precise timing synchronization between command, data, and sampling signals to function reliably Compl. ¶¶23-24 Factors like temperature, electromagnetic interference, and component aging can cause these signals to drift out of synchronization, leading to data errors and performance degradation Compl. ¶24
  • The Patented Solution: The patent describes a method for a memory controller to automatically and dynamically calibrate these critical timing relationships '835 Patent, abstract The system systematically alters the phase shifts of the various signals to explore the timing configuration space, identify a valid operational range, and determine an optimal operating point, thereby allowing the system to adapt to changing conditions throughout its operational life Compl. ¶25 '835 Patent, col. 3:5-18
  • Technical Importance: This automated calibration process is described as essential for achieving the high-speed, high-throughput, and error-free operation demanded by modern DDR memory standards and their successors, such as LPDDR4 and LPDDR5 Compl. ¶25

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 Compl. ¶98
  • Claim 1 is a method claim with the following essential elements:
    • generating command signals to access an integrated circuit component;
    • accessing data signals to convey data for the integrated circuit component;
    • accessing sampling signals to control sampling of the data signals; and
    • systematically altering a phase shift of the command signals, a phase shift of the data signals, and a phase shift of the sampling signals to determine a valid operation range of the integrated circuit device, wherein the valid operation range includes an optimal operation point for the integrated circuit device.

U.S. Patent No. 7,623,439 - CYCLIC DIVERSITY SYSTEMS AND METHODS

  • Technology Synopsis: The patent addresses a problem in certain wireless (MIMO-OFDM) systems where using a time delay on one antenna signal for diversity can be confused with natural multipath delays by simpler receivers Compl. ¶¶30-32 The patented solution uses "cyclic advancement," which shifts signal samples forward in time into the guard interval, creating a temporal shift that is opposite to multipath delay and allows the receiver to acquire the signal more reliably, thereby reducing packet error rates Compl. ¶33 Compl. ¶59
  • Asserted Claims: At least claim 1 Compl. ¶121
  • Accused Features: Wireless products supporting IEEE 802.11n, 802.11ac, and 802.11ax standards, which allegedly mandate a cyclic diversity shift feature for transmitting OFDM packets Compl. ¶121

U.S. Patent No. 8,594,122 - TRANSMIT ANNOUNCMENT INDICATION

  • Technology Synopsis: The technology aims to reduce communication overhead in wireless networks, particularly for overhead-intensive features like beamforming Compl. ¶36 The invention proposes a method where a first communication frame includes a "transmit announcement indication," which signals that a second frame will follow immediately (after a short inter-frame space) but will omit the recipient's address; this omission frees up bandwidth for other data, increasing system efficiency Compl. ¶¶37, 39
  • Asserted Claims: At least claim 27 Compl. ¶142
  • Accused Features: Wireless products that support IEEE 802.11ac beamforming and its Very High Throughput (VHT) Sounding Protocol, which is alleged to use the claimed transmit announcement system Compl. ¶142

U.S. Patent No. 11,700,544 - COMMUNICATING OVER MULTIPLE RADIO ACCESS TECHNOLOGIES (RAT)

  • Technology Synopsis: To meet high bandwidth demands for mobile devices, this invention describes a system where a device (UE) can use two different radio access technologies (e.g., 4G/LTE and 5G) simultaneously for a single data download, rather than using one as a mere fallback Compl. ¶43 To minimize overhead, the system uses the same packet data protocol and security keys across both connections Compl. ¶43 Compl. ¶159
  • Asserted Claims: At least claim 1 Compl. ¶161
  • Accused Features: Mobile devices, such as the Motorola moto g Stylus 5G, that include Qualcomm Snapdragon chipsets featuring dual simultaneous connectivity using 4G/LTE and 5G RATs Compl. ¶44 Compl. ¶161

U.S. Patent No. 11,363,564 - PAGING IN A WIRELESS NETWORK

  • Technology Synopsis: The patent describes an improved paging procedure for waking a mobile device from sleep mode in a cellular network Compl. ¶45 Instead of sending both a paging indicator and the full paging message on the same low-bandwidth control channel, the invention separates them: the device monitors a control channel for the indicator and, upon detection, is directed to a separate, high-bandwidth shared channel to receive the larger paging message, leading to faster and more efficient connection establishment Compl. ¶47 Compl. ¶71
  • Asserted Claims: At least claim 1 Compl. ¶187
  • Accused Features: Devices configured to support 3GPP LTE and/or 3GPP 5G NR cellular standards, such as the Motorola Razr+ Compl. ¶48 Compl. ¶187

III. The Accused Instrumentality

Product Identification

The complaint targets a broad range of Lenovo's products, including computers, desktops, tablets, smartphones, and laptops Compl. ¶78 Specific examples cited include the Motorola Razr+ 2024, Lenovo Yoga Slim 7x, ThinkPad T14s Gen 6, Legion Tab Gen 3, Lenovo Yoga Tab Plus, and Motorola moto g Stylus 5G Compl. ¶78 Compl. ¶98 Compl. ¶121 Compl. ¶142 Compl. ¶161 Compl. ¶187

Functionality and Market Context

  • The infringement allegations focus on core components and standards-essential functions within the accused products.
  • For the '253 Patent, the accused functionality resides in the ARM Cortex-A78 based processors, which allegedly use Address Space Identifiers (ASID) and Virtual Machine Identifiers (VMID) to manage memory translations in a manner that infringes the patent's claims for dual context IDs Compl. ¶80 A screenshot from an ARM technical manual is provided to show that each TLB entry contains fields for both an ASID and a VMID Compl. p. 31
  • For the '835 Patent, the accused functionality is the automatic memory calibration ("training") performed by Qualcomm Snapdragon processors to ensure compatibility and performance with high-speed LPDDR4/4X/5/5X memory modules Compl. ¶¶101, 105-107 A diagram from the complaint illustrates the accused Qualcomm Snapdragon X Plus platform architecture, which includes the processor and DRAM Compl. p. 51
  • For the remaining patents, the allegations are tied to the products' compliance with wireless standards such as IEEE 802.11n/ac/ax (for the '439 and '122 patents) and 3GPP 4G/5G (for the '544 and '564 patents) Compl. ¶121 Compl. ¶142 Compl. ¶161 Compl. ¶187 The complaint alleges that these standards mandate the use of the claimed technologies. Product pages for the Lenovo Legion Tab Gen 3 and Motorola razr+ 2024 are included to show their support for these Wi-Fi and cellular standards Compl. p. 64

IV. Analysis of Infringement Allegations

'253 Patent Infringement Allegations

Claim Element (from Independent Claim 5) Alleged Infringing Functionality Complaint Citation Patent Citation
storing a first context ID and a second context ID in at least one entry of entries in a translation lookaside buffer (TLB); The accused ARM Cortex-A78 processors store an Address Space Identifier ("ASID") and a Virtual Machine Identifier ("VMID") in each TLB entry. ¶80 col. 4:26-28
storing a virtual address tag in the entries; Each TLB entry in the accused processors includes a Virtual Address ("VA"). ¶81 col. 4:22-23
searching the TLB, wherein said searching comprises: comparing a first context ID of an entry with a first provided context ID and generating a first match signal; A TLB lookup is performed for a current ASID by comparing it to the ASID stored in the TLB entry. ¶82 col. 4:44-51
comparing a second context ID of the entry with a second provided context ID and generating a second match signal; A TLB lookup is performed for a current VMID by comparing it to the VMID stored in the TLB entry. ¶83 col. 4:51-53
setting a match signal to a match state if at least one of the first match signal or the second match signal indicates a match; A match is set based on various conditions involving the ASID and VMID matching, including scenarios where both must match or where a global bit and VMID must match. ¶84 col. 5:1-9
comparing the virtual address tag of the entry with a provided virtual address tag; and generating a third match signal. The processor's Memory Management Unit (MMU) compares the requested virtual address with the virtual address present in the TLB entry to generate a match signal. ¶85 col. 4:40-44

Identified Points of Contention

  • Scope Questions: A central dispute may concern whether the ARM architecture's "ASID" and "VMID" correspond to the claimed "first context ID" and "second context ID." The patent describes the first ID as a "per-process" identifier and the second as a "virtual machine" identifier '253 Patent, col. 4:26-28 The analysis will question whether the function and scope of ASID/VMID in the accused products align with the patent's definitions.
  • Technical Questions: Claim 5 requires setting a match signal if "at least one" of the context ID comparisons indicates a match. The complaint alleges scenarios that may require both an ASID and VMID match Compl. ¶84 This raises the question of whether the logical "OR" condition of the claim reads on the allegedly more complex "AND" and conditional logic of the accused processors' TLB match process.

'835 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
generating command signals to access an integrated circuit component; Accused products use command/address (CA) signals to access LPDDR5X memory components, as specified by the JEDEC standard. ¶102 col. 3:5-6
accessing data signals to convey data for the integrated circuit component; Accused products use a bi-directional data (DQ) bus to convey data for the LPDDR5X memory. ¶103 col. 3:7-8
accessing sampling signals to control sampling of the data signals; Accused products use WCK2CK Leveling, which involves accessing sampling signals (WCK) to control the sampling of data signals. ¶104 col. 3:8-10
systematically altering a phase shift of the command signals, a phase shift of the data signals, and a phase shift of the sampling signals to determine a valid operation range... Accused products perform mandatory "training" procedures at initialization, including Command Bus training, WCK-DQ training, and WCK2CK Leveling, which allegedly alter the phase/timing of CA, DQ, and sampling signals to establish critical timing relationships and ensure reliable operation. ¶¶105-107 col. 3:10-18

Identified Points of Contention

  • Scope Questions: The infringement case hinges on whether the JEDEC-specified "training" procedures fall within the scope of "systematically altering... to determine a valid operation range." This raises the question of whether "training" is an exploratory process that "determines" a range, as the claim may require, or if it is a pre-defined, one-time configuration sequence that merely sets, rather than determines, operating parameters.
  • Technical Questions: The patent describes a process that can find an "optimal operation point" '835 Patent, abstract The analysis will question what evidence the complaint provides that the accused JEDEC training procedures are designed to find an "optimal" point, as opposed to merely a "functional" or "compliant" one.

V. Key Claim Terms for Construction

'253 Patent

  • The Term: "a first context ID" and "a second context ID"
  • Context and Importance: The applicability of the patent to the accused ARM-based processors depends entirely on the construction of these terms. The infringement theory equates them with the ARM architecture's ASID and VMID, respectively. Practitioners may focus on whether the claimed terms are limited to the specific roles described in the patent's embodiments or can be construed more broadly to cover any dual-identifier system for processes and virtual environments.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claims themselves do not specify the exact nature of the context IDs, referring to them generically. This may support a construction covering any pair of identifiers used to distinguish processes and virtual environments.
    • Evidence for a Narrower Interpretation: The specification explicitly describes the two fields as a "per-process context-ID field" and a "virtual machine context-ID field" '253 Patent, col. 4:26-28 This language could be used to argue that the terms are narrowly defined by these specific functions, potentially limiting the claim's scope.

'835 Patent

  • The Term: "systematically altering... to determine a valid operation range"
  • Context and Importance: This term is the core of the asserted method claim. The dispute will likely center on whether the accused JEDEC "training" protocol meets this functional requirement. Practitioners may focus on whether "determine" implies an active, searching process of discovery, or if it can cover a pre-programmed setup routine.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent states the method involves "systematically altering a phase shift," which could be argued to cover any ordered sequence of adjustments, including a standards-mandated training routine (Compl. ¶107).
    • Evidence for a Narrower Interpretation: The specification describes a process of searching a "configuration space" to "find the valid region of operation" '835 Patent, col. 4:10-13 and shows diagrams of parameter ranges with valid windows (e.g.,'835 Patent, FIG. 4). This could support a narrower construction requiring an exploratory search that identifies the boundaries of an operational window, not just a one-time setup.

VI. Other Allegations

Indirect Infringement

The complaint alleges both induced and contributory infringement for all asserted patents. The inducement claims are based on allegations that Defendant provides products (e.g., processors, chipsets) and encourages their use through advertisements, user manuals, and by promoting compliance with standards that allegedly require the infringing functionality Compl. ¶87 Compl. ¶109 Compl. ¶129 Compl. ¶150 Compl. ¶177 Compl. ¶198

Willful Infringement

The complaint alleges that Defendant had pre-suit knowledge of the '253, '122, and '564 patents based on presentations Plaintiff made to Lenovo in October 2022, and specific knowledge of infringement of the '253 patent from a presentation in February 2023 Compl. ¶89 Compl. ¶152 Compl. ¶200 For the '835 and '439 patents, pre-suit knowledge is alleged based on the filing of a prior complaint in a different case Compl. ¶111 Compl. ¶131 Post-suit knowledge is alleged for all patents based on the service of the present complaint.

VII. Analyst's Conclusion: Key Questions for the Case

  • Claim Scope and Technical Mapping: A primary issue for several patents, particularly the '253 patent, will be one of definitional scope: can terms like "first context ID" and "second context ID," which are functionally defined in the patent, be construed to read on established industry terms of art like "ASID" and "VMID" used in the accused ARM architecture? The outcome will depend on whether the court finds a direct functional correspondence or a material difference in operation.
  • Standards Compliance as Infringement: For the '835, '439, '122, '544, and '564 patents, the infringement theories are heavily reliant on the accused products' compliance with JEDEC, IEEE, and 3GPP standards. A key evidentiary question will be one of functional equivalence: do the procedures mandated by these technical standards (e.g., memory "training," "cyclic diversity shift") in fact perform the specific, and potentially more detailed, steps required by the patent claims, or is there a fundamental mismatch in the claimed function versus the standardized implementation?
  • Portfolio Defense Strategy: The assertion of six distinct patents across a wide range of core technologies presents a significant strategic challenge for the Defendant. A central question will be how Lenovo manages a multi-front defense against allegations that implicate not only its own product designs but also its reliance on fundamental components and industry standards from major technology partners like ARM and Qualcomm.
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