Eireog Innovations Ltd v. Oracle Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Eireog Innovations Ltd. (Ireland)
  • Defendant: Oracle Corporation (Delaware)
  • Plaintiff's Counsel: BC LAW GROUP, P.C.
• Case Identification: 1:24-cv-00697, W.D. Tex., 06/24/2024
• Venue Allegations: Venue is based on Defendant Oracle Corporation having regular and established places of business within the Western District of Texas, including a principal place of business in Austin, and having committed alleged acts of infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant's server and cloud products, which utilize certain Intel and AMD central processing units (CPUs), infringe four patents related to processor architecture, specifically concerning interrupt management, virtualization enhancements, and cache processing.
• Technical Context: The patents address low-level processor functions designed to enhance performance in complex computing environments, such as reducing latency in virtualized systems and optimizing cache coherency, which are critical in the enterprise server and cloud computing markets.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the asserted patents. The complaint states that Plaintiff and its predecessors have not sold products practicing the patents, thereby asserting compliance with marking requirements under 35 U.S.C. § 287.

Case Timeline

Date	Event
2009-05-07	'399 Patent Priority Date
2010-09-21	'777 Patent Priority Date
2012-02-14	'399 Patent Issue Date
2012-08-09	'626 Patent Priority Date
2012-08-09	'870 Patent Priority Date
2013-08-06	'777 Patent Issue Date
2016-09-06	'626 Patent Issue Date
2016-09-13	'870 Patent Issue Date
2024-06-24	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,436,626 - "Processor interrupt interface with interrupt partitioning and virtualization enhancements"

The Invention Explained

• Problem Addressed: In virtualized or partitioned data processing systems, managing interrupts through a software-based hypervisor or Virtual Machine Monitor (VMM) creates performance problems, adding "delay, overhead, and complexity" that can adversely affect system performance, especially when an interrupt is targeted to an inactive partition (virtual machine) '626 Patent, col. 3:40-58
• The Patented Solution: The invention proposes an interrupt management system where an interrupt request sent to the processor includes context information such as a "partition ID." This enables the processor to "directly deliver interrupts and their associated context information to the target partition without intervention by a hypervisor program" '626 Patent, col. 2:27-39 '626 Patent, abstract This is accomplished by comparing the incoming partition ID with partition ID values stored in processor core registers '626 Patent, col. 2:35-39 Figure 3 of the patent illustrates the flow of interrupt information, including the partition identifiers (LPID, VPID), to the processor core '626 Patent, Fig. 3
• Technical Importance: This hardware-based approach to interrupt routing was designed to reduce latency and software overhead in multi-partition systems, a critical factor for improving performance in cloud computing and other large-scale virtualized environments.

Key Claims at a Glance

• The complaint asserts independent claim 1 Compl. ¶10
• Essential elements of independent claim 1 include:
  • receiving at the processor an interrupt package from an interrupt controller, where the package comprises a first interrupt request, an interrupt identifier, a partition identifier, a priority value, and a thread identifier; and
  • processing the interrupt package against one or more partitions running on the processor by comparing the priority value and partition identifier against a stored priority level and stored partition identifier retrieved from special purpose registers to determine if the interrupt is blocked or forwarded to a targeted thread.
• The complaint reserves the right to assert additional claims Compl. ¶10

U.S. Patent No. 9,442,870 - "Interrupt priority management using partition-based priority blocking processor registers"

The Invention Explained

• Problem Addressed: Similar to the '626 Patent, managing interrupt priority blocking conditions at a central interrupt controller through software creates "performance problems" and complexity, particularly when the VMM must process an interrupt for an inactive partition '870 Patent, col. 3:40-58
• The Patented Solution: The patent describes a "partitioned priority blocking mechanism" located at the virtual core of a processor '870 Patent, abstract This mechanism uses "special purpose interrupt priority registers" within the processor core itself to evaluate and manage interrupt requests on a per-partition basis, allowing for "quick and efficient interrupt priority blocking at the targeted processor" '870 Patent, col. 4:50-54 This decentralizes priority management from the interrupt controller to the individual processor cores. Figure 2 illustrates these dedicated priority blocking registers within the virtual core for both a "Guest" and a "VMM" partition '870 Patent, Fig. 2
• Technical Importance: This architecture enables more autonomous and efficient interrupt handling within each processor core, reducing reliance on a centralized controller and the VMM, thereby lowering interrupt response times in partitioned systems.

Key Claims at a Glance

• The complaint asserts independent claim 1 Compl. ¶20
• Essential elements of independent claim 1 include:
  • receiving at the processor an interrupt package for a first physical interrupt request, where the package comprises a first priority value and a first partition identifier; and
  • processing the interrupt package against partitions running on targeted virtual processors by comparing the first priority value and partition identifier against a stored priority level and partition identifier retrieved from special purpose registers at the processor to determine if the request is blocked or forwarded.
• The complaint reserves the right to assert additional claims Compl. ¶20

U.S. Patent No. 8,504,777 - "Data processor for processing decorated instructions with cache bypass"

• Technology Synopsis: The patent addresses the processing of "decorated" instructions, which are instructions carrying extra metadata. When a decorated instruction specifies a "cache bypass" and its target address is found in the cache (a cache hit), the processor invalidates that cache entry and sends the instruction directly to memory for a memory controller to perform the operation '777 Patent, abstract This is intended for operations like atomic memory updates, where bypassing the cache can avoid complex coherency issues.
• Asserted Claims: Independent claim 16 Compl. ¶30
• Accused Features: The complaint alleges that Intel and AMD CPUs, which utilize instruction prefixes (the "decorators") and support instructions with non-temporal or cache-bypassing semantics (e.g., Intel's "MOVNTI" instruction), infringe the '777 Patent Compl. Ex. 13 Compl. Ex. 14

U.S. Patent No. 8,117,399 - "Processing of coherent and incoherent accesses at a uniform cache"

• Technology Synopsis: The patent describes a unified cache where each cache line is marked as either "coherent" or "incoherent." The cache handles subsequent reads differently based on this mark and the type of read access '399 Patent, abstract A coherent read to a cache line marked "incoherent" results in a cache miss, forcing a system-wide check for a newer version of the data. An incoherent read to the same line can result in a cache hit, returning the data faster. This mechanism aims to optimize performance by avoiding unnecessary coherency checks for data that does not require it, such as instruction fetches.
• Asserted Claims: Independent claim 14 Compl. ¶40
• Accused Features: The complaint accuses Intel and AMD CPUs of infringing by implementing cache coherency protocols (such as MESI and MOESI) that allegedly differentiate between coherent and incoherent memory accesses in a manner that maps onto the patent's claims Compl. Ex. 16 Compl. Ex. 17

III. The Accused Instrumentality

• Product Identification: The complaint identifies Oracle's products using Intel-based CPUs (Haswell-based architecture and newer) and AMD Zen-based/EPYC CPUs Compl. ¶¶9, 19, 29, 39 Specific product lines named include Oracle's x86 Servers, Exadata Database Servers, and OCI (Oracle Cloud Infrastructure) Bare Metal Servers Compl. ¶9
• Functionality and Market Context: The accused instrumentalities are high-performance computing platforms that form the backbone of Oracle's enterprise hardware and cloud service offerings. The infringement allegations focus not on the servers themselves, but on the low-level functionality of the Intel and AMD processors that power them. The complaint alleges that these processors implement specific features for interrupt virtualization, priority management, and cache coherency that infringe the asserted patents. For example, the complaint's exhibits point to Intel's Virtualization Technology for Directed I/O (VT-d), including "Posted-Interrupts," as an infringing functionality for the '626 and '870 patents Compl. Ex. 3, p. 7 Compl. Ex. 11, p. 7 A diagram from an Intel presentation included in the complaint illustrates how this feature allows for "Direct Delivery of a Virtual Interrupt to a Running VM," purportedly without VMM overhead Compl. Ex. 3, p. 29, Fig. 31 Another visual from an Intel manual shows the processor's front-end microarchitecture, including the instruction "Decode" block, which is alleged to handle the claimed "decorated access instructions" of the '777 patent Compl. Ex. 14, p. 4, Fig. 2-2

IV. Analysis of Infringement Allegations

'626 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
receiving at the processor an interrupt package provided by an interrupt controller, where the interrupt package comprises	The accused Intel CPUs receive interrupts from I/O devices, which are managed by features like the I/O APIC and the VT-d IOMMU. The complaint alleges these function as an interrupt controller.	¶10; Ex. 3, pp. 6-9	col. 2:27-39
a first interrupt request, an interrupt identifier corresponding to the first interrupt request,	Interrupt requests are delivered to the processor, and each is assigned a unique "interrupt vector" number which serves as an identifier.	¶10; Ex. 3, pp. 9-13	col. 2:29-30
a partition identifier identifying a partition at the processor associated with the first interrupt request,	The complaint alleges that Intel's virtualization architecture uses a Posted-Interrupt Descriptor (PID), which records interrupts for a specific Virtual Machine (VM), to function as the claimed partition identifier. The PID contains a vector identifying pending interrupts for that VM.	¶10; Ex. 3, pp. 14-16	col. 2:30
a priority value corresponding to the first interrupt request,	The interrupt vector number for each interrupt also defines its priority, with the upper bits of the vector representing the interrupt-priority class.	¶10; Ex. 3, pp. 17-18	col. 2:30-31
and a thread identifier identifying a thread at the processor for the first interrupt request; and	In Intel's architecture, each logical processor (thread) is assigned a unique APIC ID, which is used as the destination for interrupts.	¶10; Ex. 3, pp. 18-21	col. 2:30
processing the interrupt package against one or more partitions running on the processor by comparing the priority value and partition identifier against at least a stored priority level and stored partition identifier retrieved from special purpose registers...	Intel's Posted-Interrupt processing allegedly involves the processor core comparing the priority of a pending virtual interrupt against the priority level stored in the Virtual Processor Priority Register (VPPR) to determine if the interrupt should be delivered to the currently running VM. This comparison determines if the interrupt is blocked or forwarded.	¶10; Ex. 3, pp. 22-29	col. 2:31-39

• Identified Points of Contention:
  • Scope Questions: A central question will be whether the structures in Intel's VT-d and VMX architecture (e.g., the Posted-Interrupt Descriptor, VMCS pointer, APIC ID) correspond to the claimed "partition identifier" and "thread identifier". The patent describes a discrete "LPID" and "VPID" being conveyed in an interrupt package '626 Patent, Fig. 3, whereas the accused functionality relies on a more complex system of descriptors and pointers. The court may need to determine if these are equivalent.
  • Technical Questions: The analysis will likely focus on whether the operational steps of Intel's Posted-Interrupt mechanism function in the same way as the claimed method. For example, does the comparison involving the VPPR constitute comparing against a "stored partition identifier" as required by the claim, or does it represent a different technical process?

'870 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
receiving at the processor an interrupt package for a first physical interrupt request, where the interrupt package comprises a first priority value and a first partition identifier; and	The accused Intel CPUs receive interrupt packages that include a priority (derived from the interrupt vector) and a target VM (the alleged "partition," identified via the Posted-Interrupt Descriptor).	¶20; Ex. 11, pp. 6-13	col. 3:40-58
processing the interrupt package against one or more partitions running on one or more targeted virtual processors at the processor by comparing the first priority value and first partition identifier against at least a stored priority level and stored partition identifier retrieved from one or more special purpose registers at the processor to determine on a partition basis if the first physical interrupt request is blocked or forwarded to a targeted virtual processor.	The complaint alleges that when Intel's Posted-Interrupt feature is enabled, the processor core determines whether to block or forward a virtual interrupt to a VM by comparing the interrupt's priority to the priority level stored in the Virtual Processor Priority Register (VPPR). This register is alleged to be the claimed "special purpose register" containing the "stored priority level."	¶20; Ex. 11, pp. 14-22	col. 4:47-54

• Identified Points of Contention:
  • Scope Questions: The dispute may center on the term "special purpose registers at the processor". The patent illustrates distinct "Guest Priority Blocking Register" and "VMM Priority Blocking Register" '870 Patent, Fig. 2 The case may turn on whether Intel's virtualized register architecture, such as the VPPR, which is part of the virtual-APIC page, meets the structural and functional requirements of this claim element.
  • Technical Questions: An evidentiary question will be whether the comparison performed by the Intel CPU involving the VPPR is functionally equivalent to the claimed step of "comparing the first priority value and first partition identifier against at least a stored priority level and stored partition identifier." The defense may argue that Intel's process is a priority-only comparison, not a combined priority and partition ID comparison as claimed. A state transition diagram for the MOESI protocol, used in AMD CPUs, is presented as evidence of the claimed processing of coherent and incoherent accesses ('399 patent), which will be a key point of technical dispute Compl. Ex. 16, p. 7, Fig. 7-2

V. Key Claim Terms for Construction

• For the '626 Patent:

  • The Term: "partition identifier"
  • Context and Importance: This term is the cornerstone for how the invention routes interrupts to the correct virtual machine without VMM intervention. The plaintiff's infringement case depends on mapping this term onto components of Intel's virtualization architecture, such as the Posted-Interrupt Descriptor or VMCS.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes a logical partition as a "collection of actual or emulated hardware resources" '626 Patent, col. 7:4-6, which could support a functional definition where any data structure that uniquely identifies such a collection (like a descriptor address) qualifies.
    • Evidence for a Narrower Interpretation: The patent explicitly depicts and refers to a "logical partition identifier (LPID)" as a discrete piece of data conveyed with the interrupt '626 Patent, Fig. 3, item 133 '626 Patent, col. 5:1-2 A defendant may argue this requires a specific ID field, not a pointer to a larger data structure.

• For the '870 Patent:

  • The Term: "special purpose registers at the processor"
  • Context and Importance: The invention's novelty lies in moving priority blocking to these registers within the processor core. Infringement hinges on whether Intel's virtualized registers, like the VPPR located on the virtual-APIC page, meet this definition.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language is broad, and the patent's goal is to enable "independent priority management" at the core '870 Patent, col. 4:50-54 Plaintiff may argue any register within the core used for this specific purpose qualifies.
    • Evidence for a Narrower Interpretation: Figure 2 of the patent shows distinct, named registers like the "Guest Priority Blocking Register" and "VMM Priority Blocking Register" '870 Patent, Fig. 2, items 27, 29 A defendant could argue this implies a specific hardware implementation with dedicated, non-virtualized registers, which may differ from the memory-based virtual-APIC page structure used by Intel.

VI. Other Allegations

• Indirect Infringement: The complaint alleges that Oracle induces infringement by providing customers with user manuals, datasheets, and other instructional materials that encourage and instruct them to configure and use the Accused Products in an infringing manner (e.g., by enabling virtualization features) Compl. ¶¶12, 22, 32, 42 Contributory infringement is alleged on the basis that the accused processor features are a material part of the inventions and are not staple articles of commerce suitable for non-infringing use Compl. ¶¶13, 23, 33, 43
• Willful Infringement: Willfulness allegations are based on Oracle's alleged knowledge of the patents and infringement "at least as of the filing and service of this complaint" Compl. ¶¶12, 22, 32, 42 The plaintiff requests a finding that the case is "exceptional" under 35 U.S.C. § 285, which would entitle it to attorneys' fees Compl. p. 16, ¶e

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: Can terms rooted in the patents' specific disclosed embodiments, such as "partition identifier" ('626 Patent) and "special purpose registers" ('870 Patent), be construed broadly enough to read on the distinct, and arguably more complex, architectural implementations found in modern Intel and AMD CPUs, such as virtual-APIC pages and Posted-Interrupt Descriptors?
• A second central question will be one of structural and functional mapping: Do the accused CPU features, which were developed independently over many years, actually operate in the same way as the patented inventions? For example, with respect to the '399 patent, does the standard operation of a MOESI cache-coherency protocol inherently perform the claimed method of processing "coherent and incoherent accesses" using a dedicated "mark," or is there a fundamental difference in the underlying technical mechanism that defeats the infringement allegation?
• A third key question will involve the doctrine of equivalents: If the court finds no literal infringement due to differences in structure and operation, the case may turn on whether the accused functionalities in Oracle's products perform substantially the same function, in substantially the same way, to achieve substantially the same result as the claimed inventions, particularly in the context of highly complex and standardized processor architectures.