Eireog Innovations Ltd v. Dell Tech Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Eireog Innovations Ltd. (Ireland)
  • Defendant: Dell Technologies Inc. and Dell Inc. (Delaware)
  • Plaintiff's Counsel: BC LAW GROUP, P.C.
• Case Identification: 1:24-cv-00416, W.D. Tex., 06/04/2024
• Venue Allegations: Venue is alleged to be proper based on Defendants having regular and established places of business in the Western District of Texas, including a principal place of business at One Dell Way, Round Rock, Texas.
• Core Dispute: Plaintiff alleges that a wide range of Defendant's computer products, which incorporate certain Intel and AMD processors, infringe five patents related to processor interrupt management, cache coherency, and power management.
• Technical Context: The technologies at issue concern fundamental aspects of modern multi-core processor architecture, focusing on enhancing performance and efficiency in virtualized environments and hybrid computing systems.
• Key Procedural History: The complaint is an amended complaint, filed following an original complaint on April 19, 2024. The complaint alleges that Defendants were put on notice of the asserted patents and their alleged infringement at least as of the date of the original complaint.

Case Timeline

Date	Event
2009-05-07	U.S. Patent No. 8,117,399 Priority Date
2010-09-21	U.S. Patent No. 8,504,777 Priority Date
2010-11-25	U.S. Patent No. 9,335,805 Priority Date
2012-02-14	U.S. Patent No. 8,117,399 Issued
2012-08-09	U.S. Patent No. 9,436,626 Priority Date
2012-08-09	U.S. Patent No. 9,442,870 Priority Date
2013-08-06	U.S. Patent No. 8,504,777 Issued
2016-05-10	U.S. Patent No. 9,335,805 Issued
2016-09-06	U.S. Patent No. 9,436,626 Issued
2016-09-13	U.S. Patent No. 9,442,870 Issued
2024-04-19	Original Complaint Filing Date
2024-06-04	Amended Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,436,626 - "Processor interrupt interface with interrupt partitioning and virtualization enhancements"

• Patent Identification: U.S. Patent No. 9,436,626, "Processor interrupt interface with interrupt partitioning and virtualization enhancements," issued September 6, 2016 Compl. ¶9

The Invention Explained

• Problem Addressed: In virtualized systems, interrupts intended for a guest operating system often require intervention by a hypervisor (or Virtual Machine Monitor), which introduces performance-degrading latency and software complexity '626 Patent, col. 2:27-39
• The Patented Solution: The invention describes a method where an "interrupt package" containing context information, including a "partition identifier," is sent directly to a processor '626 Patent, col. 2:27-33 The processor can then use this identifier to route the interrupt to the correct partition (e.g., a specific virtual machine) without hypervisor intervention by comparing the received partition ID against values stored in its own core registers '626 Patent, col. 2:33-39
• Technical Importance: This method of direct interrupt delivery was designed to reduce software overhead and improve interrupt response times in multi-core, virtualized computing environments.

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶11
• The essential elements of independent claim 1 include:
  • A method of managing interrupts at a processor, comprising receiving an "interrupt package" from an interrupt controller.
  • The interrupt package comprises a first interrupt request, an interrupt identifier, a partition identifier, a priority value, and a thread identifier.
  • The method further comprises processing the interrupt package by comparing the received priority value and partition identifier against a stored priority level and a stored partition identifier retrieved from special purpose registers at the processor.
  • This comparison is to determine on a partition basis if the first interrupt request is blocked or forwarded to a targeted thread.

U.S. Patent No. 9,442,870 - "Interrupt priority management using partition-based priority blocking processor registers"

• Patent Identification: U.S. Patent No. 9,442,870, "Interrupt priority management using partition-based priority blocking processor registers," issued September 13, 2016 Compl. ¶19

The Invention Explained

• Problem Addressed: Conventional interrupt management systems that place priority blocking logic at the interrupt controller create performance problems, as any changes to blocking conditions must be managed by software (e.g., a VMM), adding delay and complexity, particularly when an interrupt is targeted to an inactive partition '870 Patent, col. 3:40-58
• The Patented Solution: The patent describes moving the partitioned priority blocking mechanism from the interrupt controller to the processor core itself '870 Patent, abstract This is achieved by using "special purpose registers" at the processor to store priority levels and partition identifiers, allowing the processor to perform priority blocking quickly and efficiently without VMM intervention '870 Patent, col. 3:53-58
• Technical Importance: This architecture aims to reduce software overhead and improve interrupt response time in partitioned or virtualized multi-core systems.

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶21
• The essential elements of independent claim 1 include:
  • A method of managing interrupts at a processor, comprising receiving an interrupt package for a physical interrupt request.
  • The interrupt package comprises a first priority value and a first partition identifier.
  • The method further comprises processing the interrupt package against partitions running on targeted virtual processors by comparing the first priority value and first partition identifier against at least a stored priority level and stored partition identifier.
  • The stored values are retrieved from "one or more special purpose registers at the processor" to determine if the interrupt is blocked or forwarded to a virtual processor.

Multi-Patent Capsule: U.S. Patent No. 8,504,777 - "Data processor for processing decorated instructions with cache bypass"

• Patent Identification: U.S. Patent No. 8,504,777, "Data processor for processing decorated instructions with cache bypass," issued August 6, 2013 Compl. ¶29
• Technology Synopsis: The patent addresses the processing of "decorated instructions," which are instructions containing additional operational information. For decorated instructions that require a cache bypass, the invention specifies that a cache controller should invalidate the corresponding cache entry and provide the instruction to the system interconnect for direct handling by a memory controller '777 Patent, abstract
• Asserted Claims: At least independent claim 16 is asserted Compl. ¶31
• Accused Features: The accused functionality relates to how Dell products with certain Intel and AMD CPUs process instructions that bypass the processor cache Compl. ¶30

Multi-Patent Capsule: U.S. Patent No. 8,117,399 - "Processing of coherent and incoherent accesses at a uniform cache"

• Patent Identification: U.S. Patent No. 8,117,399, "Processing of coherent and incoherent accesses at a uniform cache," issued February 14, 2012 Compl. ¶39
• Technology Synopsis: The patent describes a method for managing a unified cache that stores both coherent (e.g., shared data) and incoherent (e.g., instruction code) information. Cache lines are marked as either coherent or incoherent. This system optimizes snooping by performing a full "global snoop" for a coherent read that misses on an incoherent line, but allows a less resource-intensive "non-global snoop" for an incoherent read miss, reducing interconnect traffic '399 Patent, abstract
• Asserted Claims: At least independent claim 14 is asserted Compl. ¶41
• Accused Features: The accused functionality concerns the cache coherency mechanisms in certain Intel and AMD CPUs used in Dell products Compl. ¶40

Multi-Patent Capsule: U.S. Patent No. 9,335,805 - "Method and apparatus for managing power in a multi-core processor"

• Patent Identification: U.S. Patent No. 9,335,805, "Method and apparatus for managing power in a multi-core processor," issued May 10, 2016 Compl. ¶49
• Technology Synopsis: The patent discloses a power management method for multi-core processors, particularly those with heterogeneous cores. The method involves determining the "leakage status" of cores and the "load uniformity status" of a workload, and then adapting core enablement and performance settings (e.g., frequency, voltage, parking) in response '805 Patent, abstract '805 Patent, claim 6
• Asserted Claims: At least independent claim 6 is asserted Compl. ¶51
• Accused Features: The accused functionality relates to power management features, such as Intel's Thread Director, in Dell products using 12th Generation Intel Core "Alder Lake" and newer hybrid architecture CPUs Compl. ¶50

III. The Accused Instrumentality

Product Identification

The complaint names an extensive list of "Accused Products," including Dell's PowerEdge Tower and Rack Servers, XE Servers, VxRail, PowerStore, PowerFlex, PowerVault, PowerMax, and various Desktops and Laptops from the XPS, Latitude, Inspiron, Alienware, and Precision lines Compl. ¶10 Compl. ¶20 Compl. ¶30 Compl. ¶40 Compl. ¶50

Functionality and Market Context

The core accused functionalities are not in the Dell products themselves, but in the processors they incorporate. The complaint targets Dell products containing specific generations of Intel CPUs (Haswell, Skylake, Alder Lake, and newer) and AMD CPUs (Zen-based) Compl. ¶10 Compl. ¶20 Compl. ¶30 Compl. ¶40 Compl. ¶50 The infringement allegations focus on the processors' internal architectures for handling virtualized interrupts, managing cache coherency, and implementing power-saving features in hybrid core designs. For example, the complaint alleges that Dell products with AMD EPYC processors use an Advanced Virtual Interrupt Controller (AVIC) and I/O Memory Management Unit (IOMMU) to deliver interrupts directly to virtual machines, allegedly practicing the '626 and '870 patents Compl. Ex. 2, p. 13 Compl. Ex. 10, p. 12 Exhibit 3, Figure 31, illustrates the data flow for a direct virtual interrupt delivery to a running VM, showing the roles of the IOMMU and logical processor core Compl. Ex. 3, p. 29 The accused products represent a substantial portion of Dell's enterprise and consumer offerings, indicating significant commercial scale.

IV. Analysis of Infringement Allegations

9,436,626 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
receiving at the processor an interrupt package... where the interrupt package comprises a first interrupt request, an interrupt identifier..., a partition identifier..., a priority value..., and a thread identifier...	The accused processors receive interrupt messages via the Advanced Programmable Interrupt Controller (APIC). These messages allegedly contain an interrupt request, an "Interrupt Vector" (identifier and priority), a destination that maps to a virtual machine (partition), and a destination APIC ID (thread).	¶11	col. 2:27-39
processing the interrupt package... by comparing the priority value and partition identifier against at least a stored priority level and stored partition identifier retrieved from special purpose registers at the processor to determine... if the first interrupt request is blocked or forwarded to a targeted thread...	The accused Intel processors allegedly use a Virtual Processor Priority Register (VPPR) as a stored priority level. An incoming virtual interrupt is allegedly only delivered if its priority exceeds the VPPR value, and delivery depends on whether the target virtual machine is currently running (the partition).	¶11	col. 2:33-44

• Identified Points of Contention:
  • Scope Question: A potential dispute may arise over whether the combination of information fields in an interrupt message (e.g., vector, destination) as processed by the accused APIC and IOMMU constitutes a single "interrupt package" as required by the claim.
  • Technical Question: The claim requires processing by comparing both a priority value and a partition identifier against stored counterparts. A question for the court is whether the accused products perform this specific two-factor comparison, or if they use a different logic (e.g., checking partition status and priority in separate, distinct steps) that may fall outside the claim scope.

9,442,870 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
receiving at the processor an interrupt package for a first physical interrupt request, where the interrupt package comprises a first priority value and a first partition identifier...	The accused processors receive interrupt messages which allegedly contain a priority value (in the Interrupt Vector field) and are associated with a specific virtual machine (the partition).	¶21	col. 1:12-17
processing the interrupt package against one or more partitions... by comparing the first priority value and first partition identifier against at least a stored priority level and stored partition identifier retrieved from one or more special purpose registers at the processor to determine... if the first physical interrupt request is blocked or forwarded to a targeted virtual processor.	The accused processors allegedly use on-core registers to manage interrupt priority for virtual machines. For AMD, this is the virtual Task Priority Register (V_TPR); for Intel, this is the Virtual Processor Priority Register (VPPR). These are alleged to be the claimed "special purpose registers" used for comparing priority to block or forward interrupts.	¶21	col. 3:53-58

• Identified Points of Contention:
  • Scope Question: A central issue will be whether the accused V_TPR and VPPR registers in AMD and Intel processors, respectively, meet the definition of "special purpose registers at the processor" for the purpose of "partition-based priority blocking" as described in the patent.
  • Technical Question: It may be disputed whether the accused processors' logic for handling virtual interrupts constitutes "processing the interrupt package... by comparing the first priority value and first partition identifier." Evidence will be needed to show that both the priority and partition are used in the comparison against stored values in the manner required by the claim.

V. Key Claim Terms for Construction

'626 Patent: "interrupt package"

• The Term: "interrupt package"
• Context and Importance: This term defines the bundle of information that is the subject of the claimed method. The infringement case hinges on whether the various pieces of data conveyed to the accused processors (e.g., interrupt vector, destination ID) collectively constitute an "interrupt package." Practitioners may focus on this term because its construction will determine if the infringement theory, which aggregates information from different hardware signals and registers, is viable.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the processor receiving "interrupt context information," which includes an "interrupt ID, partition ID, thread ID, priority level, and additional interrupt message data" '626 Patent, col. 2:29-33 This language suggests a functional collection of information rather than a rigidly defined data structure.
  • Evidence for a Narrower Interpretation: The claim recites that the "interrupt package comprises" a list of five specific identifiers. A defendant may argue this requires a single, discrete data structure containing all five elements, which may not align with how the accused processors receive disparate interrupt-related signals from the APIC and IOMMU.

'870 Patent: "special purpose registers at the processor"

• The Term: "special purpose registers at the processor"
• Context and Importance: The point of novelty of the '870 patent is moving the priority blocking logic to registers on the processor core. The case depends on whether registers like Intel's VPPR or AMD's V_TPR are considered "special purpose registers" for this claimed function.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent abstract states the invention provides "a partitioned priority blocking mechanism... in special purpose registers... located at the processor core" to enable "quick and efficient interrupt priority blocking" '870 Patent, abstract This purpose-driven description could support a broad definition covering any on-core register that achieves this function.
  • Evidence for a Narrower Interpretation: The specification contrasts the invention with the prior art "interrupt priority blocking register 5 at the interrupt controller 2" '870 Patent, col. 3:41-43 A defendant could argue the claimed registers must be a direct, one-to-one functional replacement for that specific prior art component, and that the accused registers (VPPR, V_TPR) are part of a more complex virtualization system that operates differently.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement, stating that Dell provides user manuals and online instructions that encourage customers to use the Accused Products in ways that directly infringe the asserted patents Compl. ¶13 Compl. ¶23 Compl. ¶33 Compl. ¶43 Compl. ¶53 It is also alleged that Dell's marketing materials advertising the benefits of the accused Intel and AMD processors constitute inducement Compl. ¶13
• Willful Infringement: Willfulness is alleged based on Dell's continued infringement after receiving notice of the patents and infringement allegations. The complaint specifies that Dell gained knowledge "at least as of the filing and service of the original complaint on April 19, 2024," with which claim charts were served Compl. ¶13 Compl. ¶23 Compl. ¶33 Compl. ¶43 Compl. ¶53

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: Can terms rooted in the patent's specific embodiments, such as "interrupt package" ('626 Patent) and "decorated access instruction" ('777 Patent), be construed to read on the complex, multifaceted hardware-software interactions within modern CPU architectures, or is there a fundamental mismatch in structure and operation?
• A key technical question will be one of locus of control: For the '805 patent concerning power management, does the accused system, which relies on coordination between the CPU's Intel Thread Director and the OS's scheduler, practice the claimed method "at a processor," or is the decision-making so distributed or controlled by the OS that the processor itself cannot be said to perform the claimed steps of "determining" statuses and "setting" performance states?
• An evidentiary question will center on operational equivalence: Does the accused processors' use of on-core registers like VPPR and V_TPR for managing virtual interrupts function in the same way as the "partition-based priority blocking" mechanism described in the '870 patent, or do these features operate in a materially different manner as part of a broader, non-infringing virtualization system?