DCT

1:24-cv-00254

Vervain LLC v. Kingston Technology Co Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: Vervain, LLC v. Kingston Technology Co., Inc., 1:24-cv-00254, W.D. Tex., 05/10/2024
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendants have committed acts of infringement in the district and maintain a regular and established place of business, including an office in Round Rock, TX, and an Austin-based employee who serves local customers.
  • Core Dispute: Plaintiff alleges that Defendants' flash memory products, including solid-state drives (SSDs), infringe a portfolio of eight related patents directed to methods for managing data between multi-level cell (MLC) and single-level cell (SLC) memory to improve device lifetime and performance.
  • Technical Context: The technology at issue addresses hybrid flash memory management, a foundational technique in modern SSDs for balancing the cost-effectiveness of high-density memory (like MLC/TLC/QLC) with the superior speed and endurance of SLC memory.
  • Key Procedural History: The complaint notes that in prior litigation, Kingston declined to dispute that venue was proper in the Western District of Texas. The asserted patents are part of a large family, and the Plaintiff notes it has pending continuations to the patents-in-suit.

Case Timeline

Date Event
2011-07-19 Earliest Priority Date for all Asserted Patents
2014-11-18 U.S. Patent No. 8,891,298 Issued
2015-11-24 U.S. Patent No. 9,196,385 Issued
2018-06-12 U.S. Patent No. 9,997,240 Issued
2021-03-16 U.S. Patent No. 10,950,300 Issued
2023-11-28 U.S. Patent No. 11,830,546 Issued
2023-12-26 U.S. Patent No. 11,854,612 Issued
2024-04-23 U.S. Patent No. 11,967,369 Issued
2024-04-23 U.S. Patent No. 11,967,370 Issued
2024-05-10 First Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,891,298 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Patent Identification: U.S. Patent No. 8,891,298, "Lifetime Mixed Level Non-Volatile Memory System," issued November 18, 2014 (the "'298 Patent").

The Invention Explained

  • Problem Addressed: The patent's background describes the trade-offs in non-volatile memory: cheaper, high-density multi-level cell (MLC) NAND flash has a significantly shorter operational lifetime (i.e., fewer write-erase cycles) than more expensive, higher-performance single-level cell (SLC) NAND flash ʼ298 Patent, col. 2:25-41 Using MLC exclusively can lead to premature device failure, while using SLC exclusively is cost-prohibitive for mass storage.
  • The Patented Solution: The patent discloses a memory system with both MLC and SLC modules managed by a controller ʼ298 Patent, abstract The controller is designed to enhance the system's overall lifetime by intelligently moving data. It remaps data from a block in the MLC module to the more durable SLC module if a data integrity test fails ʼ298 Patent, FIG. 2b It also proactively identifies and transfers the most frequently written data blocks to the SLC module to reduce wear on the MLC memory ʼ298 Patent, col. 5:1-12
  • Technical Importance: This hybrid management strategy enabled the widespread adoption of cost-effective MLC flash in consumer and enterprise SSDs by mitigating its primary drawback of limited endurance Compl. ¶49

Key Claims at a Glance

  • The complaint asserts independent claim 1 Compl. ¶61
  • The essential elements of claim 1 include:
    • A system with at least one MLC non-volatile memory module and at least one SLC non-volatile memory module.
    • A controller coupled to both modules.
    • The controller is adapted to:
      • (a) maintain an address map for the modules.
      • (b) determine if a data range in the MLC module fails a data integrity test and, upon failure, remap that data to the SLC module.
      • (c) determine which blocks are most frequently accessed by maintaining a count.
      • (d) allocate the most frequently written blocks by transferring their contents to the SLC module.
  • The complaint reserves the right to identify additional infringing activities, which may include assertion of other claims Compl. ¶60

U.S. Patent No. 9,196,385 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Patent Identification: U.S. Patent No. 9,196,385, "Lifetime Mixed Level Non-Volatile Memory System," issued November 24, 2015 (the "'385 Patent").

The Invention Explained

  • Problem Addressed: The patent addresses the same problem as the ʼ298 Patent: managing the trade-off between cost, performance, and endurance in systems using both MLC and SLC flash memory ʼ385 Patent, col. 2:32-48
  • The Patented Solution: The ʼ385 Patent claims a system similar to that of the ʼ298 Patent but explicitly identifies a "flash translation layer (FTL)" as the component adapted to perform the core data management functions ʼ385 Patent, claim 1 The FTL, a standard software or firmware layer in SSD controllers, is tasked with maintaining the address map, remapping data upon integrity test failures, and allocating frequently written blocks to the SLC module ʼ385 Patent, col. 3:5-15
  • Technical Importance: By explicitly naming the FTL, the invention anchors the claimed functionality within a well-defined architectural component of modern SSDs, clarifying the implementation context of the memory management method Compl. ¶100

Key Claims at a Glance

  • The complaint asserts independent claim 1 Compl. ¶96
  • The essential elements of claim 1 include:
    • A system with at least one MLC and one SLC non-volatile memory module.
    • A flash translation layer (FTL).
    • The FTL is adapted to perform the same four functions as the controller in claim 1 of the ʼ298 Patent: (a) maintain an address map, (b) remap data from MLC to SLC on a data integrity test failure, (c) determine frequently accessed blocks via a count, and (d) allocate frequently written blocks to the SLC module.
  • The complaint reserves the right to assert other claims Compl. ¶95

U.S. Patent No. 9,997,240 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Patent Identification: U.S. Patent No. 9,997,240 (the "'240 Patent"), "Lifetime Mixed Level Non-Volatile Memory System," issued June 12, 2018 Compl. ¶31
  • Technology Synopsis: The ʼ240 Patent refines the memory management concept by introducing the terms "hot blocks" for frequently written data allocated to the SLC module and "cold blocks" for infrequently written data in the MLC module. It claims a controller that allocates blocks based on this classification and periodically transfers "counted blocks" that reach a predetermined access count to the SLC module ʼ240 Patent, abstract
  • Asserted Claims: At least claim 6 Compl. ¶110
  • Accused Features: The complaint alleges that the Accused Products' controllers allocate frequently written blocks to SLC and move infrequently written data to MLC through various procedures Compl. ¶115

U.S. Patent No. 10,950,300 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Patent Identification: U.S. Patent No. 10,950,300 (the "'300 Patent"), "Lifetime Mixed Level Non-Volatile Memory System," issued March 16, 2021 Compl. ¶32
  • Technology Synopsis: The ʼ300 Patent introduces the use of volatile memory (e.g., RAM) into the data integrity test process. It describes a controller that, during a write operation to MLC, retains a copy of the data in RAM. The controller then performs a data integrity test by comparing the data stored in the MLC element to the data retained in RAM ʼ300 Patent, abstract ʼ300 Patent, col. 8:36-47
  • Asserted Claims: At least claim 1 Compl. ¶123
  • Accused Features: The complaint alleges the Accused Products' controllers use RAM (DRAM/SRAM) to cache data and perform data integrity tests by comparing data stored in flash with data retained in RAM Compl. ¶¶129, 131, 132

U.S. Patent No. 11,830,546 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Patent Identification: U.S. Patent No. 11,830,546 (the "'546 Patent"), "Lifetime Mixed Level Non-Volatile Memory System," issued November 28, 2023 Compl. ¶33
  • Technology Synopsis: The ʼ546 Patent is similar to the ʼ300 Patent, further detailing the role of memory within the controller. It claims a controller with "associated controller memory" that stores received data, transfers it to MLC memory, retains a copy in random access memory, and then performs a data integrity test by reading the stored data back to the controller memory for comparison with the retained data ʼ546 Patent, abstract
  • Asserted Claims: At least claim 1 Compl. ¶140
  • Accused Features: The complaint alleges the Accused Products have controllers with associated memory (buffers, caches) that cache written data in RAM and perform integrity tests by comparing stored and retained data Compl. ¶¶147-148

U.S. Patent No. 11,854,612 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Patent Identification: U.S. Patent No. 11,854,612 (the "'612 Patent"), "Lifetime Mixed Level Non-Volatile Memory System," issued December 26, 2023 Compl. ¶34
  • Technology Synopsis: The ʼ612 Patent claims a method for storing data that mirrors the system claims of the predecessor patents, particularly the ʼ546 Patent. The method includes steps of maintaining an address table, controlling memory access, storing received data in controller memory, transferring it to MLC, retaining it in RAM, and performing a detailed, multi-step data integrity test involving reading and comparing data ʼ612 Patent, abstract
  • Asserted Claims: At least claim 1 Compl. ¶156
  • Accused Features: The complaint alleges that when used by Kingston or its customers, the Accused Products perform the claimed method steps for storing data, including using controller memory and RAM for data integrity checks Compl. ¶¶157, 161, 165

U.S. Patent No. 11,967,369 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Patent Identification: U.S. Patent No. 11,967,369 (the "'369 Patent"), "Lifetime Mixed Level Non-Volatile Memory System," issued April 23, 2024 Compl. ¶35
  • Technology Synopsis: The ʼ369 Patent introduces an explicit distinction between "logical and physical" memory spaces. It claims a system where memory elements have physical addresses that are mapped to logical addresses, and the controller manages data transfer and integrity testing between these physical and logical spaces ʼ369 Patent, abstract
  • Asserted Claims: At least claim 1 Compl. ¶175
  • Accused Features: The complaint alleges the Accused Products use both logical memory mappings (e.g., logical block numbers) and physical memory space to manage data, and that their flash translation layers map logical to physical addresses Compl. ¶¶177, 180, 186

U.S. Patent No. 11,967,370 - "Lifetime Mixed Level Non-Volatile Memory System"

  • Patent Identification: U.S. Patent No. 11,967,370 (the "'370 Patent"), "Lifetime Mixed Level Non-Volatile Memory System," issued April 23, 2024 Compl. ¶36
  • Technology Synopsis: The ʼ370 Patent claims a system very similar to the ʼ298 Patent. It describes a controller that maintains an address map and is adapted to perform a data integrity test on data in the MLC element, remapping the entry and transferring the data to the SLC element upon failure ʼ370 Patent, abstract
  • Asserted Claims: At least claim 1 Compl. ¶198
  • Accused Features: The complaint alleges the Accused Products' controllers maintain an address map (e.g., L2P table) and incorporate defect and error management to remap degraded data from MLC to SLC locations upon a data integrity failure Compl. ¶¶203, 207-208

III. The Accused Instrumentality

Product Identification

  • The complaint identifies a wide range of Kingston's flash memory products as the "Accused Products." These include, but are not limited to, solid-state drives (SSDs) such as the XS2000, DC1500M, NV2, and FURY Renegade; USB flash drives; memory cards; and embedded flash products Compl. ¶¶9, 53-54

Functionality and Market Context

  • The Accused Products are managed by controller chips, many of which are sourced from third parties like Phison and Silicon Motion Compl. ¶9 Compl. ¶53 The complaint alleges these controllers implement sophisticated data management techniques to balance performance, cost, and reliability. This includes using "SLC Caching" or "Direct-to-TLC" systems, where a portion of denser memory (like TLC) is operated in a faster, more durable SLC mode to serve as a buffer or cache Compl. ¶12 Compl. ¶63 The complaint also points to specific controller technologies like Phison's "SmartRefresh" and Silicon Motion's "IntelligentScan & DataRefresh" as performing the data integrity and management functions described in the patents Compl. ¶74 Compl. ¶78 The complaint cites a diagram of a Phison "SLC buffer" to illustrate this functionality Compl. p. 18, Ex. Z
  • Kingston is positioned as a "world leader in memory products" and the "number-one third-party supplier of branded SSD modules," indicating the commercial significance of the Accused Products Compl. ¶8

IV. Analysis of Infringement Allegations

'298 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A system for storing data comprising: at least one MLC non-volatile memory module...; at least one SLC non-volatile memory module... The Accused Products are flash storage systems that include both MLC memory (or denser variants like TLC/QLC) and utilize SLC memory, often through an "SLC Caching" or "SLC buffer" system. ¶¶62-65 col. 4:50-54
a controller coupled to the at least one MLC non-volatile memory module and the at least one SLC non-volatile memory module... The Accused Products contain controllers, such as those from Phison and Silicon Motion, that are coupled to and manage the flash memory modules. ¶66 col. 4:55-57
a) maintain an address map of at least one of the MLC and SLC non-volatile memory modules... The controllers in the Accused Products use a mapping table, such as a logical-to-physical (L2P) table, to manage the relationship between logical addresses and the physical locations of data in the flash memory. A diagram shows the L2P table as part of the cache operating mechanism Compl. p. 21, Ex. CC ¶¶67-72 col. 5:29-41
b) determine if a range of addresses... within the at least one MLC non-volatile memory module, fails a data integrity test, and, in the event of such a failure, the controller remaps the entry to the next available equivalent range of physical addresses within the at least one SLC non-volatile memory module; The accused controllers allegedly incorporate defect and error management technology, such as Phison's "SmartRefresh," which checks for error bits and performs specific actions on failed blocks. Upon failure, data is remapped to a new location, which the complaint alleges can be in the SLC module. ¶¶73-80 col. 4:58-67
c) determine which of the blocks... are accessed most frequently by maintaining a count of the number of times each one of the blocks is accessed; and The accused controllers allegedly employ block counting, using data such as program/erase (P/E) counts and valid page counts, to determine block access frequency as part of wear-leveling and other management functions. ¶¶81-83 col. 5:1-6
d) allocate those blocks that receive the most frequent writes by transferring the respective contents of those blocks to the at least one SLC non-volatile memory module. The accused controllers allegedly use a "count balance scheme" and other garbage collection or wear-leveling techniques to transfer frequently accessed or "hot" data blocks to SLC NAND to improve performance and endurance. ¶¶84-90 col. 5:7-12

'385 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A system for storing data comprising: at least one MLC non-volatile memory module...; at least one SLC non-volatile memory module... As alleged for the '298 Patent, the Accused Products are systems containing both MLC-type and SLC-type memory. ¶¶97-99 col. 5:35-39
a flash translation layer (FTL); wherein the FTL is adapted to: The Accused Products' controllers include an FTL, which the complaint alleges performs the claimed data management functions. The complaint provides a visual of a Phison FTL Compl. p. 42, Ex. II ¶100 col. 5:40
a) maintain an address map... The FTL is alleged to provide mapping between logical and physical addresses using a data structure like an L2P table. ¶101 col. 6:32-43
b) determine if a range of addresses... fails a data integrity test, and... remaps the entry to the... SLC non-volatile memory module; The FTL is alleged to perform data integrity functions and remap data to SLC memory upon failure of a data integrity test. ¶102 col. 6:44-52
c) determine which of the blocks... are accessed most frequently by maintaining a count...; and The FTL is alleged to use block counting mechanisms. ¶103 col. 6:53-58
d) allocate those blocks that receive the most frequent writes by transferring the respective contents... to the... SLC non-volatile memory module. The FTL is alleged to transfer frequently written blocks to SLC memory. ¶104 col. 6:59-64

Identified Points of Contention

  • Scope Questions: A central question may be whether the patent term "SLC non-volatile memory module" can be interpreted to cover the accused "SLC Caching" or "SLC mode" functionality, where a portion of an MLC or TLC NAND chip is dynamically configured to operate as SLC, as opposed to being a physically distinct SLC chip as depicted in the patent figures ʼ298 Patent, FIG. 1 ʼ298 Patent, FIG. 4 Another scope question is whether "MLC non-volatile memory module" reads on the TLC and QLC memory used in many of the Accused Products Compl. ¶12
  • Technical Questions: The infringement analysis will likely scrutinize the specific nature of the "data integrity test" (Compl. ¶73). The court may need to determine whether the general-purpose error checking, ECC, and background media scan functions ("SmartRefresh") of the accused controllers perform the specific test-and-remap function required by the claims, or if there is a functional mismatch.

V. Key Claim Terms for Construction

The Term: "fails a data integrity test"

  • Context and Importance: This term is the trigger for the remapping function in element (b) of the asserted claims. Its construction is critical because it defines what kind of "failure" obligates the controller to move data from MLC to SLC.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The abstract and high-level summaries of the patents refer generally to performing a "data integrity check" or "test" without specifying the mechanism ʼ298 Patent, abstract This may support an interpretation that covers any process that detects data errors, such as the accused "SmartRefresh" feature that checks error bits Compl. ¶74
    • Evidence for a Narrower Interpretation: The patent flowcharts depict a specific sequence where data is written to NAND, read back into the controller, and then compared to verify the write was successful ʼ298 Patent, FIG. 3b, steps 110, 112, 114 This may support a narrower construction requiring a specific post-write verification step, potentially excluding routine background media scans or standard on-read error correction.

The Term: "SLC non-volatile memory module"

  • Context and Importance: The definition of this term is fundamental to the infringement case, as the claims require remapping and transferring data to this module. The dispute will question whether a dynamically configured portion of an MLC/TLC chip acting as an SLC cache constitutes an "SLC... module".
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the function of the SLC memory in terms of its superior endurance and speed relative to MLC memory ʼ298 Patent, col. 2:25-41 This functional description could support reading the term on any memory that serves that role, regardless of its physical implementation.
    • Evidence for a Narrower Interpretation: The patent's block diagrams consistently depict the "MLC flash" and "SLC flash" as distinct, separate boxes connected to the device controller, suggesting they are structurally separate components ʼ298 Patent, FIG. 1 ʼ298 Patent, FIG. 4 This could support an argument that the term requires a physically separate chip and does not cover an operating mode of an MLC chip.

VI. Other Allegations

Indirect Infringement

  • The complaint does not contain explicit counts for indirect infringement. However, it lays a potential foundation by alleging that Kingston's Accused Products are "essential, non-trivial components" integrated into downstream devices and that Kingston's "development, sales, marketing, and manufacturing activities" contribute to infringement in the United States Compl. ¶55 Compl. ¶58

Willful Infringement

  • The complaint does not use the term "willful infringement." It does, however, plead that this is an "exceptional case" and seeks attorneys' fees under 35 U.S.C. § 285 for each asserted patent Compl. ¶93 Compl. ¶107 Such a finding often involves conduct rising to the level of willfulness or other litigation misconduct. The complaint does not allege pre-suit knowledge of the patents; the filing of the complaint itself provides notice for any infringement occurring thereafter.

VII. Analyst's Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can the patent term "SLC non-volatile memory module", depicted in the patents as a physically separate unit, be construed to cover the accused "SLC caching" feature, where a controller dynamically configures a portion of a denser memory chip (e.g., TLC) to emulate SLC behavior? The resolution of this question may determine whether the fundamental architecture of the accused devices falls within the scope of the claims.
  • A second key issue will be one of functional interpretation: does the claimed "data integrity test" require a specific, post-write verification process as shown in the patent's flowcharts, or can it be interpreted more broadly to include general error detection and background media-scanning functions like Phison's "SmartRefresh," as alleged in the complaint?
  • Finally, the case may turn on an evidentiary question of operational linkage: can the plaintiff demonstrate that the accused controllers perform the specific, ordered sequence of claim steps-namely, that a failure of a data integrity test on an MLC block specifically causes the system to remap and transfer that block's data to the SLC module, as opposed to these being disconnected functions within a general wear-leveling or error management scheme?
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