VLSI Technology LLC v. Intel Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: VLSI Technology LLC (Delaware)
  • Defendant: Intel Corporation (Delaware)
  • Plaintiff's Counsel: Mann | Tindel | Thompson
• Case Name: VLSI Technology LLC v. Intel Corporation
• Case Identification: 6:19-cv-254, W.D. Tex., 04/11/2019
• Venue Allegations: Venue is based on Defendant Intel maintaining a regular and established place of business within the Western District of Texas and having committed alleged acts of infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant's Ivy Bridge and Skylake families of microprocessors infringe three patents related to dynamic voltage/frequency scaling and power management.
• Technical Context: The technology concerns methods for managing power consumption and performance in complex integrated circuits, a critical aspect of modern processor design for devices ranging from mobile phones to data centers.
• Key Procedural History: The complaint alleges that Intel had notice of U.S. Patent No. 7,725,759 from a prior lawsuit filed in the District of Delaware on March 1, 2019. The complaint also cites Intel's alleged corporate policy of not reviewing third-party patents and prior litigation involving patents from NXP (the patents' original assignee) with overlapping inventors to support allegations of willful infringement.

Case Timeline

Date	Event
2005-06-29	U.S. Patent No. 7,725,759 Priority Date
2006-08-30	U.S. Patent No. 7,523,373 Priority Date
2009-01-27	U.S. Patent No. 8,156,357 Priority Date
2009-04-21	U.S. Patent No. 7,523,373 Issue Date
2010-05-25	U.S. Patent No. 7,725,759 Issue Date
2012-04-10	U.S. Patent No. 8,156,357 Issue Date
2019-03-01	Filing of Delaware Complaint asserting U.S. Patent No. 7,725,759
2019-04-11	Complaint Filing Date (W.D. Tex.)

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,156,357 - "Voltage-based memory size scaling in a data processing system"

• Patent Identification: U.S. Patent No. 8,156,357, "Voltage-based memory size scaling in a data processing system," issued April 10, 2012 Compl. ¶8

The Invention Explained

• Problem Addressed: The patent's background describes that setting a single, fixed minimum operating voltage (Vmin) for a memory system can be inefficient. This is because operating at lower voltages to save power may render the entire memory non-functional, even if large portions could still operate reliably at that lower voltage Compl. ¶12 '357 Patent, col. 1:48-53
• The Patented Solution: The invention proposes a method to dynamically scale the effective size of a memory, such as a cache, based on the operating voltage. At a lower voltage, portions of the memory (e.g., specific cache "ways") that are known to become unreliable are identified and deactivated. The system continues to operate using the remaining, smaller, but functional portion of the memory. When the voltage is increased, the deactivated portions can be brought back online, restoring full memory size '357 Patent, abstract '357 Patent, col. 1:53-66
• Technical Importance: This approach allows a processor to operate at lower average voltages, enhancing power efficiency beyond what is possible with a fixed-size memory architecture Compl. ¶13

Key Claims at a Glance

• The complaint asserts independent Claim 1 Compl. ¶15
• The essential elements of Claim 1 are:
  • A method of using a cache with multiple ways.
  • Accessing the cache at a first power supply voltage.
  • Reducing the voltage to a second, lower value.
  • Identifying a subset of ways as non-functional at the second voltage by "retrieving information that correlates non-functional ways...with values of the power supply voltage."
  • Accessing the cache exclusive of the identified non-functional ways while at the second voltage.
  • Increasing the voltage to a third value.
  • Identifying a set of ways that are now functional at the third value.
  • Accessing the cache including the newly functional ways.
• The complaint does not explicitly reserve the right to assert dependent claims of the '357 Patent.

U.S. Patent No. 7,523,373 - "Minimum memory operating voltage technique"

• Patent Identification: U.S. Patent No. 7,523,373, "Minimum memory operating voltage technique," issued April 21, 2009 Compl. ¶37

The Invention Explained

• Problem Addressed: Due to manufacturing variations, the true minimum operating voltage of a memory can differ from one integrated circuit (IC) to another. Using a single conservative Vmin for an entire product line prevents individual ICs that are more robust from operating at their lowest possible voltage, sacrificing potential power savings '373 Patent, col. 2:17-27 Compl. ¶41
• The Patented Solution: The patent describes a method where each IC is tested during manufacturing to determine the specific minimum operating voltage for its memory. This unique value is then stored permanently on the IC itself in a non-volatile location, such as a register or fuse. This on-chip information can then be used by the IC's power management controller to make more precise, part-specific decisions about operating voltages and power states '373 Patent, abstract '373 Patent, col. 2:27-37 Compl. ¶42
• Technical Importance: This technique enables per-chip power optimization, allowing each device to operate closer to its actual physical limits rather than being constrained by worst-case assumptions for a product family '373 Patent, col. 2:27-32

Key Claims at a Glance

• The complaint asserts independent Claim 16 Compl. ¶44
• The essential elements of Claim 16 are:
  • A method involving an IC with a memory and a separate "functional circuit."
  • Testing the memory to determine its minimum operating voltage.
  • Storing this value in a non-volatile manner.
  • Providing a first regulated voltage to the functional circuit and a second, greater regulated voltage.
  • When the first voltage is at or above the minimum operating voltage, it is provided to the memory.
  • When the first voltage is below the minimum, the second voltage is provided to the memory while the first voltage is provided to the functional circuit.
• The complaint does not explicitly reserve the right to assert dependent claims of the '373 Patent.

U.S. Patent No. 7,725,759 - "System and method of managing clock speed in an electronic device"

• Patent Identification: U.S. Patent No. 7,725,759, "System and method of managing clock speed in an electronic device," issued May 25, 2010 Compl. ¶69

Technology Synopsis

The patent addresses the need for an improved method of controlling clock frequency to balance performance and power consumption Compl. ¶73 The invention describes monitoring multiple "master devices" (e.g., processor cores) on a bus. When a first master device requests a change in clock speed in response to a change in its own performance (e.g., workload), the system provides that new clock frequency to a second master device and the bus itself, coordinating performance across the system Compl. ¶74 Compl. ¶81 Compl. ¶85

Asserted Claims

Independent Claim 1 Compl. ¶76

Accused Features

The complaint accuses Intel's "Hardware-Controlled Performance States ('HWP' or 'Speed Shift')" technology, as implemented in Intel Skylake and subsequent processors, of infringement Compl. ¶75 Compl. ¶77

III. The Accused Instrumentality

Product Identification

The complaint identifies "Intel Ivy Bridge processors" as infringing the '357 and '373 patents and "Intel Skylake processors" as infringing the '759 Patent Compl. ¶14 Compl. ¶43 Compl. ¶75

Functionality and Market Context

• The accused products are central processing units (CPUs) from a leading global manufacturer. The allegedly infringing features relate to core power and performance management technologies.
• For the '357 Patent, the accused functionality is the "Dynamic Cache Shrink Feature" in Ivy Bridge processors. The complaint alleges this feature deactivates a portion of the processor's last-level cache (shrinking from 16 active "ways" to 2) during periods of low activity to enable operation at a lower voltage, and reactivates them when high activity is detected Compl. ¶17 Compl. ¶22 Compl. ¶27 An Intel presentation slide is provided as evidence, showing the reduction from 16 ways to 2 ways during a "Sleep" state Compl. p.5
• For the '373 Patent, the allegations focus on how Ivy Bridge processors manage power. The complaint alleges that information correlating minimum operating voltage (Vmin) with cache size is stored in a non-volatile manner Compl. ¶47 It further alleges the processors use a dual-voltage system where the processor "Core" (the "functional circuit") and the "LLC" cache (the "memory") are on separate power planes, allowing the core voltage to be reduced while the cache voltage is maintained from a different rail Compl. ¶50 Compl. ¶56-57 This is supported by a slide depicting "Ivy Bridge Power Planes" with a "Gated" core and "Ungated" LLC Compl. p.17
• For the '759 Patent, the accused functionality is Intel's "Speed Shift" (or HWP) technology. The complaint alleges that in Skylake processors, individual cores monitor their own workload and, upon detecting a predefined change, signal a request to the "Package Control Unit" (PCU) to change the operating frequency (P-state). The PCU then sets this frequency for other cores on the shared bus Compl. ¶79 Compl. ¶82 Compl. ¶86

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,156,357 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A method of using a cache having a plurality of ways...	Intel Ivy Bridge processors use a cache organized in a plurality of ways (e.g., 16 ways). A slide shows a cache organized in 16 ways Compl. p.5	¶16	col. 3:5-10
accessing the cache with a power supply voltage applied to the cache at a first value; reducing the power supply voltage to a second value;	The Ivy Bridge processor has a nominal operating voltage and its "Dynamic Cache Shrink Feature" is capable of reducing the power supply by 30 mV to a second, reduced voltage.	¶18; ¶19	col. 2:1-4
identifying a first set of ways...as being non-functional...wherein the step of identifying...comprises: retrieving information that correlates non-functional ways of the cache with values of the power supply voltage;	The processor identifies a set of ways as non-functional at the reduced voltage. This identification is alleged to be based on retrieving stored information that correlates cache size (and thus ways) with Vmin benefit, as shown in a chart Compl. p.6	¶20	col. 4:25-48
accessing the cache exclusive of the first set of ways, wherein the step of accessing...is performed with the power supply voltage at the second value;	When the cache is shrunk, the processor operates using only the active ways (e.g., 2 of 16) at the reduced voltage. The ways that were put to sleep are not accessed Compl. p.8	¶24; ¶25	col. 7:1-4
increasing the power supply voltage to a third value; identifying a second set of ways...that is functional with the power supply being applied at the third value; and accessing the cache including the second set of ways.	When the PCU detects high activity, the processor returns to normal operation by "expanding active ways back to 16," which are functional at the nominal (third) voltage, and accessing the full cache Compl. p.10	¶26; ¶27	col. 7:41-52

• Identified Points of Contention:
  • Scope Question: A central dispute may be the meaning of "retrieving information." The complaint alleges infringement by pointing to a graph showing a correlation between Vmin and cache size Compl. ¶20 Compl. p.6 The court will have to determine whether the accused product's mechanism for disabling ways constitutes "retrieving" pre-characterized, stored data as described in the patent specification '357 Patent, col. 4:25-28, or if it uses a real-time calculation or other method that falls outside this claim language.
  • Technical Question: What evidence demonstrates that the accused processor identifies ways as "non-functional" because of the voltage drop, as the claim requires, rather than simply deactivating them as a power-saving policy irrespective of their actual functionality at that voltage?

U.S. Patent No. 7,523,373 Infringement Allegations

Claim Element (from Independent Claim 16)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
providing an integrated circuit with a memory...; testing the memory to determine...a minimum operating voltage; storing, in a non-volatile manner, the value of the minimum operating voltage;	Ivy Bridge processors allegedly store the minimum operating voltage for different last-level cache configurations in a non-volatile manner, accessible after reboots. The complaint uses a chart showing "Vmin Benefit with Cache Size" as evidence of this stored value Compl. p.15	¶46; ¶47	col. 2:27-35
providing a functional circuit on the integrated circuit exclusive of the memory;	The Ivy Bridge processor allegedly includes cores ("functional circuit") that are exclusive of the last-level cache (LLC) memory ("memory"). This is supported by a "Power Planes" diagram showing the core and LLC as distinct blocks Compl. p.17	¶49; ¶50	col. 6:20-21
providing a first regulated voltage to the functional circuit; providing a second regulated voltage, wherein the second regulated voltage is greater than the first regulated voltage;	The core is powered by a "gated" power plane (first voltage), while the processor is powered by a "core power rail," VCC (second voltage), which is greater. The core voltage can be reduced below the VCC level.	¶51; ¶52; ¶53; ¶54	col. 8:50-52
providing the first regulated voltage as the operating voltage of the memory when the first regulated voltage is at least the value of the minimum operating voltage;	When the core voltage (first voltage) is above the memory's minimum operating voltage, the on-chip power gate is fully open, making the core voltage and VCC (second voltage) the same. The complaint alleges the first voltage is thus provided to the memory.	¶55; ¶57	col. 8:57-61
providing the second regulated voltage as the operating voltage of the memory when the first regulated voltage is less than the value of the minimum operating voltage, wherein while the second...voltage is provided...to the memory, the first...voltage is provided to the functional circuit.	The LLC memory is "ungated" and always supplied with VCC (the second voltage). When the core voltage (first voltage) is below the memory's minimum, the VCC is still provided to the memory array, while the reduced core voltage is provided to the functional circuit (the cores).	¶56; ¶58; ¶59	col. 8:61-66

• Identified Points of Contention:
  • Evidentiary Question: Does the "Vmin Benefit with Cache Size" chart Compl. p.15 constitute evidence that a specific "value of the minimum operating voltage" is "stor[ed] in a non-volatile manner" and used operationally, as Claim 16 requires? Or does it merely illustrate a known physical characteristic of the chip without proving a value is stored and read by the control logic?
  • Scope Question: The complaint's theory of how the "first regulated voltage" and "second regulated voltage" map to the accused product is complex Compl. ¶57 Compl. ¶59 A key issue will be whether the alleged operation, where an "ungated" memory is always supplied with the higher VCC, meets the claim's conditional structure of "providing" one voltage or the other based on a comparison to the stored minimum.

V. Key Claim Terms for Construction

U.S. Patent No. 8,156,357

• The Term: "retrieving information that correlates non-functional ways of the cache with values of the power supply voltage"
• Context and Importance: This term is central to how the patented system identifies which cache ways to disable. The infringement analysis will depend on whether Intel's accused "Dynamic Cache Shrink" feature performs an act of "retrieving" stored data, or if it uses an alternative mechanism. Practitioners may focus on this term because it appears to require a specific implementation (accessing stored data) rather than any method of deactivating cache portions.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification discusses "mapping registers" that "store possible voltage values...and the ways which may be used at each voltage value," which could be read to cover any form of stored configuration data '357 Patent, col. 3:60-64
  • Evidence for a Narrower Interpretation: The specification states that functionality is determined by "pre-characterizing the particular die and storing this information in mapping registers 45 prior to operating," which suggests a specific test-and-store process during manufacturing '357 Patent, col. 4:25-28 An accused infringer could argue this requires a direct lookup of pre-loaded characterization data, not a real-time algorithmic decision.

U.S. Patent No. 7,523,373

• The Term: "storing, in a non-volatile manner, the value of the minimum operating voltage"
• Context and Importance: This term is the foundation of the patent, requiring that a chip-specific minimum voltage be determined and stored. The viability of the infringement claim depends on showing that the accused processors actually perform this "storing" step.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The abstract states the value is stored in a "non-volatile memory location that may be a non-volatile register," which is general language '373 Patent, abstract This could support an argument that storing parameters from which the value is derived meets the limitation.
  • Evidence for a Narrower Interpretation: The patent's flowchart explicitly shows a TEST IC MEMORY step followed by a STORE MIN VDDlogic VOLTAGES TO NON-VOLATILE REGISTERS step '373 Patent, Fig. 4, steps 50, 52 This could support a narrower construction requiring a discrete value, determined by a test, to be written to and later read from a register, a process the accused product may not perform.

VI. Other Allegations

• Indirect Infringement: For all three patents-in-suit, the complaint alleges induced infringement. It claims Intel provides documentation, datasheets via its "publicly accessible ARK service," and software developer's manuals that instruct customers on using the accused processors in a manner that infringes the patented methods Compl. ¶29 Compl. ¶61 Compl. ¶91
• Willful Infringement: The complaint alleges willful infringement for all three patents. The basis for willfulness includes: (1) knowledge of the infringement from at least the date of the complaint's filing; (2) for the '759 Patent, knowledge from a prior lawsuit filed in Delaware on March 1, 2019 Compl. ¶90; and (3) a theory of willful blindness based on Intel's alleged corporate policy of forbidding engineers from reading non-Intel patents to avoid infringement liability Compl. ¶28 Compl. ¶60 Compl. ¶90

VII. Analyst's Conclusion: Key Questions for the Case

1. A core issue will be one of definitional scope: Does the accused "Dynamic Cache Shrink" feature's method for deactivating cache ways constitute "retrieving information that correlates" non-functional ways with voltage levels, as required by the '357 patent? The case may turn on whether Intel's system relies on pre-stored data tables or an algorithm that falls outside this language.

2. A central evidentiary question will be one of operational reality: Does the complaint's evidence, largely based on high-level technical presentations, demonstrate that the accused processors actually "stor[e], in a non-volatile manner, the value of the minimum operating voltage" and use it to conditionally supply power as required by the '373 patent? Or do the accused products achieve a similar result through a different architecture that does not map to the claim's specific steps?

3. A key legal and technical question will be one of willful blindness: Can Plaintiff leverage Intel's alleged corporate policy of not reading third-party patents, combined with prior litigation involving the same technology area and inventors, to successfully establish willful infringement and the potential for enhanced damages? This will depend on the factual development of what Intel knew or should have known about the asserted patents.