DCT

2:26-cv-00875

PulseLink Systems LLC v. NVIDIA Corp

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Complaint
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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:26-cv-00875, E.D. Tex., 09/29/2026
  • Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because NVIDIA maintains regular and established places of business in the district. This claim is based on NVIDIA’s alleged operational and financial control over data center facilities operated by partners Lambda, Inc. (in Plano and Allen) and Aligned Data Centers (in Plano), as well as a manufacturing facility operated by Coherent Corporation (in Sherman).
  • Core Dispute: Plaintiff alleges that Defendant’s data-center networking products, including its Data Processing Units (DPUs), Ethernet switches, and related software, infringe five patents related to network packet processing, loop prevention, multicast rerouting, MAC address learning, and adaptive traffic routing.
  • Technical Context: The technology at issue involves methods for optimizing performance, stability, and efficiency in high-speed computer networks, which are critical for the large-scale data centers that power modern AI and cloud computing services.
  • Key Procedural History: The complaint alleges that Plaintiff engaged in licensing discussions with Defendant beginning in May 2026, during which it provided express notice of the Asserted Patents, infringement analysis, and claim charts. The patents-in-suit originated with Avaya Inc., an enterprise networking company.

Case Timeline

Date Event
2002-04-19 '785 Patent Priority Date
2005-08-17 '220 Patent Priority Date
2009-05-13 '431 Patent Priority Date
2009-05-14 '614 Patent Priority Date
2010-09-10 '230 Patent Priority Date
2010-09-28 '785 Patent Issued
2012-10-30 '614 Patent Issued
2013-01-08 '431 Patent Issued
2013-02-05 '220 Patent Issued
2013-10-22 '230 Patent Issued
2026-05-12 Plaintiff provides notice of infringement to Defendant
2026-05-26 Defendant responds to Plaintiff's notice
2026-06-25 Plaintiff provides further infringement information to Defendant
2026-07-02 Defendant responds to Plaintiff
2026-07-27 Plaintiff provides further infringement information to Defendant
2026-08-03 Defendant confirms receipt of Plaintiff's information
2026-08-25 Plaintiff provides additional details regarding infringement
2026-09-22 Defendant responds to Plaintiff and fails to take a license
2026-09-29 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,804,785 - "Network System Having an Instructional Sequence for Performing Packet Processing and Optimizing the Packet Processing"

  • Patent Identification: U.S. Patent No. 7,804,785, "Network System Having an Instructional Sequence for Performing Packet Processing and Optimizing the Packet Processing," issued September 28, 2010 (the “’785 Patent”).

The Invention Explained

  • Problem Addressed: The patent addresses inefficiencies in prior network systems where discrete hardware devices (e.g., firewalls, load balancers) would each independently process the same data packets, duplicating work and degrading performance Compl. ¶41 ’785 Patent, col. 1:25-39 Existing "fast-path" processing architectures were often "stateless" and did not typically optimize packet processing Compl. ¶44 ’785 Patent, col. 2:30-44
  • The Patented Solution: The invention proposes a virtualized architecture where different network functions are modeled as "Virtual-Service-Modules" arranged in a "virtual graph" Compl. ¶46 ’785 Patent, col. 5:11-16 For a given flow of packets, the system generates a "Combined Action List" of all the primitive processing operations required by the modules in the flow's path Compl. ¶49 An "optimizer" then analyzes this combined list to remove redundant or obsolete steps, creating a shorter, more efficient "optimized combined action list" that is executed by a fast-path processing engine Compl. ¶53 ’785 Patent, col. 11:12-21
  • Technical Importance: This architecture provided a method for consolidating and optimizing the functions of multiple network appliances into a single, programmable system, improving throughput and efficiency Compl. ¶56

Key Claims at a Glance

  • The complaint asserts independent claim 1 and dependent claims 2, 8, and 11 Compl. ¶139
  • The essential elements of independent claim 1 include:
    • A "virtual graph" comprising a plurality of "service modules" modeled to represent network elements.
    • A "first packet processing path" (fast path) with limited decision-making capacity.
    • A "second packet-processing path" (slow path) for handling exceptions.
    • A "stateful decision logic" to determine which path a packet should take.
    • An "optimization component" that optimizes the operations by removing redundant or obsolete primitive operations.
  • The complaint reserves the right to assert additional claims Compl. p. 64

U.S. Patent No. 8,300,614 - "Preventing Packet Loops in Unified Networks"

  • Patent Identification: U.S. Patent No. 8,300,614, "Preventing Packet Loops in Unified Networks," issued October 30, 2012 (the “’614 Patent”).

The Invention Explained

  • Problem Addressed: In "unified networks" that use a mix of physical connections and virtual tunnels, a switch may have multiple potential paths to reach the same destination. This can lead to "infinite loops" where packets are forwarded endlessly between switches, disrupting traffic and consuming network resources Compl. ¶63 ’614 Patent, col. 2:55-67
  • The Patented Solution: The patent discloses a rules-based framework to proactively prevent loops. The system identifies the network topology and, for a given packet, determines if forwarding it on a particular port would create a loop. If a loop is detected, a "loop rule" is used to identify and select an alternative, non-looping port—for example, by prioritizing a physical connection over a virtual tunnel if both are available Compl. ¶64 ’614 Patent, col. 9:5-15 This is implemented by managing VLAN membership to programmatically exclude loop-causing ports from the forwarding plane Compl. ¶65 ’614 Patent, col. 11:35-55
  • Technical Importance: The invention provides a concrete method to ensure stability in complex, hybrid networks that combine physical and virtual infrastructure, which is a foundational requirement for modern data centers Compl. ¶68

Key Claims at a Glance

  • The complaint asserts independent claim 1 and dependent claims 2 and 7 Compl. ¶151
  • The essential elements of independent claim 1 include:
    • "Identifying" a topology of unified switches and links between them.
    • "Computing" at least one port corresponding to a packet's destination.
    • "Determining" at a unified switch when forwarding on a particular port causes a "loop back".
    • "Identifying", in response, a "loop rule" indicative of another port.
    • "Forwarding" the packet on the port indicated by the loop rule, which is a different type (tunnel or physical) than the port causing the loop.
  • The complaint reserves the right to assert additional claims Compl. p. 64

U.S. Patent No. 8,351,431 - "Method and Apparatus for Providing Fast Reroute of a Multicast Packet Within a Network Element to an Available Port Associated with a Multi-Link Trunk"

  • Patent Identification: U.S. Patent No. 8,351,431, "Method and Apparatus for Providing Fast Reroute of a Multicast Packet Within a Network Element to an Available Port Associated with a Multi-Link Trunk," issued January 8, 2013 (the “’431 Patent”).
  • Technology Synopsis: The patent addresses slow recovery from port failures for multicast traffic on multi-link trunks, which typically requires slow control-plane intervention Compl. ¶72 The solution is a hardware-based "fast-reroute" framework where Forwarding Data Units (FDUs) use synchronized local port-state databases to perform a lookup and dynamically select an available "UP" port, enabling sub-ten-millisecond failover without involving the control plane Compl. ¶73 ’431 Patent, abstract
  • Asserted Claims: Independent claim 1 and dependent claims 3 and 5 Compl. ¶163
  • Accused Features: NVIDIA's switching systems implementing multicast failover and MLAG-related forwarding, specifically the NVIDIA Spectrum SN5000 series switch in a PIM active-active MLAG configuration Compl. ¶114

U.S. Patent No. 8,565,230 - "Shared Virtual Tunnels Supporting MAC Learning in Communication Networks"

  • Patent Identification: U.S. Patent No. 8,565,230, "Shared Virtual Tunnels Supporting MAC Learning in Communication Networks," issued October 22, 2013 (the “’230 Patent”).
  • Technology Synopsis: The patent addresses "MAC-learning churn" in dual-homed networks, where a receiving device must constantly re-learn a MAC address as packets arrive from two different tunnels Compl. ¶84 The invention uses a "shared virtual tunnel" with a single virtualized source-device address, causing the receiving device to learn the MAC address against one logical tunnel, which stabilizes the forwarding table even as traffic is load-balanced across the two physical paths Compl. ¶85 ’230 Patent, abstract
  • Asserted Claims: Independent claim 1 and dependent claims 4 and 5 Compl. ¶175
  • Accused Features: NVIDIA switches with dual-homed shared-tunnel encapsulation, particularly the NVIDIA Spectrum SN5000 series switch in an MLAG VXLAN active-active configuration Compl. ¶115

U.S. Patent No. 8,369,220 - "Routing a Flow of Elastic Traffic"

  • Patent Identification: U.S. Patent No. 8,369,220, "Routing a Flow of Elastic Traffic," issued February 5, 2013 (the “’220 Patent”).
  • Technology Synopsis: The patent addresses inefficient routing of "elastic traffic" (e.g., TCP), where conventional protocols either congest the shortest path or spread traffic without feedback Compl. ¶98 The solution uses a two-stage, performance-based path selection method: it first assigns new flows in a round-robin manner until all paths have a minimum flow count, and then assigns subsequent new flows to the path with the highest measured throughput Compl. ¶99 ’220 Patent, col. 2:57-67
  • Asserted Claims: Claims 1-14 Compl. ¶187
  • Accused Features: NVIDIA Ethernet platform products with adaptive routing, including the NVIDIA Spectrum-X Ethernet Platform, its switches, and SuperNICs Compl. ¶116

III. The Accused Instrumentality

Product Identification

The complaint identifies several categories of accused products, collectively referred to as the "Accused Instrumentalities." These include: NVIDIA's BlueField Data Processing Units (DPUs), ConnectX SmartNICs, and SuperNICs; the NVIDIA DOCA software framework; and NVIDIA's Spectrum series Ethernet switches (including the SN2000, SN3000, SN4000, and SN5000 series) and the Spectrum-X Ethernet Platform, which run software such as Cumulus Linux Compl. ¶¶112-116

Functionality and Market Context

The complaint alleges these products form the core of NVIDIA's data-center networking platform, which is designed to interconnect tens of thousands of GPU-accelerated servers for large-scale AI and high-performance computing (HPC) workloads Compl. ¶¶109-110 The DPUs and SmartNICs are described as processors that offload networking and security tasks from a server's main CPU. The Spectrum switches are high-speed Ethernet switches that form the data center fabric. The DOCA framework is the software development kit used to program and configure the functionality of the DPUs and SmartNICs Compl. ¶112

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references but does not attach claim chart exhibits (Exhibits 6-10) detailing its infringement allegations Compl. ¶139 Compl. ¶151 Compl. ¶163 Compl. ¶175 Compl. ¶187 The following is a prose summary of the infringement theories for the lead patents based on the complaint's narrative.

’785 Patent Infringement Allegations
The complaint alleges that NVIDIA's BlueField DPU, ConnectX SmartNIC, and DOCA software framework infringe the ’785 Patent Compl. ¶112 The infringement theory suggests that the accused products create a virtualized packet processing pipeline that mirrors the patent's claims. The complaint alleges these products form a "virtual graph of service modules," use a "fast-path and slow-path dual processing architecture," employ "stateful connection-tracking decision logic" to determine a packet's path, and include an "optimization component that removes redundant primitive operations" Compl. ¶146 These functions are allegedly implemented through the DOCA Flow framework and Connection Tracking modules Compl. ¶146

’614 Patent Infringement Allegations
The complaint alleges that NVIDIA's Spectrum series switches running Cumulus Linux infringe the ’614 Patent through their implementation of overlay loop prevention features Compl. ¶113 The infringement theory centers on the use of "EVPN Multihoming, split-horizon filtering, and Designated Forwarder mechanisms for VXLAN overlay loop prevention" Compl. ¶113 These features allegedly perform the claimed steps of identifying the network topology, determining when a virtual path would create a loop, and forwarding packets through a permitted physical or alternative path to avoid the loop Compl. ¶158

Identified Points of Contention

  • Scope Questions: A central question for the '785 Patent will be whether the accused DOCA software's architecture of programmable "pipes" and "actions" can be properly characterized as an "optimization component" that "remov[es] redundant primitive operations" as claimed. For the '614 Patent, a key dispute may be whether the standardized EVPN and VXLAN loop prevention mechanisms operate in a manner that falls within the scope of the patent's claimed "loop rule."
  • Technical Questions: The infringement analysis will likely require a detailed technical comparison between the accused products and the patent claims. For the '785 Patent, this may involve examining whether NVIDIA's "connection tracking" is functionally the same as the claimed "stateful decision logic." For the '614 Patent, a technical question is whether the proactive VLAN-membership management described in the patent is functionally equivalent to the split-horizon filtering and designated forwarder election used in the accused EVPN systems.

V. Key Claim Terms for Construction

The Term: "optimization component" (’785 Patent, claim 1)

  • Context and Importance: This term is central to the '785 Patent’s claimed novelty of improving efficiency. Infringement depends on whether the accused NVIDIA products contain a component that performs the claimed optimization of removing redundant operations from a combined list of processing steps Compl. ¶146
  • Intrinsic Evidence for a Broader Interpretation: The specification compares the optimizer to "an optimizing programming language compiler," which suggests a potentially broad definition covering any component that makes a sequence of instructions more efficient '785 Patent, col. 12:61-64
  • Intrinsic Evidence for a Narrower Interpretation: The patent discloses a table with specific optimization rules, such as "merge source or destination NAT with a subsequent full NAT" and "merge incremental TCP and IP checksum updates into a single TCP checksum update" '785 Patent, Fig. 10 A defendant may argue the term is limited to these or similar specific types of rule-based logical combinations.

The Term: "loop rule" (’614 Patent, claim 1)

  • Context and Importance: This term defines the logic for selecting a non-looping path, which is the core of the '614 Patent's solution. The infringement case rests on whether the accused EVPN mechanisms function as such a "loop rule."
  • Intrinsic Evidence for a Broader Interpretation: The claim describes the rule as "indicative of another port for forwarding," which could support a broad interpretation covering any logic that redirects traffic to avoid a loop '614 Patent, col. 14:1-2
  • Intrinsic Evidence for a Narrower Interpretation: Dependent claim 7 specifies a situation where the rule "directs invocation of the physical connection for forwarding the packet" when both a physical and virtual path exist '614 Patent, col. 13:25-33 This may support an argument that the term is limited to a specific preference logic, rather than any general loop avoidance mechanism.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement by asserting that NVIDIA knowingly encourages its customers to infringe by providing detailed documentation, technical support, training videos, and professional services that instruct users on how to configure and operate the accused products in an infringing manner Compl. ¶¶143, 155 It alleges contributory infringement on the basis that NVIDIA supplies components, such as DPUs and specific software modules for EVPN and MLAG, that are specially made for the infringing use and are not staple articles of commerce capable of substantial non-infringing use when deployed as instructed (Compl. ¶¶146, 158).
  • Willful Infringement: The complaint alleges willful infringement based on pre-suit knowledge, asserting that NVIDIA received express notice of the Asserted Patents and infringement allegations through a letter and subsequent licensing discussions beginning on May 12, 2026 Compl. ¶121 In the alternative, it pleads willful blindness, arguing that NVIDIA, as a sophisticated actor, was aware of the foundational patent portfolios of its predecessors (Avaya) and deliberately avoided investigating them Compl. ¶131 Willfulness is also alleged based on continued infringement after the filing of the complaint Compl. ¶133

VII. Analyst’s Conclusion: Key Questions for the Case

  • A threshold issue will be one of venue: the case will likely test the contemporary interpretation of a "regular and established place of business," focusing on whether NVIDIA’s asserted deep financial and operational integration with third-party data centers and manufacturers in the Eastern District of Texas is sufficient to establish residency for patent venue purposes.
  • A core technical issue will be one of functional equivalence: does the modern, standards-based functionality in NVIDIA's products (e.g., EVPN multihoming, VXLAN overlays) operate in substantially the same way as the specific, and in some cases proprietary, methods for loop prevention and MAC learning disclosed in patents from the late 2000s/early 2010s, or do they represent a different technological approach to solving similar problems?
  • A central claim construction dispute for the '785 patent will concern definitional scope: can the term "optimization component", described in the patent as removing redundant primitive operations from a list, be construed to read on the accused DOCA software's architecture of programmable "pipes" and "actions," or is there a fundamental mismatch in their claimed function and operation?