Flashcore Innovations LLC v. Samsung Electronics Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Flashcore Innovations LLC (Texas)
  • Defendant: Samsung Electronics Co., Ltd. (Republic of Korea); Samsung Electronics America, Inc. (New York)
  • Plaintiff’s Counsel: Fabricant, Rubino & Lambrianakos LLP
• Case Identification: 2:26-cv-00822, E.D. Tex., 09/14/2026
• Venue Allegations: Venue is alleged to be proper for Samsung Electronics Co., Ltd. as a foreign corporation and for Samsung Electronics America, Inc. based on its corporate offices and business transactions within the Eastern District of Texas.
• Core Dispute: Plaintiff alleges that Defendant’s High Bandwidth Memory (HBM) products and associated memory controllers infringe patents related to high-performance memory architecture and memory access scheduling methods.
• Technical Context: The dispute centers on technologies for high-bandwidth memory, a critical component for data-intensive applications like artificial intelligence (AI), high-performance computing (HPC), and advanced graphics processing.
• Key Procedural History: The complaint alleges that Samsung had pre-suit knowledge of the ’657 Patent no later than June 18, 2018, based on a citation to the patent in Samsung's own Korean patent application, which may be significant for the willfulness allegation.

Case Timeline

Date	Event
2011-12-12	’644 Patent Priority Date
2013-11-29	’657 Patent Priority Date
2015-02-10	’644 Patent Issue Date
2017-08-22	’657 Patent Issue Date
2018-06-18	Alleged date of Samsung's knowledge of ’657 Patent via its own foreign patent application publication
2024-03-01	Samsung demonstrates accused HBM technology at MemCon 2024
2026-09-14	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,740,657 - "Memory Device for Multiple Processors and Memory System Having the Same"

• Patent Identification: U.S. Patent No. 9,740,657, "Memory Device for Multiple Processors and Memory System Having the Same," issued August 22, 2017.

The Invention Explained

• Problem Addressed: The patent addresses the problem of conventional memory systems failing to provide sufficient effective bandwidth for systems with multiple processors, where different processors may simultaneously require access to different memory locations with varying urgency, leading to performance bottlenecks ʼ657 Patent, col. 1:41-54
• The Patented Solution: The invention describes a memory device architecture designed for parallel processing of memory requests. It achieves this through a combination of features: multiple memory banks that are internally divided into independently operable "sub-banks," and a data port with multiple "data channels" that can be dynamically configured (e.g., combined or split) to handle simultaneous requests of varying data widths ʼ657 Patent, abstract ʼ657 Patent, col. 2:1-14 This allows the memory device to process multiple, distinct access requests from different processors at the same time.
• Technical Importance: This architectural approach of enabling configurable, parallel data pathways and subdividing memory resources is foundational for increasing the effective bandwidth of memory systems, a critical factor for performance in modern System-on-Chip (SoC) designs ʼ657 Patent, col. 1:20-25

Key Claims at a Glance

• The complaint asserts at least independent Claim 1 Compl. ¶17
• The essential elements of Claim 1 include:
  • A memory device comprising a command port, an address port, and a data port.
  • The data port comprises a plurality of data channels that are "independently driven to simultaneously process a plurality of memory access requests."
  • A "mode register" is used for "changing a number of the plurality of data channels" by combining or dividing them.
  • A plurality of memory banks, where each bank is divided into a plurality of sub-banks to "simultaneously perform operations."
  • Each sub-bank is divided based on a "bit line."
  • The mode register also changes "at least a part of data widths of the plurality of data channels to be different from one another."
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 8,954,644 - "Apparatus and Method for Controlling Memory"

• Patent Identification: U.S. Patent No. 8,954,644, "Apparatus and Method for Controlling Memory," issued February 10, 2015.

The Invention Explained

• Problem Addressed: The patent identifies inefficiencies in memory controllers that process access requests in a simple, sequential order. This approach incurs significant latency ("waiting cycles") when requests require accessing different rows within the same memory bank or when switching between banks, thereby degrading overall system performance ʼ644 Patent, col. 1:56-65 ʼ644 Patent, col. 2:1-8
• The Patented Solution: The invention proposes an apparatus and method for adaptively reordering memory access requests to maximize bandwidth. It uses a system of buffers, including a main request buffer and bank-specific buffers, to schedule operations intelligently. The controller can look ahead in the request queue; if a current request would cause a delay (e.g., by targeting a "full" bank buffer), it can skip ahead to process a later request targeting a different, available bank. The system also prioritizes successive requests to the same memory row ("row hits") to avoid the latency penalty of closing one row and opening another ʼ644 Patent, abstract ʼ644 Patent, col. 6:40-54
• Technical Importance: This dynamic scheduling logic allows the memory system to utilize otherwise idle cycles, significantly reducing wait times and increasing memory throughput, which is crucial for data-intensive multimedia and processing tasks ʼ644 Patent, col. 1:35-44

Key Claims at a Glance

• The complaint asserts at least independent Claim 6 Compl. ¶36
• The essential steps of method Claim 6 include:
  • (a) Reading a plurality of memory access requests from a buffer unit in order.
  • (b) Determining if a "first bank buffer unit" is not full for an n-th request.
  • (c) If the first bank buffer is not full, transferring the request there; if it is full, reading a subsequent request for a "second bank."
  • (d) Determining if the "second bank buffer unit" is not full and, if so, transferring the subsequent request there.
  • (e) Storing the order in which requests are transferred to the bank buffer units for sequential execution.
  • The claim also includes a "wherein" clause requiring the system to modify the request order to ensure requests to the "same row of same bank are successively processed."
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

III. The Accused Instrumentality

Product Identification

• The complaint identifies Samsung's High Bandwidth Memory ("HBM") products, including specific generations such as HBM2, HBM2E, HBM3, HBM3E, HBM4, and HBM4E, along with their commercial names (e.g., "Aquabolt," "Flashbolt") Compl. ¶11 The allegations also extend to the memory controllers that operate these HBM modules Compl. ¶¶37-41

Functionality and Market Context

• The Accused Products are described as high-bandwidth DRAM modules used in conjunction with GPUs and processors for AI and HPC applications Compl. ¶18 The complaint alleges these products feature a multi-channel architecture with subdivided memory banks that support parallel memory access Compl. ¶¶20-22 It further alleges that the associated controllers queue, reorder, and schedule memory requests based on bank and row status to improve throughput, for example by prioritizing "row hits" Compl. ¶¶37-41 The complaint highlights their market significance by noting Samsung's public demonstrations of the technology at industry events like MemCon 2024 Compl. ¶24 Compl. ¶43 No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

’971 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a data port comprising a plurality of data channels being independently driven to simultaneously process a plurality of memory access requests...	Samsung HBM3 uses multiple independent channels and pseudo-channels to support parallel memory accesses.	¶20	col. 2:6-10
a mode register changing a number of the plurality of data channels being independently driven by combining or dividing the plurality of data channels...	Samsung's HBM technology includes mode-register-controlled splitting of HBM channels into multiple narrower channels.	¶21	col. 2:11-14
a plurality of memory banks, wherein each of the plurality of memory banks is divided into a plurality of sub-banks to simultaneously perform operations...	Samsung HBM divides memory banks into smaller sub-bank resources that support parallel operation.	¶22	col. 2:1-6
wherein each of the plurality of sub-banks is divided based on a bit line...	Samsung HBM DRAM arrays physically subdivided along bit-line and sense-amplifier structures.	¶22	col. 8:28-31
wherein the mode register changes at least a part of data widths of the plurality of data channels to be different from one another by combining or dividing the plurality of data channels.	On information and belief, Samsung HBM use mode-register-controlled configurations such as x64+x32+x32.	¶22	col. 8:42-49

• Identified Points of Contention:
  • Scope Questions: The complaint alleges the use of "pseudo-channels" Compl. ¶20 A potential point of dispute is whether these "pseudo-channels" meet the claim limitation of being "independently driven," which could be construed to require a certain degree of physical or logical separation.
  • Technical Questions: The infringement theory relies on the accused devices having a "mode register" that performs the claimed functions of combining/dividing channels and altering data widths Compl. ¶21 Compl. ¶22 The case may require detailed evidence on the exact mechanism Samsung uses for channel configuration and whether it functions as the claimed "mode register."

’644 Patent Infringement Allegations

Claim Element (from Independent Claim 6)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
(a) reading, by a memory access request control unit, a plurality of memory access requests from a memory access request buffer unit in order...	Samsung HBM3-capable controllers queue multiple memory requests and dynamically schedule their execution... and store multiple requests in a memory request queue and process them through a command scheduler.	¶37	col. 10:13-17
(c) ...if the first bank buffer unit is full, reading a memory access request, bank information of a memory address of which is a second bank, among memory access requests coming after the n-th memory access request...	Samsung controllers distribute requests among separate bank queues and schedule requests associated with different banks out of their original order.	¶39	col. 10:22-31
...modifies the memory access request order so that memory access requests attempting to access a same row of same bank are successively processed.	Samsung bank schedulers use an open-page policy that considers row hits, favoring requests to the already-open row of the same bank.	¶41	col. 10:50-54

• Identified Points of Contention:
  • Scope Questions: The infringement allegation for the ’644 Patent is directed at the functionality of the memory controller used with the HBM modules, not the memory itself Compl. ¶¶37-41 A central issue will be whether the accused combination of Samsung HBM and a third-party or Samsung-made controller practices the claimed method.
  • Technical Questions: Claim 6 recites a specific look-ahead logic where the controller, upon finding a "full" bank buffer, reads a later request for a different bank. The complaint makes a general allegation that controllers "distribute requests among separate bank queues" Compl. ¶39, but does not specify how it performs this exact look-ahead step. Proving this specific operational logic will be a key evidentiary challenge.

V. Key Claim Terms for Construction

For the ’657 Patent

• The Term: "independently driven"
• Context and Importance: This term is central to the claimed parallel processing capability. The complaint’s use of the term "pseudo-channels" Compl. ¶20 suggests that the degree of independence in the accused devices may become a focal point. Practitioners may focus on this term because its construction will determine whether architectures with shared underlying resources can infringe.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification states the channels are driven to "simultaneously process a plurality of memory access requests" ʼ657 Patent, col. 2:8-10 This functional language could support an interpretation where any configuration allowing simultaneous processing, regardless of physical separation, is "independently driven."
  • Evidence for a Narrower Interpretation: Figure 1 depicts "DATA CHANNEL 1" through "DATA CHANNEL n" as distinct parallel lines between the controller and memory device ʼ657 Patent, Fig. 1 A party could argue this implies physically or logically separate pathways are required for channels to be "independently driven."

For the ’644 Patent

• The Term: "memory access request buffer unit"
• Context and Importance: Claim 6 describes a system with a main "memory access request buffer unit" that feeds separate "bank buffer units." The complaint alleges a "memory request queue" and "separate bank queues" Compl. ¶37 Compl. ¶39 The relationship between these alleged structures and the claimed units will be critical. Practitioners may focus on this term because infringement may depend on whether the accused controller has a structure that maps to the specific, two-tiered buffer system described in the patent.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The abstract describes the unit functionally as determining and storing "memory access request order" ʼ644 Patent, abstract, which could be argued to cover a wide range of queuing mechanisms.
  • Evidence for a Narrower Interpretation: Figure 2 explicitly shows "MEMORY ACCESS REQUEST BUFFER UNIT" (210) as a distinct block from the "BANK CONTROL UNIT" (230), which contains the individual bank buffer units (231-234) ʼ644 Patent, Fig. 2 This could support a narrower construction requiring a hierarchical buffer architecture with a clear separation between the main queue and the bank-specific queues.

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement for both patents. Inducement is based on allegations that Samsung provides products along with instructions, user manuals, and product literature that encourage infringing use by customers and end-users Compl. ¶¶27-29 Compl. ¶¶46-48 Contributory infringement is based on allegations that the accused HBM modules are a material part of the invention, are not staple articles of commerce, have no substantial non-infringing use, and are known to be especially made for use in an infringing manner Compl. ¶30 Compl. ¶49
• Willful Infringement: Willfulness is alleged for both patents. For the ’657 Patent, the complaint alleges pre-suit knowledge based on Samsung's citation of the patent in its own Korean patent application, purportedly establishing knowledge as of June 18, 2018 Compl. ¶26, fn. 2 For both patents, willfulness is also predicated on knowledge "at least as of the date of this Complaint" and, alternatively, on a theory of willful blindness arising from an alleged corporate policy of not reviewing the patents of others Compl. ¶26 Compl. ¶45

VII. Analyst’s Conclusion: Key Questions for the Case

1. Willfulness and Pre-Suit Knowledge: A threshold issue will be the evidentiary strength of the pre-suit knowledge allegation against Samsung regarding the ’657 Patent. The case may turn on whether the citation in a Korean patent application is sufficient to establish actual knowledge and intent, which would be central to the claim for willful infringement and potential enhanced damages.
2. Architectural Mapping: A core technical question for the ’657 Patent will be one of definitional scope: can terms like "independently driven" channels and "mode register" be construed to cover the architecture of Samsung's HBM products, which the complaint describes using potentially distinct terminology like "pseudo-channels" and "mode-register-controlled configurations"?
3. Functional Equivalence of Controller Logic: For the ’644 Patent, a key evidentiary question will be one of functional proof: does the accused memory controller software and hardware perform the specific, multi-step reordering method of Claim 6? The analysis will likely focus on whether the plaintiff can demonstrate that the controller implements the claimed look-ahead logic for handling full bank buffers, or if it uses a technically distinct scheduling algorithm.