Mimirip LLC v. MediaTek Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: MimirIP LLC (Texas)
  • Defendant: MediaTek Inc. (Taiwan)
  • Plaintiff's Counsel: Latham & Watkins LLP
• Case Identification: 2:26-cv-00777, E.D. Tex., 09/01/2026
• Venue Allegations: Venue is asserted to be proper because MediaTek is a foreign corporation subject to personal jurisdiction in the district, has committed acts of infringement in the district, and has not contested venue in other recent patent cases in the same district.
• Core Dispute: Plaintiff alleges that Defendant's System-on-Chip (SoC) products infringe four patents related to semiconductor manufacturing methods and memory control circuitry.
• Technical Context: The patents address fundamental aspects of modern semiconductor design, including fabrication techniques for metal interconnects, transistor structure to improve performance, and timing controls for high-speed memory interfaces.
• Key Procedural History: The complaint notes that the asserted patents originated with SK hynix, a major global competitor of MediaTek. It also references several other recent patent infringement lawsuits filed against MediaTek in the Eastern District of Texas to support its venue and jurisdiction arguments.

Case Timeline

Date	Event
2006-06-28	Priority Date for U.S. Patent No. 7,468,317
2006-12-07	Priority Date for U.S. Patent No. 7,755,954
2006-12-07	Priority Date for U.S. Patent No. 7,978,547
2008-02-29	Priority Date for U.S. Patent No. 8,274,102
2008-12-23	U.S. Patent No. 7,468,317 Issues
2010-07-13	U.S. Patent No. 7,755,954 Issues
2011-07-12	U.S. Patent No. 7,978,547 Issues
2012-09-25	U.S. Patent No. 8,274,102 Issues
2026-09-01	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,468,317 - "Method of Forming Metal Line of Semiconductor Device"

The Invention Explained

• Problem Addressed: The patent's background describes how using a traditional metal barrier layer (like titanium/titanium nitride) when depositing tungsten for metal lines in a semiconductor can increase line resistance, which hinders device performance and speed '317 Patent, col. 1:52-61
• The Patented Solution: The invention proposes a method that replaces the conventional metal barrier layer with a nitride insulating layer. This method involves sequentially forming two insulating layers with different etch selectivities, etching a contact hole, forming a metal barrier and filling it with metal to create a plug, and then forming the final metal line '317 Patent, abstract '317 Patent, col. 1:36-41 The use of the nitride layer is asserted to result in a tungsten line with lower resistance '317 Patent, col. 2:1-3
• Technical Importance: This approach aimed to reduce electrical resistance in the increasingly small and dense wiring of integrated circuits, a critical factor for improving chip speed and power efficiency '317 Patent, col. 1:12-18

Key Claims at a Glance

• The complaint asserts independent Claim 1 Compl. ¶36
• The essential elements of Claim 1 are:
  • Sequentially forming a first and second insulating layer with different etch selectivities on a substrate.
  • Sequentially etching the layers to form a contact hole.
  • Forming a metal barrier layer on the surface, including the contact hole.
  • Depositing a first metal material to gap-fill the contact hole.
  • Stripping the first metal material so it remains only within the contact hole, forming a contact plug.
  • Forming a metal line on the second insulating layer including the contact plug.
• The complaint reserves the right to assert other claims Compl. ¶37

U.S. Patent No. 7,755,954 - "Data I/O Control Signal Generating Circuit In A Semiconductor Memory Apparatus"

The Invention Explained

• Problem Addressed: The patent background explains that as semiconductor memory apparatus become more highly integrated, the operating margin for data input/output (I/O) decreases, and errors can occur, particularly when a device must support both high-speed and low-speed operation modes under the same tightly restricted I/O timing '954 Patent, col. 1:46-62
• The Patented Solution: The invention describes a circuit that generates a data I/O control signal with a timing delay that adapts to the operational mode. It uses a delay block that can produce both a "relatively short delay" and a "relatively long delay" signal, and a selection block that chooses the appropriate delay based on the speed mode, which is determined by a CAS (Column Address Strobe) latency signal '954 Patent, abstract '954 Patent, col. 2:3-8 This allows the I/O timing to be optimized for both high-speed and low-speed conditions, improving the operating margin '954 Patent, col. 5:1-10
• Technical Importance: This technology allows for more robust and reliable memory controller performance across different operating speeds, a crucial feature for devices that must dynamically adjust performance to save power or handle different workloads.

Key Claims at a Glance

• The complaint asserts independent Claim 1 Compl. ¶58
• The essential elements of Claim 1 are:
  • A circuit comprising a delay block and a selection block.
  • The delay block generates a delay signal with a relatively short delay value and another with a relatively long delay value.
  • The selection block is configured to select the short delay signal in a high-speed mode and the long delay signal in a low-speed mode.
  • The high-speed mode signal is enabled when a CAS latency signal is more than a predetermined value.
  • The low-speed mode signal is enabled when the CAS latency signal is less than the predetermined value.
• The complaint reserves the right to assert other claims Compl. ¶59

U.S. Patent No. 7,978,547 - "Data I/O Control Signal Generating Circuit In A Semiconductor Memory Apparatus"

Technology Synopsis

This patent, a continuation of the '954 patent, also describes a circuit for adaptively controlling data I/O timing in memory. It claims a configuration with first and second delay blocks providing different delay values, and a selection block that chooses between them based on a CAS latency signal to produce the final I/O control signal '547 Patent, abstract Compl. ¶79 The core concept remains the use of selectable delay paths to accommodate different memory operating speeds.

Asserted Claims

Independent Claim 1 Compl. ¶79

Accused Features

The DDR3-compatible memory controller and physical layer ("PHY") timing circuitry within the Accused Products Compl. ¶81

U.S. Patent No. 8,274,102 - "Semiconductor Device"

Technology Synopsis

This patent addresses the physical structure of transistors. It describes a semiconductor device where a PMOS (P-type Metal-Oxide-Semiconductor) transistor is formed over a silicon germanium (SiGe) layer, which creates a compressive strain structure '102 Patent, abstract This strain is known to increase "hole mobility," improving the transistor's switching speed and overall performance '102 Patent, col. 1:20-24

Asserted Claims

Independent Claim 9 Compl. ¶98

Accused Features

The physical structure of the Accused SoCs, specifically alleging the presence of an active region, a silicon germanium layer in the PMOS region, and PMOS and NMOS gates formed over the active region Compl. ¶¶101-104

III. The Accused Instrumentality

Product Identification

The complaint identifies a wide range of MediaTek's System-on-Chip (SoC) products, including the Dimensity, Helio, and Kompanio series, as the "Accused Products" or "Accused SoCs" Compl. ¶33 Compl. ¶55

Functionality and Market Context

The Accused SoCs are described as the central processing chips in a variety of consumer electronics like smartphones, tablets, and televisions Compl. ¶22 The infringement allegations focus on two aspects of these SoCs:

1. Manufacturing Process & Structure: For the '317 and '102 patents, the complaint alleges that the very method of manufacturing and the resulting physical structure of the SoCs infringe. For example, it alleges the Dimensity 6300 is manufactured using the method claimed in the '317 patent Compl. ¶¶39-40 and the Dimensity 7400 contains the physical transistor structure claimed in the '102 patent Compl. ¶101
2. Memory Control Functionality: For the '954 and '547 patents, the complaint alleges that the memory controller and PHY circuitry within the SoCs, which are designed to comply with JEDEC DDR3 memory standards, practice the claimed inventions for adaptive timing control Compl. ¶60 Compl. ¶81

IV. Analysis of Infringement Allegations

'317 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A method of forming a metal line...comprising the steps of: sequentially forming a first insulating layer and a second insulating layer with different etch selectivities on a semiconductor substrate;	The complaint alleges that the method for manufacturing the Dimensity 6300 includes forming sequential insulating layers with different etch selectivities, supported by a transmission electron microscopy (TEM) image and an energy-dispersive X-ray spectroscopy (EDX) map.	¶40	col. 1:36-39
sequentially etching predetermined regions of the first insulating layer and the second insulating layer to form a contact hole;	A TEM image is provided to show what is alleged to be the claimed contact hole etched into the insulating layers of the Dimensity 6300.	¶41	col. 1:39-41
forming a metal barrier layer on the entire surface including a contact hole;	The complaint presents an EDX map allegedly showing a titanium (Ti) metal barrier layer formed over the surface, including within the contact hole.	¶42	col. 1:42-44
depositing a first metal material on the entire surface so that the contact hole is gap-filled;	An EDX map is presented to show what is alleged to be cobalt (Co) as the first metal material filling the contact hole.	¶43	col. 1:48-50
stripping the first metal material on the second insulating layer so that the first metal material remains only within the contact hole, thus forming a contact plug;	The complaint provides an annotated image allegedly showing the first metal material (cobalt) remaining only within the contact hole, forming a contact plug.	¶44	col. 2:1-4
forming a metal line on a predetermined region of the second insulating layer including the contact plug.	An EDX map is presented to show what is alleged to be a tungsten (W) metal line formed over the insulating layer and including the previously formed contact plug.	¶45	col. 2:14-16

• Identified Points of Contention:
  • Process Questions: While the complaint provides detailed microscopy evidence, a key dispute may arise over whether the accused manufacturing process performs the claimed steps in the claimed order and manner. For instance, the defense may question whether the stripping step Compl. ¶44 functions exactly as claimed or if the final metal line is formed "on a predetermined region" in the manner envisioned by the patent.
  • Scope Questions: The interpretation of "different etch selectivities" could be a focal point. The court will need to determine if the materials used in the accused process exhibit this property in a way that falls within the claim's scope as understood from the patent's specification.

'954 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a delay block for generating a delay signal having a relatively short delay value and a delay signal having a relatively long delay value;	The complaint alleges that the accused DDR3 products have an adjustable DQS delay circuitry that provides different write-timing delay values, which are alleged to be the claimed "relatively short" and "relatively long" delay values.	¶61	col. 1:4-6
a selection block for selecting any one of the delay signals according to a speed type of an operation mode...configured to select the delay signal having a relatively short delay value in a high-speed operation mode, and is configured to select the delay signal having a relatively long delay value in a low-speed operation mode	The complaint alleges that the accused DDR3 products' controller/PHY logic selects different DQS write-time delay values based on the CAS Write Latency (CWL) timing mode, which is alleged to constitute the claimed selection block.	¶¶62-63	col. 2:11-15
wherein the high-speed operation mode signal is a signal which is enabled in a high level when a CAS latency signal is more than a predetermined value	The complaint maps this to the DDR3 standard's MR2 register, alleging that for high CWL values (e.g., 9-12), a specific bit (A5) is set high, which acts as the claimed high-speed signal when the CWL is more than a predetermined value (e.g., 8-9 clock cycles).	¶64	col. 2:31-33
wherein the low-speed operation mode signal is a signal which is enabled in a high level when the CAS latency signal is less than the predetermined value.	The complaint alleges that for low CWL values (e.g., 5-8), the MR2 bit A5 is set low, and a decoded signal corresponding to this state acts as the claimed low-speed signal, enabled when the CWL is less than the predetermined value.	¶65	col. 2:33-35

• Identified Points of Contention:
  • Technical Questions: A central question will be whether the accused products' implementation of the JEDEC DDR3 standard is a direct equivalent of the claimed circuit. The defense may argue that compliance with a general standard does not automatically mean infringement of a specific patented circuit architecture, and there may be technical differences in how the delay and selection are actually implemented.
  • Scope Questions: The case may turn on the construction of "CAS latency signal." The complaint maps this term to the CWL value encoded in the DDR3 standard's MR2 register. The court will need to decide if the standard's mechanism for setting latency modes is what the patent means by a "CAS latency signal" that enables a high-speed or low-speed "operation mode signal."

V. Key Claim Terms for Construction

• For the '317 Patent:

  • The Term: "different etch selectivities"
  • Context and Importance: This term is fundamental to the core inventive step of using two distinct insulating layers that can be etched sequentially to form the contact hole. The infringement analysis depends on whether the materials used in MediaTek's process have this claimed property.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent claims are not limited to specific materials, suggesting the term could encompass any pair of materials where one etches at a different rate than the other under a given etchant. Claim 1 itself simply requires the property exists '317 Patent, claim 1
    • Evidence for a Narrower Interpretation: The specification's preferred embodiment and claim 9 specifically identify the first insulating layer as an "oxidization layer" and the second as a "nitride layer" '317 Patent, col. 1:36-39 '317 Patent, claim 9 A party could argue the term should be construed in light of this more specific disclosure.

• For the '954 Patent:

  • The Term: "CAS latency signal"
  • Context and Importance: This signal is the input that controls which delay path (high-speed or low-speed) is selected. The infringement case hinges on mapping this claim term to the functionality of the accused DDR3-compliant products. Practitioners may focus on this term because the complaint's theory relies on equating this term with the CWL values programmed into a DDR3 memory mode register.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language is functional, referring to a signal that indicates whether CAS latency is above or below a threshold. This could be read to cover any signal that conveys this information, regardless of its specific format or origin '954 Patent, claim 1 The specification also refers to "High CAS Latency (HCL) signal" and "low CAS Latency (LCL) signal" in general terms '954 Patent, col. 3:50-55
    • Evidence for a Narrower Interpretation: The patent's figures and detailed description show distinct "HCL" and "LCL" input lines to the selection block '954 Patent, FIG. 2 A party might argue that a "CAS latency signal" must be a dedicated signal line as depicted in the embodiments, rather than a value stored in a register that is later decoded, as alleged by the complaint Compl. ¶64

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement to infringe for all four patents. The allegations are based on MediaTek knowingly designing the Accused SoCs with the infringing features and encouraging third-party manufacturers, distributors, and customers to import, sell, and use products containing them Compl. ¶48 Compl. ¶69 Compl. ¶88 Compl. ¶107
• Willful Infringement: Willfulness is alleged for all four patents. The complaint asserts that MediaTek knew or should have known of the patents since their issue dates due to its position as a major competitor of the original assignee, SK hynix Compl. ¶26 It further alleges that, at a minimum, MediaTek has had knowledge of its infringement since the filing of the complaint Compl. ¶50 Compl. ¶71 Compl. ¶90 Compl. ¶109

VII. Analyst's Conclusion: Key Questions for the Case

The resolution of this case may depend on the court's determination of two central issues:

1. A core issue for the '317 and '102 patents will be one of empirical identity: Do the transmission electron microscopy and spectroscopy images presented in the complaint accurately depict the accused devices, and if so, do these physical structures and the processes used to create them map directly onto the specific limitations of the asserted claims? The dispute will likely move from high-level allegations to a microscopic comparison of materials, layers, and process steps.

2. A key question for the '954 and '547 patents will be one of standards-based interpretation: Does an accused device's compliance with an industry standard (JEDEC DDR3) inherently constitute infringement of a patent claim whose limitations are described in more abstract or architectural terms? The court will need to decide if the functional blocks and signals described in the patents are necessarily present in any standards-compliant DDR3 memory controller, or if the standard allows for non-infringing alternative implementations.