2:26-cv-00747
InnoMemory LLC v. Kontron Europe GmbH
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: InnoMemory, LLC (Texas)
- Defendant: Kontron Europe GmbH (Germany)
- Plaintiff's Counsel: Rabicoff Law LLC
- Case Identification: 2:26-cv-00747, E.D. Tex., 08/25/2026
- Venue Allegations: Venue is asserted based on the Defendant being a foreign corporation and having committed alleged acts of patent infringement within the district.
- Core Dispute: Plaintiff alleges that Defendant's products, which incorporate memory devices, infringe a patent related to methods for reducing power consumption during memory refresh operations.
- Technical Context: The technology concerns power-saving techniques in dynamic random access memory (DRAM), which is critical for extending the battery life of portable and mobile electronic devices.
- Key Procedural History: The asserted patent is a continuation of a prior application which issued as U.S. Patent No. 6,618,314, establishing an earlier priority date for the claimed subject matter. The complaint does not mention any other prior litigation, licensing history, or administrative proceedings related to the patent-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2002-03-04 | '960 Patent Priority Date |
| 2003-07-29 | '960 Patent Application Filing Date |
| 2006-06-06 | '960 Patent Issue Date |
| 2026-08-25 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"
- Patent Identification: U.S. Patent No. 7,057,960 ("Method and architecture for reducing the power consumption for memory devices in refresh operations"), issued June 6, 2006.
The Invention Explained
- Problem Addressed: The patent addresses the problem of significant power consumption in memory devices during standby mode '960 Patent, col. 1:28-35 Conventional dynamic memories (DRAMs) must periodically refresh their memory cells to prevent data loss, a process that consumes power even when the device is idle. The patent notes that even in partial refresh modes, conventional designs activate peripheral support circuits for the entire memory array, leading to unnecessary power drain '960 Patent, col. 2:26-29
- The Patented Solution: The invention proposes an architecture that divides the memory array into multiple sections (e.g., quadrants) and provides independent control over the peripheral circuitry for each section '960 Patent, abstract During a partial refresh operation, the patented method activates the peripheral circuits only for the specific section(s) being refreshed, while leaving the circuits for the other sections powered down '960 Patent, col. 6:8-21 This selective activation is managed by dedicated control signals (e.g., REF0-REFn) that are generated in response to a programmable address indicating which sections to refresh '960 Patent, col. 4:8-13 '960 Patent, claim 1 Figure 3 of the patent illustrates this architecture, showing how a refresh control block generates separate signals (REF0-REF3) to control different quadrants of the memory array.
- Technical Importance: This approach aimed to reduce standby power consumption, a critical factor for the growing market of battery-powered mobile devices like portable telephones, where extending standby time is a significant competitive advantage '960 Patent, col. 1:35-45
- No probative visual evidence provided in complaint.
Key Claims at a Glance
The complaint alleges infringement of "exemplary method claims" without specifying claim numbers Compl. ¶11 Independent claim 1 is the broadest method claim.
- Independent Claim 1 (Method):
- A method for reducing power consumption in a memory array having a plurality of sections.
- The method involves controlling background operations (e.g., refresh) in each section in response to control signals.
- These control signals are generated in response to a "programmable address signal."
- The background operations can be enabled simultaneously in two or more sections, "independently of any other section."
- The method involves presenting the control signals and decoded address signals to "periphery array circuits" of the sections.
The complaint does not explicitly reserve the right to assert dependent claims, but refers generally to infringement of "one or more claims" Compl. ¶11
III. The Accused Instrumentality
Product Identification
The complaint refers to "Exemplary Defendant Products" but does not name them in the main body of the document Compl. ¶11 It states these products are identified in charts within "Exhibit 2" Compl. ¶13
Functionality and Market Context
The complaint does not describe the functionality of the accused products. It alleges that the products are identified in charts that compare them to the patent claims Compl. ¶13 The complaint alleges these products were made, used, sold, or imported by the Defendant Compl. ¶11 The complaint does not provide sufficient detail for analysis of the products' specific functionality or market context.
IV. Analysis of Infringement Allegations
The complaint alleges infringement via claim charts provided in Exhibit 2, which was not available for this analysis Compl. ¶13 Compl. ¶14 The complaint summarily alleges that the "Exemplary Defendant Products" practice the claimed technology and "satisfy all elements of the Exemplary '960 Patent Claims" Compl. ¶13 Due to the absence of the referenced exhibit and any specific factual allegations in the complaint's body, a detailed claim chart summary cannot be constructed.
Identified Points of Contention
Based on the language of claim 1 of the '960 Patent, the infringement analysis may raise several key questions for the court.
- Scope Questions: A central question may be the proper construction of "periphery array circuits." The patent provides examples such as "sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" '960 Patent, col. 11:66-col. 12:2 The dispute could turn on whether the specific components within the accused products' memory controllers fall within the scope of this term as it is defined and used in the patent.
- Technical Questions: A significant technical question is what evidence the plaintiff will offer to show that the accused products' memory controllers can enable refresh operations in multiple sections "independently of any other section," as required by claim 1. The defense may argue that their products refresh sections in fixed groups or pairs, which may not meet this "independently" limitation. Further, evidence will be required to demonstrate that this independent control is driven by a "programmable address signal," a term that may itself become a focus of claim construction.
V. Key Claim Terms for Construction
"periphery array circuits"
- Context and Importance: This term is the object of the invention's core function: selective activation and deactivation to save power. The definition of what is included in these "circuits" will be critical to determining infringement, as it defines what must be controlled by the claimed signals.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim language itself is general, and practitioners may argue it should not be limited to the specific examples given. The specification describes the function of these circuits as being to "access the memory cells" '960 Patent, col. 3:25-27, potentially encompassing any circuitry required for that purpose.
- Evidence for a Narrower Interpretation: Claim 5 explicitly lists a group of circuits: "sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" '960 Patent, col. 11:66-col. 12:2 A party may argue that this list, though in a dependent claim, informs and narrows the scope of the term as used in the independent claim.
"programmable address signal"
- Context and Importance: Claim 1 requires the control signals to be generated "in response to a programmable address signal." This suggests the selection of memory sections for refresh is not hard-wired but configurable. The interpretation of "programmable" will be key to determining whether the accused devices meet this limitation.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A party could argue that any signal that can be changed or set, even if only at system boot or by a driver, qualifies as "programmable."
- Evidence for a Narrower Interpretation: Claim 27 and the specification describe a "register configured to store said one or more block address signals," which control which sections are refreshed '960 Patent, claim 27 '960 Patent, col. 8:1-4 This may support an argument that the term requires a dedicated, writable register for storing the section-selection information, a more specific form of programmability.
VI. Other Allegations
- Indirect Infringement: The complaint does not contain allegations of indirect infringement.
- Willful Infringement: The complaint does not use the word "willful." However, in its prayer for relief, Plaintiff requests that the case be declared "exceptional" for the purpose of awarding attorneys' fees pursuant to 35 U.S.C. § 285 Compl. Prayer E.i The complaint does not plead any specific facts regarding pre-suit knowledge of the patent or egregious conduct that would typically support such a request.
VII. Analyst's Conclusion: Key Questions for the Case
This dispute, as framed by the complaint and the patent-in-suit, appears to center on the precise architecture and operation of modern memory controllers. The key questions for the court will likely be:
A core issue will be one of definitional scope: can the term "periphery array circuits", as defined in the '960 Patent, be construed to read on the specific collection of hardware components used in the Defendant's memory architecture? The outcome will depend on whether the patent's examples are treated as limiting or merely illustrative.
A key evidentiary question will be one of technical implementation: what level of evidence is required to prove that the accused products' memory controllers enable refresh operations for different memory sections "independently of any other section," as mandated by claim 1? This will likely involve a deep dive into the hardware design and firmware of the accused devices to determine if their control scheme matches the patent's specific requirements for granular, programmable power management.