InnoMemory LLC v. Dfi Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: DFI Inc. (Taiwan)
  • Plaintiff's Counsel: Rabicoff Law LLC
• Case Identification: 2:26-cv-00745, E.D. Tex., 08/25/2026
• Venue Allegations: Venue is asserted based on the defendant being a foreign corporation.
• Core Dispute: Plaintiff alleges that Defendant's unspecified memory products infringe a patent related to methods for reducing power consumption in memory devices during refresh operations.
• Technical Context: The technology concerns power management in dynamic random-access memory (DRAM), a critical issue for extending battery life in portable electronic devices.
• Key Procedural History: The patent-in-suit is a continuation of U.S. Application No. 10/090,850, which issued as U.S. Patent No. 6,618,314.

Case Timeline

Date	Event
2002-03-04	Earliest Priority Date (from parent application)
2003-07-29	Application Date for U.S. Patent No. 7,057,960
2006-06-06	Issue Date for U.S. Patent No. 7,057,960
2026-08-25	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

The Invention Explained

• Problem Addressed: The patent describes a problem with conventional dynamic random-access memory (DRAM) devices used in battery-powered electronics. During standby or power-down modes, these devices must periodically refresh their memory cells to prevent data loss, a process that consumes power. Conventional methods activate the support circuitry (periphery array circuits) for the entire memory array during a refresh cycle, even if only a portion of the memory contains data that needs to be retained, leading to unnecessary power consumption. '960 Patent, col. 1:28-56 '960 Patent, col. 2:25-29
• The Patented Solution: The invention provides a method and architecture to reduce this power consumption by dividing the memory array into multiple sections (e.g., quadrants) and selectively controlling the background operations, such as refresh, for each section independently. A control circuit receives a programmable signal indicating which sections to refresh and presents control and address signals only to the periphery array circuits of those specific sections, leaving the circuits for other sections inactive. '960 Patent, abstract '960 Patent, col. 5:46-col. 6:22 This targeted activation of support circuitry is designed to minimize standby power draw.
• Technical Importance: This approach allows for more granular power management in memory subsystems, a key factor in improving the operational longevity of mobile and battery-operated devices. '960 Patent, col. 1:30-34

Key Claims at a Glance

The complaint does not specify which claims are asserted, instead referring to "Exemplary '960 Patent Claims" detailed in an attached exhibit not provided with the complaint Compl. ¶13 Independent method claim 1 is representative of the patent's core teachings.

• Independent Claim 1:
  • controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals,
  • wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
  • presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.

The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

The complaint does not name any specific accused products. It refers generally to "Defendant products" and "Exemplary Defendant Products" that are identified in charts within "Exhibit 2" Compl. ¶11 Compl. ¶13 This exhibit was not included with the filed complaint.

Functionality and Market Context

The complaint alleges that the accused products "practice the technology claimed by the '960 Patent" Compl. ¶13 Based on the patent's subject matter, these are likely memory devices (e.g., DRAM chips or modules) that incorporate power-saving features for background or refresh operations. The complaint does not provide any specific details about the functionality or market position of the accused products.

IV. Analysis of Infringement Allegations

The complaint alleges that infringement is detailed in claim charts provided in an external exhibit Compl. ¶13, which is not available for analysis. The infringement theory, as stated in the complaint, is that the accused products "satisfy all elements of the Exemplary '960 Patent Claims" Compl. ¶13 Without the specific product details or the claim charts, a detailed element-by-element analysis is not possible.

No probative visual evidence provided in complaint.

Identified Points of Contention

Given the lack of specific infringement allegations in the complaint, any analysis must anticipate likely areas of dispute based on the claim language.

• Scope Questions: A central question may be whether the power-saving functionality in the accused products operates in a manner that falls within the scope of the claims. For example, does the mechanism for selecting memory portions for low-power refresh rely on a "programmable address signal" that allows sections to be enabled "independently," as required by claim 1?
• Technical Questions: A key technical question will be whether the accused products actually de-activate "periphery array circuits" for non-refreshed sections. The defense may argue that their products achieve power savings through a different technical means, such as voltage reduction or clock gating, that does not map onto the claimed method of selectively enabling and disabling distinct periphery circuits.

V. Key Claim Terms for Construction

The complaint provides no basis for claim construction analysis. However, based on the technology and claim language, the following terms may be central to the dispute.

"background operations"

• Context and Importance: This term defines the scope of the claimed method. The patent primarily discusses "refresh operations" but also mentions "parity checking" and "housekeeping operations" as potential background operations '960 Patent, col. 2:54-55 '960 Patent, col. 8:20-24 Practitioners may focus on this term to determine if the power-saving modes in the accused products, which may involve various low-power states, qualify as the claimed "background operations."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: Claim 1 uses the general term "background operations" without limitation. The specification also refers to "other background memory access operations and/or housekeeping operations" as being within the invention's scope '960 Patent, col. 8:20-22
  • Evidence for a Narrower Interpretation: The patent's title, abstract, and detailed description are heavily focused on "refresh operations," which could support an argument that "background operations" should be construed as being limited to refresh-type activities. '960 Patent, title '960 Patent, abstract '960 Patent, col. 2:54-55

"programmable address signal"

• Context and Importance: This signal is the input that controls which memory sections are selected for the background operation. Its definition is critical for determining whether the accused products meet this limitation. The dispute may turn on what type of signal qualifies as "programmable" in this context.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term itself suggests any signal that can be set or altered to designate an address or location, which could encompass a wide range of software- or hardware-based controls.
  • Evidence for a Narrower Interpretation: The patent states this signal is used to generate control signals and that the portion of the array to be refreshed "may be controlled by information (e.g., a block address) stored in a refresh address register" '960 Patent, col. 8:2-4 This may support an argument that the term requires a specific register-based implementation that stores a "block address."

"periphery array circuits"

• Context and Importance: The invention's power-saving benefit comes from selectively deactivating these specific circuits. Defining what is included in "periphery array circuits" will be essential to proving infringement.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term could be interpreted broadly to mean any support circuitry associated with a memory section that is not part of the core cell matrix itself.
  • Evidence for a Narrower Interpretation: Claim 5 and the associated specification provide a specific, though not necessarily exhaustive, list of such circuits, including "sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" '960 Patent, col. 8:66-col. 9:1 A party could argue the term is limited to this class of components.

VI. Other Allegations

Willful Infringement

The complaint does not contain an explicit allegation of willful infringement. However, in the prayer for relief, it requests that the case be declared "exceptional" and seeks an award of attorneys' fees under 35 U.S.C. § 285 Compl., Prayer for Relief E.i. The complaint does not plead any specific facts, such as pre-suit knowledge of the patent, to support this request.

VII. Analyst's Conclusion: Key Questions for the Case

The complaint's lack of specificity makes any early analysis preliminary. The case will likely center on the following questions once discovery commences.

• An Evidentiary Question of Fact: The primary issue will be whether Plaintiff can produce evidence that the accused products-once they are identified-actually practice the claimed method. Given the bare-bones nature of the complaint, the entire case hinges on Plaintiff's ability to demonstrate that Defendant's devices employ a power-saving architecture that selectively enables and disables discrete periphery circuits for different memory sections.
• A Definitional Question of Scope: A core legal issue will be the construction of "periphery array circuits." The infringement analysis will depend heavily on whether the components that are allegedly deactivated in the accused products fall within the court's definition of this term, or if Defendant's products achieve power savings via an alternative mechanism not covered by the claims.
• A Functional Question of Independence: The case may turn on the interpretation of claim 1's requirement that background operations "can be enabled simultaneously in two or more of said plurality of sections independently of any other section." The key question will be whether the accused devices' control architecture provides this specific level of independent, granular control over memory sections, or if their power management scheme operates on a different principle.