Stellar Semiconductor Tech LLC v. Samsung Electronics Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Stellar Semiconductor Technologies, LLC (Delaware)
  • Defendant: Samsung Electronics Co., Ltd. (Republic of Korea) and Samsung Electronics America, Inc. (New York)
  • Plaintiff's Counsel: Susman Godfrey LLP.
• Case Identification: 2:26-cv-00673, E.D. Tex., 08/07/2026
• Venue Allegations: Venue for Samsung Electronics Co., Ltd. is based on it being a foreign corporation. Venue for Samsung Electronics America, Inc. is based on alleged acts of infringement within the district and its regular and established place of business in Plano, Texas, which is slated to become its U.S. headquarters.
• Core Dispute: Plaintiff alleges that Defendants' semiconductor processors, and the consumer electronics that contain them, infringe six patents related to advanced semiconductor device structures and manufacturing methods.
• Technical Context: The technology at issue involves fundamental building blocks of modern microprocessors, including FinFET transistor architectures, specialized contact structures, and SRAM memory cell layouts used in leading-edge manufacturing nodes.
• Key Procedural History: The complaint notes that Defendants have not disputed personal jurisdiction or venue in the Eastern District of Texas in other recent patent litigation. It also highlights Samsung's significant investments in semiconductor fabrication facilities in Texas, partly supported by U.S. and Texas government funding initiatives.

Case Timeline

Date	Event
2011-11-09	'140 Patent Priority Date
2012-12-05	'367 Patent Priority Date
2014-10-14	'100 Patent Priority Date
2015-04-30	'966 Patent Priority Date
2015-12-22	U.S. Patent No. 9,219,140 Issues
2016-03-08	U.S. Patent No. 9,281,367 Issues
2016-11-23	'267 Patent Priority Date
2017-03-07	U.S. Patent No. 9,589,966 Issues
2017-06-06	U.S. Patent No. 9,673,100 Issues
2018-02-20	U.S. Patent No. 9,899,267 Issues
2019-08-20	'666 Patent Priority Date
2024-09-10	U.S. Patent No. 12,087,666 Issues
2026-08-07	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,219,140 - "Metal Oxide Semiconductor Transistor and Manufacturing Method Thereof"

• Issued: December 22, 2015.

The Invention Explained

• Problem Addressed: In advanced semiconductor manufacturing, particularly in "high-k last" processes, the high-temperature annealing step required to improve the quality of the high-k dielectric layer can be harmful to other previously formed components, such as the silicide layer that forms the electrical contact to the source/drain region. ʼ140 Patent, col. 1:40-54
• The Patented Solution: The patent describes forming the silicide layer after the high-k dielectric layer has been formed and annealed, thereby decoupling the two critical process steps. The silicide is formed within a narrow contact hole, which results in a unique "crescent" or "smile" shape with a curved top and bottom surface. ʼ140 Patent, abstract ʼ140 Patent, col. 5:15-36 This shape is alleged to increase the contact area between the silicide and an overlying contact plug, reducing electrical resistance. ʼ140 Patent, col. 5:47-51
• Technical Importance: This method allows for the optimization of both the high-k gate dielectric and the silicide contact, which is critical for maintaining performance and reliability as transistors scale to smaller dimensions. ʼ140 Patent, col. 2:13-18

Key Claims at a Glance

• The complaint asserts infringement of at least claim 1 and dependent claims 3, 4, and 7 Compl. ¶¶57; Compl. ¶60
• Independent Claim 1 recites essential elements including:
  • A MOS transistor comprising a substrate, gate dielectric, gate, and source/drain region.
  • A silicide layer disposed on the source/drain region.
  • The silicide layer comprises a "crescent structure" defined by specific geometric properties: a curved bottom surface and a curved top surface, both bending toward the substrate; the top surface is "sunken from two sides"; two ends form "point tips raised up"; and the middle is thicker than the periphery.

U.S. Patent No. 9,281,367 - "Semiconductor Structure Having Contact Plug and Method of Making the Same"

• Issued: March 8, 2016.

The Invention Explained

• Problem Addressed: As semiconductor devices shrink, creating reliable electrical connections (contacts) to the transistor's gate and source/drain regions becomes increasingly difficult. Conventional wiring schemes can suffer from high resistance and an increased risk of electrical shorts between the gate contact and the source/drain contact. ʼ367 Patent, col. 1:36-47
• The Patented Solution: The patent discloses a multi-level contact structure using two distinct interlayer dielectric (ILD) layers. The structure features three types of contact plugs: a first plug connects to the source/drain; a second, wider plug connects to the first plug from the layer above; and a third, separate plug connects directly to the gate, extending through both ILD layers. A key feature is that the top of the first contact plug is physically higher than the top of the gate, which creates vertical separation to help prevent short circuits. ʼ367 Patent, abstract ʼ367 Patent, col. 2:7-13
• Technical Importance: This architecture provides a robust and spatially efficient method for routing separate electrical connections to the gate and source/drain regions in dense, modern transistor layouts, enhancing device performance and reliability. ʼ367 Patent, col. 2:5-7

Key Claims at a Glance

• The complaint asserts infringement of at least claim 1 and dependent claims 2, 3, and 10 Compl. ¶¶72; Compl. ¶74
• Independent Claim 1 recites essential elements including:
  • A transistor on a substrate.
  • A first ILD layer on the transistor, with a bottom surface level with the gate's top surface.
  • A first contact plug in the first ILD layer to connect the source/drain region, wherein the top surface of this plug is higher than the top surface of the gate.
  • A second ILD layer on the first ILD layer.
  • A second contact plug in the second ILD layer electrically connected to the first contact plug.
  • A third contact plug in both the first and second ILD layers to electrically connect the gate.

U.S. Patent No. 9,589,966 - "Static Random Access Memory"

• Patent Identification: U.S. Patent No. 9589966, "Static Random Access Memory", issued March 7, 2017 Compl. ¶25
• Technology Synopsis: The patent discloses a static random access memory (SRAM) cell structure. The invention focuses on a contact scheme comprising a first contact plug in a first interlayer dielectric (ILD) layer and a second contact plug in a second ILD layer, where the second plug connects to the first, creating a two-tiered contact. Compl. ¶26 This structure is designed to address patterning and connectivity challenges in dense SRAM arrays.
• Asserted Claims: At least claim 1 is asserted Compl. ¶83
• Accused Features: The complaint alleges that the SRAM cell contact topologies in the Accused Processors, which use multi-layer contact plugs, infringe the '966 patent Compl. ¶82

U.S. Patent No. 9,673,100 - "Semiconductor Device Having Contact Plug in Two Dielectric Layers and Two Etch Stop Layers"

• Patent Identification: U.S. Patent No. 9673100, "Semiconductor Device Having Contact Plug in Two Dielectric Layers and Two Etch Stop Layers", issued June 6, 2017 Compl. ¶28
• Technology Synopsis: The patent claims a semiconductor device with a "butted contact" structure, where a single contact plug connects to both a gate structure and an adjacent source/drain contact plug. The structure is enabled by a specific stack of materials, including two separate dielectric layers and two separate etch-stop layers, which allows for the precise formation of these complex, space-saving contacts. Compl. ¶29 Compl. ¶92
• Asserted Claims: At least claim 1 is asserted Compl. ¶94
• Accused Features: The complaint accuses processors made with TSMC's N4 and N4P nodes of infringing, alleging they employ butted contact structures formed using a dual etch-stop and multi-layer dielectric integration Compl. ¶93

U.S. Patent No. 9,899,267 - "Semiconductor Device and Manufacturing Method Thereof"

• Patent Identification: U.S. Patent No. 9899267, "Semiconductor Device and Manufacturing Method Thereof", issued February 20, 2018 Compl. ¶31
• Technology Synopsis: This patent addresses the need to electrically isolate adjacent gate electrodes in densely packed logic cells. It describes a "gate isolation structure" composed of three vertically stacked sections, where the lower sections extend progressively deeper, with the bottom section being lower than the bottom surface of the surrounding shallow trench isolation (STI) structure. Compl. ¶32 Compl. ¶105
• Asserted Claims: At least claim 8 is asserted Compl. ¶105
• Accused Features: The complaint alleges that certain advanced process nodes employ three-section gate-isolation structures as part of their standard-cell design rules, infringing the '267 patent Compl. ¶104

U.S. Patent No. 12,087,666 - "Semiconductor Device"

• Patent Identification: U.S. Patent No. 12087666, "Semiconductor Device", issued September 10, 2024 Compl. ¶34
• Technology Synopsis: The patent claims a specific layout for a standard logic cell that reduces area and simplifies design. The invention centers on the use of a "first slot contact structure" that is continuously elongated across active regions and an isolation structure, in combination with a "second slot contact structure" that is shorter than the first. Compl. ¶35
• Asserted Claims: At least claim 1 is asserted Compl. ¶116
• Accused Features: The complaint accuses certain process nodes of employing slot-contact and gate-contact layout configurations in their standard logic cells that practice the claimed invention Compl. ¶115

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are semiconductor processors, including the Qualcomm Snapdragon series (e.g., 855, 865, 8 Gen 1, 8 Gen 2) and Samsung Exynos series (e.g., 1280, 1380), as well as the Samsung-branded consumer devices that incorporate them, such as Galaxy smartphones and tablets Compl. ¶¶49-50 Compl. p. 16 chart

Functionality and Market Context

The infringement allegations focus on the physical micro-architecture of the processors, not their software or user-facing functions. The complaint alleges that specific advanced manufacturing process nodes used by Samsung and its foundry partner, TSMC, (e.g., 7nm, 5nm, 4nm, 3nm nodes) produce FinFET transistors, contact stacks, and cell layouts with structures that infringe the Asserted Patents Compl. ¶¶37-47 The complaint asserts that these processors are specialized components made for incorporation into consumer electronics and are not staple articles of commerce suitable for substantial non-infringing use Compl. ¶65

IV. Analysis of Infringement Allegations

The complaint provides annotated Transmission Electron Microscope (TEM) images from reverse-engineering analyses to support its infringement allegations. The annotated TEM cross-section of the Snapdragon 8+ Gen 1 processor shown in the complaint depicts the crescent silicide structure alleged to infringe the '140 patent Compl. p. 19, top image Another annotated TEM cross-section of the same processor identifies first, second, and third contact plugs alleged to infringe the '367 patent Compl. p. 23

'140 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a silicide layer disposed on a part of the source/drain region, wherein the silicide layer comprises a curved bottom surface and a curved top surface, wherein both the curved top surface and the curved bottom surface of the silicide layer bends toward the substrate and the curved top surface is sunken from two sides thereof ... and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure	The Snapdragon 8+ Gen 1 processor allegedly contains a silicide layer on its source/drain region that has a "crescent" shape, with both a curved top and bottom surface bending toward the substrate, a sunken top surface, and a thicker middle portion, as shown in an annotated TEM image.	¶59	col. 5:15-36

'367 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a first contact plug disposed in the first ILD layer to electrically connect the source/drain region, wherein a top surface of the first contact plug is higher than a top surface of the gate...	The accused Snapdragon 8+ Gen 1 processor allegedly includes a first contact plug ("CT") in a first interlayer dielectric (ILD) layer, with its top surface positioned higher than the top surface of the transistor gate.	¶72	col. 2:7-10
a second ILD layer disposed on the first ILD layer;	A second ILD layer of silicon oxide is allegedly disposed on the first ILD layer in the accused processor.	¶72	col. 2:10-10
a second contact plug disposed in the second ILD layer to electrically connect the first contact plug;	A second contact plug ("VCT") is allegedly disposed in the second ILD layer and connects to the first contact plug.	¶72	col. 2:10-11
and a third contact plug disposed in the first ILD layer and the second ILD layer to electrically connect the gate.	A third contact plug ("VCG") allegedly extends through both the first and second ILD layers to connect to the gate.	¶72	col. 2:11-13

• Identified Points of Contention:
  • Scope Questions: For the '140 patent, a central dispute may concern the definition of "crescent structure." The claim provides a detailed list of geometric constraints, and the infringement analysis will likely focus on whether the accused structures meet every recited constraint. For the '367 patent, a question may arise as to whether the structures identified as the "first ILD layer" and "second ILD layer" in the accused devices constitute distinct layers as contemplated by the patent, or if they are sub-layers of a single integrated dielectric stack.
  • Technical Questions: The infringement analysis for all asserted patents will heavily rely on evidence from structural and elemental analysis (e.g., TEM, EDS). A key technical question will be whether the plaintiff's reverse-engineering analysis accurately characterizes the accused structures and whether those characterizations demonstrate a one-to-one correspondence with the claimed elements. For example, for the '140 patent, the analysis will turn on whether the accused silicide layer actually has the specific sunken top surface, raised tips, and differential thickness required by the claim.

V. Key Claim Terms for Construction

• The Term: "crescent structure" ('140 Patent, Claim 1)

• Context and Importance: This term is the central feature of independent claim 1 of the '140 patent. The infringement allegation rests entirely on whether the accused silicide layer embodies this specific, complex geometry. Practitioners may focus on this term because its detailed definition within the claim itself provides significant material for claim construction arguments.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent also refers to the invention as a "smile structure," which could be argued to imply a more general shape rather than a strict geometric form ʼ140 Patent, col. 5:36
  • Evidence for a Narrower Interpretation: Claim 1 itself provides a highly detailed definition, acting as its own lexicography: "a curved bottom surface and a curved top surface, wherein both ... bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up ... and the silicide layer in the middle is thicker than the silicide layer in the peripheral." A defendant may argue this explicit definition strictly limits the claim scope to structures that meet all of these criteria. ʼ140 Patent, claim 1

• The Term: "a first interlayer dielectric (ILD) layer" and "a second ILD layer" ('367 Patent, Claim 1)

• Context and Importance: Claim 1 of the '367 patent requires two distinct ILD layers. The validity of the infringement read depends on mapping structures in the accused device to these two separate limitations. A defendant may argue that the accused device contains a single, integrated dielectric stack that does not meet the "two layer" requirement.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation (supporting two distinct layers): The elements are listed separately in the claim. Further, dependent claim 10 recites "an etch stop layer disposed between the first ILD layer and the second ILD layer" ʼ367 Patent, claim 10 The presence of an explicit intermediate layer strongly suggests the patent contemplates two structurally separate ILD layers. The complaint alleges the accused device has such an etch-stop layer Compl. ¶74
  • Evidence for a Narrower Interpretation (supporting a single integrated stack): A defendant could argue that while the specification describes a sequential formation process, the resulting structure is a functionally integrated unit. If the boundary between the alleged "first" and "second" layers is not structurally or materially distinct in the final product absent the etch-stop layer, it could raise the question of whether they constitute two separate "layers" as claimed.

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement for all asserted patents. Inducement is based on allegations that Samsung actively encourages infringement through marketing, technical support, and documentation for the Accused Processors and Products (e.g.,Compl. ¶64). Contributory infringement is based on the allegation that the Accused Processors are specialized components especially made for infringing the patents and are not staple articles of commerce with substantial non-infringing uses (e.g.,Compl. ¶65).
• Willful Infringement: Willfulness is alleged based on Samsung's knowledge of the patents and its infringement, at least as of the filing and service of the complaint Compl. ¶125 The complaint reserves the right to prove pre-suit knowledge based on factors such as Samsung's participation in semiconductor industry standards bodies, prior licensing communications, or its own reverse-engineering of competing devices Compl. ¶128

VII. Analyst's Conclusion: Key Questions for the Case

1. A question of structural and geometric correspondence: The case for several patents hinges on microscopic evidence. A central issue will be whether the physical structures within the accused processors, as revealed by plaintiff's reverse engineering, actually possess the specific, multi-part geometries recited in the claims, such as the '140 patent's "crescent structure" or the '267 patent's "three-section gate isolation structure."

2. A question of elemental mapping: For patents requiring multi-layer structures, such as the '367 and '100 patents, a key dispute will be whether the complex, integrated material stacks in the accused devices can be discretely mapped onto the separate elements recited in the claims. For example, does an accused dielectric stack with an intermediate etch-stop layer constitute "a first ILD layer" and "a second ILD layer" as two distinct claim limitations, or is it an indivisible structure that fails to meet the claim's requirements?

3. A question of foundry versus OEM liability: The complaint targets Samsung for infringement stemming from processors fabricated by both Samsung's own foundry and by third-party foundry TSMC. This raises questions about the nature and scope of Samsung's liability, distinguishing between direct infringement by "making" (for Samsung-fabricated chips) and by "using," "selling," or "importing" (for all accused chips), and how the facts support the comprehensive claims for indirect and willful infringement across this complex supply chain.