DCT

2:26-cv-00553

Netlist Inc v. Samsung Electronics Co Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:26-cv-00553, E.D. Tex., 07/06/2026
  • Venue Allegations: Venue is asserted based on Defendants' alleged regular and established places of business within the Eastern District of Texas, including facilities in Plano and Richardson, and the commission of infringing acts within the district.
  • Core Dispute: Plaintiff alleges that Defendant's DDR5 server memory modules infringe a patent related to memory module architecture with local, independently programmable clock synchronization.
  • Technical Context: The lawsuit concerns high-performance memory modules (DDR5 RDIMMs and MRDIMMs) used in servers, cloud computing, and AI applications, where signal timing and integrity are critical for speed and capacity.
  • Key Procedural History: The complaint is filed amidst extensive, ongoing litigation between Netlist and Samsung. This includes prior jury verdicts finding Samsung willfully infringed other Netlist patents related to memory technology, and separate, protracted contract litigation concerning a 2015 Joint Development and License Agreement (JDLA) that Netlist terminated in 2020. The complaint also references Samsung's unsuccessful arguments in prior cases that Netlist's patents were subject to RAND licensing obligations. Notably, the complaint for infringement of the patent-in-suit was filed on July 6, 2026, one day prior to the patent's stated issue date of July 7, 2026.

Case Timeline

Date Event
2013-07-27 '407 Patent Priority Date
2020-07-15 Netlist terminates JDLA with Samsung
2021-10-14 C.D. Cal. court finds Netlist's JDLA termination was effective
2023-04-01 E.D. Tex. jury finds Samsung willfully infringed five Netlist patents
2024-05-17 C.D. Cal. jury returns verdict finding Samsung materially breached the JDLA
2024-11-01 E.D. Tex. jury finds Samsung willfully infringed three other Netlist patents
2024-11-01 '407 Patent's underlying application ('410 Application) filed
2024-12-26 C.D. Cal. court grants Samsung's motion for a new trial in the JDLA case
2025-03-24 C.D. Cal. jury in new trial returns verdict for Netlist on JDLA breach
2025-09-30 Netlist files USITC complaint against Samsung alleging infringement
2026-07-06 Complaint Filed
2026-07-07 '407 Patent Issue Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,675,407 - "Memory Module with Local Clock Signals"

  • Patent Identification: U.S. Patent No. 12,675,407, "Memory Module with Local Clock Signals," issued July 7, 2026 (the "'407 Patent").

The Invention Explained

  • Problem Addressed: In high-density, high-speed memory modules, routing control and clock signals from a central controller to numerous memory chips can lead to timing variations (skew) due to unequal wire lengths and electrical loading, which compromises performance and limits density (Background, col. 2:7-29).
  • The Patented Solution: The invention describes a memory module architecture that decentralizes timing control. It uses on-module circuitry to receive a main system clock and then generate multiple, separate "local clocks." Each local clock is sent to a specific group of memory devices. Crucially, the phase relationship of each local clock relative to the system clock can be programmed independently, allowing for fine-tuned timing adjustments for each group of memory devices to compensate for signal skews across the module (Abstract; '407 Patent, col. 9:1-11).
  • Technical Importance: This approach of creating locally synchronized, independently adjustable timing domains on a memory module is designed to enable faster and more reliable operation for advanced memory standards like DDR5 Compl. ¶16 Compl. ¶30

Key Claims at a Glance

  • The complaint asserts at least Claim 1 of the '407 Patent Compl. ¶48
  • The essential elements of independent Claim 1 are:
    • A memory module operable in a computer system, comprising a printed circuit board (PCB), connectors, and memory devices organized in a plurality of groups.
    • Circuitry mounted on the PCB that is configurable to:
      • receive a system clock and control/address (C/A) signals from a memory controller;
      • generate module C/A signals;
      • generate a plurality of local clocks corresponding to the plurality of groups of memory devices;
      • the local clocks have respective phase relationships with the system clock that are programmable independently of each other;
      • output the module C/A signals to the memory devices; and
      • output the plurality of local clocks to their corresponding groups of memory devices (and not to other groups), with each group performing memory operations in accordance with its respective local clock.
  • The complaint does not explicitly reserve the right to assert dependent claims but makes allegations against "at least one of the claims" Compl. ¶48

III. The Accused Instrumentality

Product Identification

  • The complaint accuses Samsung's DDR5 memory modules, including DDR5 Registered Dual In-line Memory Modules (RDIMMs) and DDR5 Multiplexed Rank Dual In-line Memory Modules (MRDIMMs) Compl. ¶26 Specific examples include products with part numbers M321R8GA0PB0-CWM, M321R8GA0BB0-CQK, and M321R4GA3BB6-CQK Compl. ¶27

Functionality and Market Context

  • The accused products are high-performance memory modules for servers used in data-intensive applications like cloud computing and AI Compl. ¶18 Compl. ¶21 The complaint alleges these modules contain a printed circuit board, DRAM memory chips, and critical circuitry in the form of a Registering Clock Driver (RCD) or a Multiplexed Registering Clock Driver (MRCD) Compl. ¶29 This circuitry, sourced from third parties like Rambus, Montage, and Renesas, is alleged to buffer and re-drive clock and command/address signals from the memory controller to the DRAM chips on the module Compl. ¶60 Compl. ¶61 A screenshot from a Samsung marketing video shows an accused DDR5 RDIMM being installed into a server motherboard Compl. ¶73, p. 36

IV. Analysis of Infringement Allegations

'407 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a printed circuit board (PCB) having connectors configured to provide electrical connections between the memory module and the system bus; The accused DDR5 modules have a green printed circuit board with gold edge connections ("Gold Fingers") that connect to a motherboard's memory slot. ¶56; ¶57 col. 4:1-6
memory devices mounted on the PCB and organized in a plurality of groups, wherein a respective group of the memory devices is configurable to communicate data with the memory controller via a corresponding subset of the data signal lines; The accused modules integrate multiple DRAM chips, organized into groups (e.g., channels A & B), that communicate data over corresponding data signal lines (DQ[31:0]_A and DQ[31:0]_B). A visual from a Samsung presentation shows memory devices organized into groups. ¶58; ¶59 col. 5:21-27
circuitry mounted on the PCB and configurable to: receive from the memory controller a system clock...and input control and address (C/A) signals... The accused modules include an RCD or MRCD chip that receives clock, command, and address signals from the system memory controller. ¶60; ¶63 col. 10:11-19
generate module C/A signals in response to the input C/A signals; The RCD/MRCD on the accused modules buffers and re-drives the input C/A signals, generating module C/A signals for output to the DRAM devices. A diagram from a Renesas brochure illustrates the RCD generating output C/A signals. ¶64; ¶29 col. 3:21-29
generate a plurality of local clocks corresponding, respectively, to the plurality of groups of the memory devices... The RCD is alleged to produce four separate clock pairs for the DRAM channels, which are alleged to be the "plurality of local clocks." ¶68 col. 9:1-5
the plurality of local clocks having respective phase relationships with the system clock, the respective phase relationships being programmable independently of each other; The complaint alleges the phase relationships of the output clocks from the RCD/MRCD are independently programmable for each channel using "control words" as specified in JEDEC standards. The complaint includes a table from a JEDEC standard showing control words for output delay. ¶66; ¶67; ¶30 col. 9:5-8
output the plurality of local clocks to the memory devices, wherein a respective local clock...is output to a corresponding group of the memory devices and not to any other group... The RCD is alleged to distribute specific clock pairs to corresponding DRAM channels (groups of memory devices), and not to other channels. ¶68 col. 9:43-50
the corresponding group of the memory devices is configurable to perform memory read or write operations by communicating data signals with the memory controller...in accordance with the respective local clock. The complaint cites JEDEC timing diagrams to allege that read/write operations for a group of memory devices are performed in accordance with the respective local clock signal received by that group. ¶70; ¶71 col. 18:36-43
  • Identified Points of Contention:
    • Scope Questions: A central question will be whether the combination of components on the accused modules-specifically the RCD/MRCD chips (sourced from third parties) and associated traces-constitutes the claimed "circuitry." The defense may argue that the claims require a specific circuit structure not present in the accused products.
    • Technical Questions: The infringement theory relies heavily on the functionality of the RCD/MRCD components as defined by JEDEC standards. A key technical question is whether programming the RCD/MRCD via standardized "control words" to adjust output timing Compl. ¶66 is functionally equivalent to the claimed feature that "phase relationships being programmable independently of each other." The court may need to determine if there is a substantive difference between adjusting "output delay" as described in the JEDEC standard and programming a "phase relationship" as claimed in the patent.

V. Key Claim Terms for Construction

  • The Term: "circuitry... configurable to... generate a plurality of local clocks"

  • Context and Importance: This term is the functional core of the invention. The definition will determine whether the accused RCDs/MRCDs, which buffer and re-drive clocks, fall within the claim scope. Practitioners may focus on this term because the infringement theory depends on equating the accused RCD/MRCD with the claimed "circuitry."

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification describes the "circuitry" in functional terms, such as "a module control circuit (module controller or module control device) 116" and "data buffers 118" working together (col. 3:62-66; col. 4:42-49). This may support an interpretation that covers a collection of discrete components that collectively perform the claimed function.
    • Evidence for a Narrower Interpretation: The patent also discloses specific circuit diagrams for implementing the timing adjustments, such as a "DB Control circuit 310" (Fig. 3) and a "dynamic delay control circuit 650" (Fig. 13). The defense may argue these specific embodiments limit the scope of "circuitry" to a structure that more closely mirrors these diagrams, potentially distinguishing it from the accused RCDs.

  • The Term: "programmable independently of each other"

  • Context and Importance: This limitation defines the required level of control over the local clocks' phase relationships. The dispute will likely center on whether the method of programming the accused RCDs via JEDEC control words meets this requirement.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification states that the data buffers have "programmable control of the timing of read/write data signals and the phase of the locally synchronized clock signal" (col. 10:21-25), suggesting a focus on the functional outcome of programmability rather than the specific mechanism.
    • Evidence for a Narrower Interpretation: The specification details a training method where a "proper phase adjustment can be programmed" into data buffers (col. 14:11-18). The defense could argue this implies a specific type of direct programmability or a training routine that differs from the operation of the accused JEDEC-compliant devices. The use of "control words" in the accused products Compl. ¶67 might be argued as a standardized, less-flexible configuration rather than being fully "programmable independently."

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement through Samsung's affirmative acts of providing specifications, datasheets, marketing materials, and instruction manuals that allegedly encourage and facilitate the use of the Accused DDR5 Products by customers in an infringing manner Compl. ¶73 Compl. ¶75 Contributory infringement is also alleged, based on the assertion that the accused products are a material part of the invention and have no substantial non-infringing use Compl. ¶77
  • Willful Infringement: Willfulness is alleged based on Samsung's purported pre-suit knowledge of the '407 patent family and pending applications, its alleged practice of monitoring Netlist's patent filings, and the extensive history of patent litigation between the parties Compl. ¶78 Compl. ¶40 The filing of the complaint itself is also cited as providing notice Compl. ¶78

VII. Analyst's Conclusion: Key Questions for the Case

  • A threshold procedural question will be one of jurisdiction: can the court hear a patent infringement claim that was filed one day prior to the patent's official issue date, given that an action for infringement can only be brought for acts occurring during the patent's term?
  • A central issue will be one of claim scope: can the term "circuitry", as described in the '407 patent, be construed to read on the accused DDR5 modules' architecture, which includes Registering Clock Drivers (RCDs) and Multiplexed Registering Clock Drivers (MRCDs) sourced from third-party manufacturers?
  • A key evidentiary question will be one of technical equivalence: does the functionality of the accused RCDs and MRCDs, which use standardized JEDEC "control words" to adjust output signal timing, meet the claim requirement of generating "local clocks" with "phase relationships being programmable independently of each other," or is there a material difference in the method and degree of programmability?
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