ImberaTek LLC v. Sony Group Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Imberatek LLC (Texas)
  • Defendant: Sony Group Corp and Sony Corp (Japan)
  • Plaintiff's Counsel: McANDREWS, HELD & MALLOY, LTD.
• Case Identification: 2:26-cv-00547, E.D. Tex., 07/02/2026
• Venue Allegations: Venue is alleged to be proper under 28 U.S.C. § 1391(c)(3) because the Defendants are foreign corporations and may be sued in any judicial district.
• Core Dispute: Plaintiff alleges that Defendants' Xperia series smartphones, and specifically their internal semiconductor components, infringe four patents related to advanced semiconductor packaging and embedded electronic module technology.
• Technical Context: The technology at issue involves methods for embedding semiconductor components within circuit boards, a key process for achieving the miniaturization and high-density interconnections required in modern mobile devices.
• Key Procedural History: The complaint details extensive pre-suit licensing negotiations beginning in January 2021, which included the execution of a non-disclosure agreement (NDA) in September 2023 and the provision of detailed infringement claim charts by the Plaintiff to the Defendant in November 2023. Plaintiff characterizes Defendants' response during this period as "holdout behavior," which forms the basis for its willful infringement allegations.

Case Timeline

Date	Event
2003-02-26	Earliest Priority Date ('527 Patent)
2003-04-01	Earliest Priority Date ('723 Patent)
2004-08-05	Earliest Priority Date ('194 Patent)
2008-05-12	Earliest Priority Date ('324 Patent)
2009-10-27	'527 Patent Issued
2012-07-17	'723 Patent Issued
2013-07-16	'194 Patent Issued
2015-08-11	'324 Patent Issued
2021-01-27	Plaintiff allegedly sent initial notice letter to Defendants
2021-03-04	Defendants allegedly responded, requesting claim charts
2023-08-24	Plaintiff allegedly offered to provide claim charts under an NDA
2023-09-28	Plaintiff and Defendants allegedly executed an NDA
2023-11-06	Plaintiff allegedly sent detailed claim charts to Defendants
2024-03-19	Defendants allegedly sent written questions on the claim charts
2024-10-22	Plaintiff allegedly provided notice regarding the '194 Patent
2026-07-02	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,609,527 - Electronic Module, Issued October 27, 2009

The Invention Explained

• Problem Addressed: The patent's background section describes technical challenges in connecting unpackaged semiconductor components directly to circuit boards, such as mechanical stress and alignment difficulties associated with prior art methods like flip-chip (FC) technology and creating feed-throughs in insulation layers '527 Patent, col. 1:8-21 '527 Patent, col. 1:40-54
• The Patented Solution: The invention proposes an electronic module where a component with flat contact zones is embedded within an insulating layer. Electrical connections are made using "solid contact bumps" that are "solderlessly made" on both the component's flat contacts and a conductive-pattern layer, creating a direct, embedded, and solderless connection between the two sets of bumps '527 Patent, abstract '527 Patent, col. 6:50-65
• Technical Importance: This approach aimed to create more reliable, durable, and densely packed electronic modules by embedding components directly into the board structure without the need for traditional solder '527 Patent, col. 3:36-40

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶59
• The essential elements of Claim 1 are:
  • An electronic module, comprising:
  • a first conductive-pattern layer having a first surface;
  • first solid contact bumps solderlessly made on the first surface of the first conductive-pattern layer and metallurgically and electrically connected thereto;
  • a component having flat contact zones;
  • second solid contact bumps solderlessly made on the flat contact zones and metallurgically and electrically connected thereto;
  • an insulating-material layer on the first surface of the first conductive pattern layer; and
  • wherein the component is embedded in the insulating-material layer and the second solid contact bumps are metallurgically, electrically and solderlessly connected to the first solid contact bumps.
• The complaint alleges infringement of "one or more claims" of the '527 Patent, reserving the right to assert additional claims Compl. ¶59

U.S. Patent No. 8,222,723 - Electronic Module Having A Conductive Pattern Layer, Issued July 17, 2012

The Invention Explained

• Problem Addressed: The patent addresses the need for a simple and economical method for manufacturing reliable electronic modules with embedded components '723 Patent, col. 2:56-62
• The Patented Solution: The patent describes an electronic module where a component is embedded within an insulating layer and connected to a conductive-pattern layer. The connection is formed by creating holes through two distinct adhesive layers and filling the holes with a conductive material. Critically, the invention requires that the "first hardened adhesive layer" (on the component) and the "second hardened adhesive layer" (on the conductive-pattern layer) have different compositions '723 Patent, abstract '723 Patent, col. 5:19-37
• Technical Importance: The use of two different adhesive compositions allows for the optimization of material properties, such as adhesion and thermal conductivity, for both the component and the circuit board substrate, potentially improving manufacturing yield and device reliability '723 Patent, col. 3:1-14

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶76
• The essential elements of Claim 1 are:
  • An electronic module, comprising: a conductive-pattern layer; an insulating-material layer supporting it; and at least one component inside the insulating layer with a first surface and contact zones.
  • A first hardened adhesive layer on the first surface of the component.
  • A second hardened adhesive layer in contact with the conductive-pattern layer and the first hardened adhesive layer.
  • Holes in the first and second hardened adhesive layers at the locations of the contact zones.
  • Conductive material in the holes creating an electrical connection.
  • A final limitation requires that the first hardened adhesive layer has a first composition and the second hardened adhesive layer has a second composition different from the first.
• The complaint alleges infringement of "one or more claims" of the '723 Patent Compl. ¶76

Multi-Patent Capsule: U.S. Patent No. 9,107,324

• Patent Identification: U.S. Patent No. 9,107,324, Circuit Module and Method of Manufacturing the Same, Issued August 11, 2015 Compl. ¶41
• Technology Synopsis: The '324 Patent is directed to a circuit module with an embedded component where the contact elements connecting the component to the conductors include an "intermediate layer." This intermediate layer contains a "third metal" that is different from both the "first metal" of the component's contact terminals and the "second metal" of the conductors, a structure designed to improve reliability when joining dissimilar metals like aluminum and copper '324 Patent, abstract Compl. ¶94 The claims also require a specific geometry where the contact area between the intermediate layer and the terminal is smaller than the surface area of the terminal itself Compl. ¶101
• Asserted Claims: At least Claim 17 is asserted Compl. ¶96
• Accused Features: The PMIC components within the Accused Products are alleged to infringe, specifically their multi-layer contact structures Compl. ¶¶97-104

Multi-Patent Capsule: U.S. Patent No. 8,487,194

• Patent Identification: U.S. Patent No. 8,487,194, Circuit Board Including An Embedded Component, Issued July 16, 2013 Compl. ¶40
• Technology Synopsis: The '194 Patent describes a circuit board with an embedded component where the electrical connection features a unique configuration. Specifically, it claims a "plurality of individual contact elements" that connect to "at least one single contact area," creating a many-to-one connection between the board's conductive layer and the component's contact pad '194 Patent, abstract Compl. ¶115 This structure may enhance connection reliability and fault tolerance.
• Asserted Claims: At least Claim 1 is asserted Compl. ¶117
• Accused Features: Both PMIC and Application Processor (AP) components within the Accused Products are alleged to have contact structures that meet the claims of the '194 Patent Compl. ¶¶118-122

III. The Accused Instrumentality

• Product Identification: The Accused Products are various models of Sony's Xperia series smartphones, including the Xperia 5 II, 5 III, 5 IV, PRO, PRO-I, 1 II, 1 III, 1 IV, and 1 V Compl. ¶28 The complaint also identifies specific internal components as infringing, including various Power Management Integrated Circuits (PMICs) and an Application Processor (AP) Compl. ¶43
• Functionality and Market Context: The Accused Products are commercial smartphones sold in the United States Compl. ¶¶11-12 The allegedly infringing functionality is not user-facing but lies in the physical construction and packaging of the semiconductor chips inside the devices Compl. ¶43 The complaint alleges that the PMICs and APs within these phones are manufactured using embedded packaging techniques that practice the patented inventions Compl. ¶45 For example, the complaint provides a photograph from a product teardown showing a Qualcomm PM8350 PMIC on the main logic board of a Sony Xperia 5 III Compl. ¶43 Compl. Ex. 7, p. 21

IV. Analysis of Infringement Allegations

'527 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
An electronic module, comprising: a first conductive-pattern layer having a first surface,	The accused PMICs are identified as electronic modules containing a copper conductive-pattern layer, as shown in cross-sections and confirmed by Energy Dispersive X-Ray (EDX) maps.	¶60	col. 6:40-45
first solid contact bumps solderlessly made on the first surface of the first conductive-pattern layer and metallurgically and electrically connected thereto,	The accused PMICs allegedly have solid contact bumps made via a solderless plating process, evidenced by the absence of tin in EDX maps, which connect to the conductive-pattern layer.	¶61	col. 5:27-32
a component having flat contact zones,	The accused PMICs are alleged to have a component with flat contact zones, as shown in cross-sectional images.	¶62	col. 5:10-15
second solid contact bumps solderlessly made on the flat contact zones and metallurgically and electrically connected thereto,	The accused PMICs allegedly have a second set of solid contact bumps, also made solderlessly, on the component's flat contact zones, as shown by the absence of tin in EDX maps.	¶63	col. 5:10-15
an insulating-material layer on the first surface of the first conductive-pattern layer,	The accused PMICs are alleged to contain an insulating layer on the conductive layer's surface, with EDX maps showing the presence of insulating materials such as oxygen (O) and silicon (Si).	¶64	col. 4:45-49
wherein the component is embedded in the insulating-material layer and wherein the second solid contact bumps made on the flat contact zones of the component are metallurgically, electrically and solderlessly connected to the first solid contact bumps made on the first surface of the first conductive-pattern layer.	Cross-sections allegedly show the component embedded in the insulating layer, with the first and second sets of bumps connected to each other without solder. An EDS map shows the solderless connection Compl. Ex. 7, p. 32	¶65	col. 6:50-65

• Identified Points of Contention:
  • Scope Questions: A central dispute may revolve around the term "solderlessly made". The complaint's theory relies on showing the absence of tin (a common element in solder) to prove this limitation. The defense may argue that the term is limited to the specific embodiments disclosed in the patent, such as ultrasonic welding or thermo-compression, and that the accused plating process is distinct.
  • Technical Questions: The analysis will question whether the structures identified as "solid contact bumps" in the accused products meet the claimed functional and structural requirements, and whether the alleged metallurgical and electrical connection is achieved in the manner claimed.

'723 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
An electronic module, comprising: a conductive-pattern layer; an insulating-material layer supporting the conductive-pattern layer; at least one component inside the insulating-material layer...	The accused PMICs are identified as electronic modules containing a conductive layer, an insulating layer, and an embedded component, as shown in cross-sections.	¶¶77-79	col. 5:5-18
a first hardened adhesive layer on the first surface of the at least one component;	Cross-sections of the accused PMICs allegedly show a first hardened adhesive layer on the surface of the embedded component.	¶80	col. 5:19-21
a second hardened adhesive layer in contact with the conductive-pattern layer and the first hardened adhesive layer;	Cross-sections of the accused PMICs allegedly show a second hardened adhesive layer in contact with both the first adhesive layer and the conductive-pattern layer.	¶81	col. 5:22-25
holes in the first and second hardened adhesive layer at the locations of the contact zones;	The accused PMICs are alleged to have holes formed through both adhesive layers, located at the component's contact zones.	¶82	col. 5:26-28
conductive material in the holes and in electrical connection with the contact zones of the component and the conductive-pattern layer,	An EDX map allegedly shows copper as the conductive material filling the holes and forming an electrical connection Compl. Ex. 7, p. 87	¶83	col. 5:29-33
wherein the first hardened adhesive layer has a first composition and the second hardened adhesive layer has a second composition different from the first composition.	The complaint alleges this is demonstrated by different textures in a Scanning Electron Microscope (SEM) image and different colors in an EDX layered map Compl. Ex. 7, p. 88	¶84	col. 5:34-37

• Identified Points of Contention:
  • Scope Questions: The case may turn on the construction of "a second composition different from the first composition." The question for the court will be what degree and type of difference is required to meet this limitation and whether visual differences in SEM/EDX images are sufficient proof.
  • Technical Questions: A key evidentiary question will be whether the different textures and colors observed in the plaintiff's reverse engineering analysis are indicative of a deliberate, functional difference in material composition as required by the claim, or if they are merely incidental artifacts of the manufacturing process.

V. Key Claim Terms for Construction

For the '527 Patent

• The Term: "solderlessly made"
• Context and Importance: This term is fundamental to the novelty of Claim 1. The infringement analysis hinges on whether the accused manufacturing process, which the complaint implies is a plating technique, falls within the scope of "solderless." Practitioners may focus on this term because it distinguishes the invention from prior art soldering methods.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent specification repeatedly contrasts the invention with traditional soldering, emphasizing the avoidance of high temperatures and molten metal '527 Patent, col. 4:20-29 This language may support an interpretation that any connection process not involving traditional solder is "solderless."
  • Evidence for a Narrower Interpretation: The specification explicitly discloses specific solderless methods like "ultrasonic welding, thermo-compression, or some other such method" '527 Patent, col. 4:23-26 A defendant may argue the term should be limited to these disclosed examples or to methods involving direct mechanical bonding, potentially excluding a plating process.

For the '723 Patent

• The Term: "a second composition different from the first composition"
• Context and Importance: This limitation is the central feature of independent claim 1. Infringement depends entirely on proving that two separate adhesive layers in the accused products have compositions that are legally "different."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language itself does not quantify the required difference, which may support an argument that any detectable variation in chemical or physical properties suffices. The patent abstract simply states the compositions are "different" '723 Patent, abstract
  • Evidence for a Narrower Interpretation: The patent specification suggests that different adhesives may be selected to optimize distinct properties, such as "thermal conductivity, thermal expansion coefficient, mechanical strength," etc. '723 Patent, col. 3:9-14 A defendant may argue that the "difference" must be material and functional, not merely an incidental variation shown in an SEM image.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement against Sony, stating that it actively encourages infringement by providing marketing materials, technical specifications, and user manuals for the Accused Products with knowledge of the patents and that the use of the products constitutes infringement Compl. ¶68 Compl. ¶87 Compl. ¶108 Compl. ¶126 The complaint also alleges contributory infringement, stating that the accused PMIC and AP components are material components of the inventions, are not staple articles of commerce, and are known to be especially made for use in an infringing manner Compl. ¶69 Compl. ¶88 Compl. ¶109 Compl. ¶127
• Willful Infringement: The complaint makes detailed allegations of willful infringement based on pre-suit knowledge. It asserts that Sony had actual notice of the Asserted Patents and their infringement since at least January 27, 2021, and received detailed claim charts for multiple patents on November 6, 2023, following the execution of an NDA Compl. ¶¶46-51 The complaint alleges that Sony continued to infringe despite this knowledge and engaged in "holdout behavior," thereby creating an objectively high likelihood that its actions constituted infringement of valid patents Compl. ¶50 Compl. ¶67

VII. Analyst's Conclusion: Key Questions for the Case

1. A central issue will be one of definitional scope: How will the court construe the term "solderlessly made" in the '527 patent and the requirement for "different" adhesive compositions in the '723 patent? The outcome of the infringement analysis for the lead patents will likely depend heavily on these claim construction rulings.

2. A key evidentiary question will be one of technical proof: Can the plaintiff's reverse-engineering evidence, based on SEM and EDX analysis of accused chips, definitively prove that the microscopic structures and material compositions within Sony's mass-produced commercial products meet every limitation of the asserted claims? The defense will likely challenge whether these analyses accurately reflect a functionally "different" composition or a "solderless" connection as legally required by the claims.

3. A major legal question will be one of willfulness and intent: Given the extensive pre-suit correspondence documented in the complaint, including the provision of claim charts under an NDA, a critical issue for trial will be whether Sony's conduct rises to the level of willful infringement, which could expose it to the risk of enhanced damages.