Mare Infinitus Tech LLC v. Samsung Electronics Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Mare Infinitus Technologies LLC (Texas)
  • Defendant: Samsung Electronics Co., Ltd. (Republic of Korea); Samsung Electronics America, Inc. (New York); Samsung Semiconductor, Inc. (California)
  • Plaintiff's Counsel: Kent & Risley LLC
• Case Identification: 2:26-cv-00504, E.D. Tex., 06/24/2026
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendants have committed acts of patent infringement in the district and maintain regular and established places of business in the district, specifically referencing locations in Plano, Texas.
• Core Dispute: Plaintiff alleges that Defendant's High Bandwidth Memory (HBM) products infringe patents related to the structure and manufacturing method of vertical interconnections within semiconductor packages.
• Technical Context: The technology relates to through-silicon vias (TSVs), a critical component for vertically stacking semiconductor dies to create high-density, high-performance devices like HBM, which is essential for the AI and high-performance computing markets.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date	Event
2012-11-13	Priority Date for '164 and '982 Patents
2015-12-08	'164 Patent Issued
2016-03-01	'982 Patent Issued
2026-06-24	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,209,164 - "Interconnection structure of package structure and method of forming the same"

• Issued: December 8, 2015

The Invention Explained

• Problem Addressed: The patent's background section describes that traditional methods for forming through-silicon vias (TSVs) often rely on vacuum techniques, such as plasma vapor deposition, to create a seed layer for electroplating. This process requires "high-priced equipment, which increases device costs" '164 Patent, col. 1:45-51
• The Patented Solution: The invention proposes a package structure and a corresponding manufacturing method that avoids costly vacuum deposition. It describes forming a "first pad" over the opening of a via-hole, and then using that pad as a seed layer for a subsequent electroplating process that fills the hole to create a "via structure" '164 Patent, col. 4:59-col. 5:2 The claimed structure specifies that this resulting via structure is disposed within the via-hole "without exceeding the first opening" on the top side of the device '164 Patent, abstract '164 Patent, Fig. 1F
• Technical Importance: This approach aims to lower the manufacturing cost of 3D-stacked semiconductor packages by replacing an expensive vacuum deposition step with a less complex and more cost-effective screen printing and electroplating process.

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶23
• The essential elements of independent claim 1 include:
  • A first semiconductor device with a first semiconductor substrate, a first electronic device, and a via-hole formed completely through it.
  • An interconnection structure comprising a via structure within the via-hole that does not exceed the via-hole's first opening.
  • A first pad on the first side of the device, covering the via-hole, adjoined to the via structure, electrically connected to the first electronic device, and disposed on the "same level" as the first electronic device.
  • A second semiconductor device that is vertically integrated with the first semiconductor device.
• The complaint does not explicitly reserve the right to assert dependent claims but makes general allegations of infringement of "one or more claims" Compl. ¶26

U.S. Patent No. 9,275,982 - "Method of forming interconnection structure of package structure"

• Issued: March 1, 2016

The Invention Explained

• Problem Addressed: As a divisional of the '164 Patent, the '982 Patent addresses the same problem: the high cost associated with conventional TSV fabrication methods that require vacuum deposition equipment '982 Patent, col. 1:50-58
• The Patented Solution: This patent claims the method of creating the cost-effective interconnection structure. The core of the claimed method is a specific sequence of steps: first "forming a first pad covering the first opening" of the via-hole, and then "forming a via structure in the via-hole subsequent to forming the first pad" '982 Patent, claim 1 This sequence enables the pad to be used as a seed layer for electroplating the via structure, thereby bypassing the need for a separate, expensive vacuum deposition step to create a seed layer '982 Patent, col. 4:1-5, referencing Fig. 1F
• Technical Importance: The invention provides a specific, ordered manufacturing process intended to reduce the cost and complexity of producing 3D-stacked semiconductor devices.

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶36
• The essential elements of independent claim 1 include:
  • Providing a first semiconductor device.
  • Forming a via-hole through the device.
  • Forming a first pad that covers the opening of the via-hole.
  • Forming a via structure inside the via-hole subsequent to forming the first pad.
  • Vertically integrating the first semiconductor device with a second semiconductor device.
• The complaint makes general allegations of infringement of "one or more claims" of the patent Compl. ¶39

III. The Accused Instrumentality

Product Identification

• Samsung High Bandwidth Memory ("HBM") and "substantially similar products," with HBM3 being specifically noted Compl. ¶3 Compl. ¶23 Compl. ¶36

Functionality and Market Context

• The complaint alleges these are commercial memory products supplied for use in high-performance Artificial Intelligence Graphics Processing Units (AI GPUs), such as the AMD MI series Compl. ¶3 HBM technology relies on stacking multiple memory dies vertically and connecting them with TSVs, enabling very high memory bandwidth, which is crucial for AI and data center applications Compl. ¶3 The complaint alleges these products are marketed, sold, and distributed throughout the United States, including within the Eastern District of Texas Compl. ¶3

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint. The complaint references claim chart exhibits that were not included in the filing Compl. ¶24 Compl. ¶37 The following analysis is based on the narrative allegations.

'164 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a first semiconductor device comprising a first semiconductor substrate and a first electronic device... the first semiconductor device has a via-hole formed completely through the first semiconductor device...	The Samsung HBM products are alleged to be composed of stacked semiconductor dies, where each die functions as a "first semiconductor device" containing a substrate, electronic circuits, and through-silicon vias (TSVs), which are the "via-holes."	¶23; ¶24	col. 3:1-49
an interconnection structure... comprises: a via structure disposed in the via-hole without exceeding the first opening;	The TSVs in the accused HBM products allegedly contain a conductive "via structure" that is confined within the boundaries of the via opening on the top surface of the die.	¶23; ¶24	col. 4:7-14
a first pad disposed on the first side of the first semiconductor device and covering the via-hole... adjoined to the via structure... electrically connected to the first electronic device, and the first pad and the first electronic device are disposed on the same level...	The accused HBM products are alleged to have a conductive pad on the surface that covers the TSV, is connected to it, and is connected to the die's electronic circuitry at the same planar level.	¶23; ¶24	col. 4:59-col. 5:2
a second semiconductor device vertically integrated with the first semiconductor device...	The accused HBM products are inherently stacked-die devices, where a "second semiconductor device" (another die) is vertically integrated on top of the "first semiconductor device."	¶23; ¶24	col. 7:15-23

'982 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
providing a first semiconductor device...	The manufacturing process for Samsung HBM products allegedly begins with providing a semiconductor die.	¶36; ¶37	col. 3:1-4
forming a via-hole through the first semiconductor device...	The manufacturing process allegedly includes etching or drilling to create the through-silicon vias (TSVs).	¶36; ¶37	col. 3:40-49
forming a first pad covering the first opening;	The manufacturing process allegedly involves creating a conductive pad over the opening of the newly formed via-hole.	¶36; ¶37	col. 3:59-62
forming a via structure in the via-hole subsequent to forming the first pad...	The manufacturing process allegedly uses the previously formed pad as a seed layer for an electroplating step that fills the via-hole to create the conductive via structure.	¶36; ¶37	col. 3:63-col. 4:2
substantially vertically integrating the first semiconductor device with a second semiconductor device.	The manufacturing process allegedly concludes with stacking and bonding a second die on top of the first.	¶36; ¶37	col. 7:15-23

• Identified Points of Contention:
  • Structural Scope: For the '164 Patent, a potential point of contention is the claim limitation requiring the "first pad" and the "first electronic device" to be "disposed on the same level." The defense may argue that the topology of the accused HBM products does not meet this specific spatial arrangement.
  • Methodological Sequence: For the '982 Patent, infringement hinges on proving the specific temporal sequence of the manufacturing steps. A key question will be whether Plaintiff can produce evidence that Samsung's process forms the via structure subsequent to forming the pad, as opposed to a simultaneous or different sequential process.

V. Key Claim Terms for Construction

• The Term: "without exceeding the first opening" '164 Patent, claim 1

• Context and Importance: This term defines a critical geometric constraint on the via structure. Infringement requires the conductive filling of the via-hole to remain within the lateral confines of the hole's opening on one side. Practitioners may focus on this term because high-resolution imaging of the accused device's cross-section could reveal a structure that flares beyond the opening, potentially supporting a non-infringement argument.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent does not provide explicit language supporting a broader, non-literal interpretation of this geometric limit.
  • Evidence for a Narrower Interpretation: The specification states that because the via structure is formed after the pad, it "does not exceed the first opening" '164 Patent, col. 4:10-12 Figure 1F, which illustrates this, depicts the via structure (132) as being flush with or recessed from the edge of the first opening (111), strongly suggesting a literal geometric boundary.

• The Term: "subsequent to forming the first pad" '982 Patent, claim 1

• Context and Importance: This term establishes a specific, required order of operations in the claimed manufacturing method. The case for infringement of the '982 patent depends entirely on proving this sequence is practiced. Practitioners may focus on this term because it is the core of the asserted process invention and any evidence of a different manufacturing order would be a strong defense.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent does not appear to offer language that would broaden the clear temporal meaning of "subsequent to."
  • Evidence for a Narrower Interpretation: The specification describes the purpose of this sequence: "an electroplating process is performed using the first pad 130 as a seed layer to deposit a via structure 132" ('164 Patent, col. 3:63-col. 4:2, which the '982 patent incorporates). This ties the "subsequent" step directly to the inventive concept of using the pad as a seed layer, reinforcing a strict, literal interpretation of the process order.

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement for both patents Compl. ¶25 Compl. ¶29 Compl. ¶38 Compl. ¶42 The basis for inducement includes allegations that Samsung promotes, advertises, and provides instructions for the HBM products, knowing their intended use will infringe Compl. ¶27 Compl. ¶40 Contributory infringement is alleged on the basis that the HBM products are not staple articles of commerce and are especially made for an infringing use Compl. ¶29 Compl. ¶42
• Willful Infringement: Willfulness is alleged based on both post-suit and alleged pre-suit knowledge. The complaint asserts that Defendants "knew of the existence of the... Patent or at least should have known... but were willfully blind to its existence" prior to the lawsuit Compl. ¶28 Compl. ¶41 It further claims infringement has been willful and deliberate "at least as early as the filing of this action" Compl. ¶30 Compl. ¶43

VII. Analyst's Conclusion: Key Questions for the Case

• A central issue will be one of structural and topological proof: can the Plaintiff demonstrate through technical analysis that the internal structure of Samsung's HBM products precisely matches the claimed architecture of the '164 patent, particularly the geometric constraint that the "via structure" is formed "without exceeding the first opening" and the spatial arrangement of the "pad" and "electronic device" on the "same level"?

• A second core issue will be one of methodological evidence: for the '982 patent, can the Plaintiff obtain and present evidence, likely through extensive and contested discovery into Samsung's proprietary manufacturing lines, proving that Samsung's process follows the exact temporal sequence of "forming a via structure... subsequent to forming the first pad," as required by claim 1?