DCT

2:26-cv-00456

Netlist Inc v. Samsung Electronics Co Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:26-cv-00456, E.D. Tex., 06/08/2026
  • Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendants are subject to personal jurisdiction, maintain regular and established places of business in the district (specifically facilities in Plano and Richardson, Texas), and have committed acts of infringement within the district. The complaint also references prior litigation between the parties in the same venue.
  • Core Dispute: Plaintiff alleges that Defendants' DDR5 server memory modules infringe a patent related to methods for a memory subsystem to provide distinct signaling to a host system controller during initialization and normal operations.
  • Technical Context: The lawsuit concerns high-performance memory modules (e.g., RDIMMs) used in servers for cloud computing and other data-intensive applications, a market where efficiency and reliability are critical.
  • Key Procedural History: The complaint is filed against a backdrop of extensive litigation between Netlist and Samsung. It references a 2015 Joint Development and License Agreement (JDLA) that was terminated, multiple prior jury verdicts in E.D. Tex. finding Samsung and Micron infringed other Netlist patents, and an ongoing dispute over whether Netlist's patents are subject to reasonable and non-discriminatory (RAND) licensing obligations under JEDEC standards.

Case Timeline

Date Event
2009-06-12 '937 Patent Priority Date
2020-07-15 Netlist terminates JDLA with Samsung
2023-04-01 Jury finds Samsung willfully infringed five Netlist patents, awarding $303.15 million
2024-01-01 Jury awards Netlist $445 million in damages against Micron
2024-11-01 Jury finds Samsung willfully infringed three other Netlist patents, awarding $118 million
2026-06-08 Complaint Filing Date
2026-06-09 '937 Patent Issue Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,650,937 - "Memory Module Operable to Provide Distinct Signaling Interfaces Via an Open-Drain Output for Distinct Operations"

  • Patent Identification: U.S. Patent No. 12,650,937 ("Memory Module Operable to Provide Distinct Signaling Interfaces Via an Open-Drain Output for Distinct Operations"), issued June 9, 2026.

The Invention Explained

  • Problem Addressed: The patent addresses inefficiencies during computer system initialization where a system memory controller must perform "blind execution," meaning it must pause and wait for a predetermined period for a memory module to complete internal tasks (like training sequences) without receiving any feedback on the task's actual status or completion time '937 Patent, col. 3:1-27 This can lead to unnecessary delays.
  • The Patented Solution: The invention describes a memory subsystem that uses a single open-drain output pin to provide two different types of signals depending on the operational mode. During normal operation, the pin functions as a standard error-out signal (a "first signaling interface"). However, during an initialization operation, the same pin is used to send a distinct notification signal back to the system memory controller (a "second signaling interface"), providing feedback on the status of the initialization sequence '937 Patent, abstract '937 Patent, col. 7:1-30 This creates a handshake mechanism that eliminates blind waiting without requiring new hardware pins.
  • Technical Importance: This dual-use signaling method allows for more efficient and responsive system initialization while reducing design cost and complexity by repurposing an existing hardware interface '937 Patent, col. 8:35-44

Key Claims at a Glance

  • The complaint asserts at least independent Claim 1 Compl. ¶46
  • The essential elements of Claim 1 include:
    • A memory subsystem with a printed circuit board, dynamic random access memory (DRAM) elements, and a memory subsystem controller.
    • The memory subsystem controller has an open-drain output coupled to an error signal line.
    • The controller provides a "signaling interface" for normal read/write operations and a "feedback path" for initialization sequences, both via the same open-drain output.
    • During normal operations, the controller can output a parity error signal.
    • During initialization, the controller outputs distinct signals (e.g., timed low-logic pulses) corresponding to different parts of the initialization sequence.
    • During normal read/write operations, data signals are transmitted in response to control/address (C/A) signals.
    • During the initialization operation, the subsystem does not respond to C/A signals by transmitting data signals.
  • The complaint reserves the right to assert additional claims Compl. ¶46

III. The Accused Instrumentality

Product Identification

  • The accused instrumentalities are Samsung's DDR5 memory products, including DDR5 Registered Dual In-line Memory Modules (RDIMMs) Compl. ¶26 A specific example cited is Samsung Product Part No. M321R8GA0BB0-CQK Compl. ¶26

Functionality and Market Context

  • The accused products are high-performance memory modules designed for servers in enterprise and data-center environments Compl. ¶18 Compl. ¶49 The complaint alleges that these RDIMMs include a printed circuit board, DRAM devices, and a memory subsystem controller called a Registered Clock Driver (RCD) Compl. ¶27 Compl. ¶50 The complaint asserts that these products are designed to comply with JEDEC industry standards for DDR5 memory, which define their physical layout, electrical requirements, and signaling protocols Compl. ¶48 A product image shows a Samsung DDR5 RDIMM module populated with DRAM chips and a central RCD component Compl. p. 13

IV. Analysis of Infringement Allegations

'937 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A memory subsystem operable with a system memory controller of a host system...the memory bus including control/address (C/A) signal lines, data signal lines, and an error signal line The Accused DDR5 RDIMMs are memory subsystems that operate with a host CPU's memory controller via a memory bus with C/A, data, and error (ALERT_n) signal lines, as defined by JEDEC standards. ¶49; ¶54 col. 5:1-16
a printed circuit board configured to be coupled to the system memory controller via the memory bus; [and] dynamic random access memory elements on the printed circuit board... The accused RDIMMs comprise a printed circuit board with DRAM elements. A JEDEC diagram shows the connection of DRAM (SDRAM) elements to the edge connector. ¶50; ¶55 col. 5:51-61
a memory subsystem controller on the printed circuit board...having an open drain output configured to be coupled to the error signal line, wherein the memory subsystem controller is further operable to provide a signaling interface...during normal memory read and write operations and a feedback path...for initialization operation sequences... The RCD on the accused products is alleged to be the "memory subsystem controller." Its ALERT_n pin is alleged to be the "open drain output" coupled to the error line, providing a signaling interface for parity errors (normal operation) and a feedback path for initialization (training modes). A JEDEC diagram illustrates the ALERT_n circuit wiring as an open-drain output. ¶50; ¶56; ¶58; ¶59 col. 7:25-30
wherein the memory subsystem controller is operable to output via the signaling interface a parity error signal in response to a parity error having occurred during any of the normal memory read and write operations The RCD is allegedly configured to output a parity error signal on the ALERT_n pin, as described in the JEDEC standard for the RCD. ¶60; ¶62 col. 8:11-20
wherein the memory subsystem controller is operable to output via the feedback path a first signal related to a first part of the initialization operation sequences and subsequently a second signal related to a second part...the first signal causing the open drain output to be at a low logic level for a first time period...the second signal causing the open drain output to be at the low logic level for a second time period... The RCD allegedly outputs timed low-logic-level signals on the ALERT_n pin during different JEDEC training modes (e.g., DCS Training and DCA Training), which constitute distinct parts of the initialization. A timing diagram from the JEDEC standard shows the ALERT_n pin being driven low for a specific duration during DCS Training Mode. ¶63; ¶64 col. 10:1-24
wherein, during each of the memory read and write operations, the memory subsystem is operable to output or receive data signals in response to respective C/A signals... During normal operation, the accused products exchange data signals (DQ) in response to C/A signals from the host controller, consistent with standard memory function. ¶65 col. 6:45-54
wherein, during the initialization operation, the memory subsystem is not operable to respond to any C/A signals from the system memory controller by outputting to, or receiving from, the data signal lines any data signals. During initialization (e.g., JEDEC CS training modes), all commands to the DRAM are allegedly blocked by the RCD, preventing the transmission of data signals in response to C/A signals. ¶66; ¶67 col. 7:46-52
  • Identified Points of Contention:
    • Scope Questions: A central dispute may arise over whether the term "memory subsystem controller" as used in the patent can be construed to read on the specific, standardized "Registered Clock Driver (RCD)" found in the accused DDR5 products. The defense may argue the patent contemplates a more general-purpose or differently configured controller.
    • Technical Questions: The infringement theory relies heavily on the allegation that the functions of the "ALERT_n" pin, as defined by JEDEC standards, perform the dual-mode signaling required by the claim. A key question will be whether the ALERT_n pin's function during JEDEC "training modes" constitutes the claimed "feedback path for initialization operation sequences," distinct from its role in signaling parity errors during "normal memory read and write operations."

V. Key Claim Terms for Construction

  • The Term: "memory subsystem controller"

    • Context and Importance: This term is critical because the complaint identifies the accused products' Registered Clock Driver (RCD) as this element. The viability of the infringement claim depends on whether the functions and characteristics of a standard RCD fall within the scope of this term as defined by the patent.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification describes the controller in functional terms, stating it "generally controls the operation of the memory module" and may comprise various types of logic, including ASICs or PLDs, suggesting the term is not limited to one specific structure '937 Patent, col. 5:41-59
      • Evidence for a Narrower Interpretation: The patent depicts specific circuit implementations, such as the multiplexer-based logic in Figure 3, which distinguishes between a "task_in_progress signal" and an "error signal" '937 Patent, Fig. 3 '937 Patent, col. 11:18-34 A defendant may argue that these specific embodiments limit the term to a controller that explicitly incorporates such distinct internal logic, rather than a standardized component like an RCD.

  • The Term: "initialization operation"

    • Context and Importance: The claim requires a distinct "feedback path" that is used "during an initialization operation." The complaint alleges that the JEDEC-defined "DCS Training Mode" and "DCA Training Mode" are such operations Compl. ¶¶63-64 Compl. ¶¶66-67 The case may turn on whether these specific, standardized training modes qualify as the "initialization operation" envisioned by the patent.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification explicitly states that an "initialization sequence may comprise one or more training sequences" '937 Patent, col. 6:2-3 This language directly supports including training modes within the term's scope.
      • Evidence for a Narrower Interpretation: The background section describes the problem in the context of a system memory controller (MCH) handing off control to the memory subsystem and then waiting blindly '937 Patent, col. 3:8-27 A defendant might argue that the term is limited to this specific type of MCH-initiated hand-off sequence, and that JEDEC training modes function differently.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges Defendants induce infringement by providing customers and end-users with specifications, datasheets, and instruction manuals that "encourage and facilitate infringing use" of the accused DDR5 products Compl. ¶68 It further alleges contributory infringement, claiming the products have no substantial non-infringing use and constitute a material part of the invention Compl. ¶69
  • Willful Infringement: The complaint alleges that Samsung had pre-suit knowledge of the '937 Patent even before its issuance by "actively monitoring the '017 Application" from which the patent matured Compl. ¶70 For Avnet, willfulness is alleged based on knowledge since at least the filing of the complaint Compl. ¶71

VII. Analyst's Conclusion: Key Questions for the Case

This case presents a focused dispute over a single patent in the technically complex and high-stakes server memory market, layered against a contentious litigation history. The resolution will likely depend on the court's determination of three central questions:

  1. A Question of Construction: Is the patent's term "memory subsystem controller" broad enough to encompass a standardized "Registered Clock Driver (RCD)" as implemented in JEDEC-compliant DDR5 modules, or do the patent's specific embodiments and descriptions limit the term to a more specialized or differently configured device?

  2. A Question of Functionality: Does the operation of the "ALERT_n" pin on the accused RDIMMs, as governed by the JEDEC standard, actually perform the dual-mode signaling function required by Claim 1? This will involve a technical deep dive into whether its use in "training modes" is functionally equivalent to the patent's "feedback path for initialization" and distinct from its use for parity errors in "normal operations."

  3. A Question of Intent: Given the extensive litigation history and the complaint's specific allegation that Samsung monitored the patent application pre-issuance, will the evidence support a finding of willful infringement? This question elevates the potential damages at stake and underscores the strategic nature of the lawsuit.

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