Netlist Inc v. Samsung Electronics Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Netlist, Inc. (Delaware)
  • Defendant: Samsung Electronics Co., Ltd. (Republic of Korea); Samsung Electronics America, Inc. (New York); Samsung Semiconductor, Inc. (California)
  • Plaintiff's Counsel: Irell & Manella LLP
• Case Identification: 2:26-cv-00441, E.D. Tex., 06/01/2026
• Venue Allegations: Venue is alleged to be proper in the Eastern District of Texas because the defendants are subject to personal jurisdiction, maintain regular and established places of business in the district, and have allegedly committed acts of infringement within the district.
• Core Dispute: Plaintiff alleges that Defendant's High Bandwidth Memory (HBM) products infringe a patent related to methods for reducing driver load in stacked memory die packages.
• Technical Context: High Bandwidth Memory (HBM) technology involves vertically stacking multiple DRAM dies to achieve very high data transfer rates, a critical component for modern artificial intelligence (AI) and high-performance computing (HPC) systems.
• Key Procedural History: The complaint details a long and contentious litigation history between the parties, including a 2015 Joint Development and License Agreement (JDLA) that Netlist terminated in 2020, a termination upheld by a jury. Netlist also cites multiple prior jury verdicts in the same district finding that Samsung willfully infringed other Netlist memory patents, resulting in substantial damage awards. The complaint preemptively addresses Samsung's anticipated defenses related to Reasonable and Non-Discriminatory (RAND) licensing obligations under the JEDEC standard-setting body, arguing the patent-in-suit is not a Standard Essential Patent (SEP) and that prior court rulings and Samsung's own conduct negate any such obligations.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,646,537, "Memory Package Having Stacked Array Dies and Reduced Driver Load," issued June 2, 2026

The Invention Explained

• Problem Addressed: In conventional stacked-die memory packages, a single driver must be powerful enough to send signals through interconnects to all dies in the stack. The patent's background explains that these large drivers consume significant power and physical space on the control die '537 Patent, col. 1:30-35
• The Patented Solution: The invention proposes a solution to reduce this driver load. Instead of one set of drivers and interconnects serving all stacked dies, the stack is partitioned into multiple groups (e.g., a "first plurality" and a "second plurality" of dies) '537 Patent, abstract Each group is served by its own dedicated set of interconnects and drivers. This division ensures that any single driver only needs to drive signals to a smaller subset of the total dies, allowing for smaller, more power-efficient drivers '537 Patent, col. 5:6-23 '537 Patent, Fig. 2 The architecture ensures that the interconnects for one group of dies are electrically isolated from the other groups '537 Patent, col. 7:40-51
• Technical Importance: This load-partitioning technique is a key enabling technology for increasing the density of 3D-stacked memory (like HBM) without incurring prohibitive power and area costs associated with large drivers.

Key Claims at a Glance

• The complaint asserts infringement of at least independent Claim 1 Compl. ¶44
• Claim 1 of the '537 Patent recites the following essential elements for a DRAM package:
  • An interface with terminals.
  • Stacked DRAM dies, which include a "first plurality" and a "second plurality" of DRAM dies.
  • A control die coupled between the stacked dies and the interface.
  • Die interconnects, including through-silicon vias (TSVs).
  • The die interconnects include separate "first die interconnects" for the first plurality and "second die interconnects" for the second plurality.
  • The first die interconnects conduct signals (both command/address and data) to the first plurality of dies.
  • The second die interconnects conduct signals to the second plurality of dies.
  • A negative limitation: the first plurality is configured "to not receive or output any signals" via the second die interconnects.
  • A negative limitation: the second plurality is configured "to not receive or output any signals" via the first die interconnects.
  • The control die includes signal conduits that couple the external terminals to the respective first and second die interconnects.
• The complaint does not explicitly reserve the right to assert dependent claims but incorporates all preceding paragraphs into its claim for relief Compl. ¶43

III. The Accused Instrumentality

• Product Identification: The accused instrumentalities are Samsung's High Bandwidth Memory (HBM) products, specifically including HBM2, HBM2E, HBM3, HBM3E, HBM4, and newer versions Compl. ¶24
• Functionality and Market Context:
  • The complaint describes the accused products as high-speed memory technology that utilizes vertically stacked DRAM dies interconnected by through-silicon vias (TSVs) Compl. ¶¶23, 26 A graphic from Samsung's website illustrates the stacked architecture of its HBM products, highlighting the use of Through Silicon Vias (TSVs) to interconnect a base die and vertically stacked core dies Compl. p. 16
  • These products are alleged to be used in data-intensive applications like servers supporting cloud computing, HPC, and AI workloads Compl. ¶19 The complaint notes that these products are marketed under names such as "Aquabolt," "Flashbolt," and "Shinebolt" and are compliant with JEDEC memory standards Compl. ¶24 Compl. ¶25

IV. Analysis of Infringement Allegations

'537 Patent Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: Claim 1 recites a "first plurality" and a "second plurality" of dies. The complaint alleges that in HBM3 and later products, the dies are grouped into four sets for a "spiral configuration" Compl. ¶50 A point of contention may be whether the claim's "first" and "second" plurality structure can be construed to read on an architecture with more than two distinct die groupings and interconnect sets.
  • Technical Questions: The infringement case hinges on the negative limitations requiring electrical isolation between the pluralities. The complaint relies on marketing materials, diagrams from prior art challenges, and JEDEC specifications to argue that interconnects for one channel "bypass" dies belonging to another Compl. ¶¶51-52 A key question for the court will be whether this evidence is sufficient to prove that one plurality is "configured to not receive or output any signals" from the interconnects of another, or if there is a functional or electrical connection not apparent from these high-level diagrams.

V. Key Claim Terms for Construction

• The Term: "plurality of DRAM dies"
  • Context and Importance: The infringement theory depends on partitioning the stack of DRAM dies in the accused HBM products into distinct "pluralities." The construction of this term is critical for determining whether the groupings alleged by Netlist (e.g., odd/even dies, or spiral channel assignments) fall within the claim scope.
  • Intrinsic Evidence for a Broader Interpretation: The specification refers generally to dividing the array dies into "subsets" '537 Patent, col. 18:2-4, which could support a flexible interpretation that covers any logical grouping, including the complex "twist" and "spiral" architectures alleged in the complaint.
  • Evidence for a Narrower Interpretation: The figures and primary embodiments illustrate a straightforward division of a stack into two contiguous groups of dies (e.g., top and bottom halves) '537 Patent, Fig. 2 A defendant may argue this context limits the term "plurality" to such simple, physically adjacent groupings, not the interleaved groupings alleged for the accused products.
• The Term: "configured to not receive or output any signals"
  • Context and Importance: This negative limitation is the core of the patent's claimed isolation and load reduction. The dispute will focus on what level of electrical and functional isolation is required to satisfy "not receive or output."
  • Intrinsic Evidence for a Broader Interpretation: This could be interpreted functionally, meaning the dies are not intended to operate using signals from the other interconnects. The patent's goal is load reduction, suggesting that as long as a driver doesn't have to drive the load of the other plurality, the limitation is met.
  • Evidence for a Narrower Interpretation: The patent specification describes the die interconnects for different subsets as being "electrically isolated" '537 Patent, col. 6:34-36 A defendant may argue this requires a high degree of electrical isolation, and that the complaint's evidence, based on high-level diagrams, fails to rule out phenomena like parasitic coupling or other electrical interactions that would violate this "not receive or output" requirement.

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement by asserting that Samsung provides specifications, datasheets, and instruction manuals that "encourage and facilitate infringing use" of the accused HBM products Compl. ¶55 It also alleges contributory infringement, stating the products have no substantial non-infringing use and constitute a material part of the invention Compl. ¶56
• Willful Infringement: Willfulness is alleged based on Samsung's knowledge of the '537 patent since at least the filing of the complaint, and potentially from its issuance. The complaint further alleges pre-suit knowledge by citing Samsung's admission in other litigation to "actively monitoring Netlist's patent applications prior to issuance" Compl. ¶57

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the claim language of a "first plurality" and "second plurality" of dies, which is illustrated with simple two-group divisions in the patent, be construed broadly enough to encompass the more complex, interleaved, multi-channel "twist" and "spiral" architectures found in Samsung's various HBM products?
• A second central question will be one of evidentiary sufficiency: do the complaint's proffered exhibits-consisting of marketing materials, JEDEC standard tables, and diagrams from prior proceedings-provide sufficient technical proof to meet the claim's negative limitation that one group of dies is "configured to not receive or output any signals" from the interconnects of another, or will a more detailed circuit-level analysis be required to establish the claimed electrical isolation?
• Finally, the case will involve a significant procedural and historical context, raising the question of how the extensive prior litigation between the parties-including prior findings of willful infringement against Samsung and court determinations that related Netlist patents are not standard-essential-will influence matters such as willfulness, damages, and the viability of Samsung's potential RAND-based defenses.