DCT

2:26-cv-00393

Monolithic 3D Inc v. SK hynix Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:26-cv-00393, E.D. Tex., 05/11/2026
  • Venue Allegations: Venue is alleged to be proper as Defendant is a foreign company that may be sued in any judicial district, and because Defendant transacts substantial business and has committed acts of infringement in the Eastern District of Texas.
  • Core Dispute: Plaintiff alleges that Defendant's High Bandwidth Memory (HBM) and 3D NAND semiconductor memory products infringe five U.S. patents related to 3D semiconductor device structures and fabrication methods.
  • Technical Context: The technology at issue is three-dimensional integrated circuit (3D IC) memory, which enables higher density, speed, and power efficiency compared to traditional 2D memory, and is critical for applications in artificial intelligence, high-performance computing, and consumer electronics.
  • Key Procedural History: The complaint alleges that Defendant had knowledge of the asserted patent portfolio at least as of November 26, 2025, when Plaintiff filed its first patent infringement complaints against Defendant, a fact which may be material to the allegations of willful infringement.

Case Timeline

Date Event
2010-05-02 U.S. Patent No. 12,464,734 Priority Date
2014-01-28 U.S. Patent No. 12,362,330 Priority Date
2014-01-28 U.S. Patent No. 12,400,961 Priority Date
2015-09-21 U.S. Patent No. 12,564,006 Priority Date
2015-09-21 U.S. Patent No. 12,250,830 Priority Date
2024-06-17 HPE Discover 2024 conference attended by Defendant
2025-03-11 U.S. Patent No. 12,250,830 Issued
2025-07-15 U.S. Patent No. 12,362,330 Issued
2025-08-26 U.S. Patent No. 12,400,961 Issued
2025-11-04 U.S. Patent No. 12,464,734 Issued
2025-11-26 Plaintiff's first complaints filed against Defendant
2026-02-24 U.S. Patent No. 12,564,006 Issued
2026-05-11 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,564,006 - 3D Semiconductor Device and Structure with Memory Cells and Multiple Metal Layers (Issued Feb. 24, 2026)

The Invention Explained

  • Problem Addressed: The patent's background describes that traditional two-dimensional scaling of integrated circuits (ICs) has stalled, and that wire delays, rather than transistor performance, now dominate the power consumption and performance limitations of ICs Compl. ¶33 '006 Patent, col. 1:15-2:54
  • The Patented Solution: The invention proposes a monolithic three-dimensional semiconductor device architecture. It features a foundational "first level" containing memory control circuits built on a single crystal layer, with multiple subsequent "levels" of memory cells and transistors vertically stacked, or "overlaid," on top Compl. ¶41 '006 Patent, abstract This vertical stacking reduces the length of interconnecting wires, thereby improving performance and power efficiency Compl. ¶33
  • Technical Importance: This monolithic 3D architecture represented a potential paradigm shift to continue increasing memory density and performance beyond the limits of 2D scaling Compl. ¶33

Key Claims at a Glance

  • The complaint asserts at least independent Claim 1 Compl. ¶41
  • The essential elements of Claim 1 include:
    • A 3D semiconductor device comprising: a first level comprising a first single crystal layer and first transistors;
    • A first metal layer disposed above or below the first level;
    • A second metal layer overlaying the first metal layer;
    • A second level comprising second transistors, overlaying the first level;
    • A third level comprising third transistors, overlaying the second level;
    • A fourth level comprising fourth transistors, overlaying the third level;
    • Wherein the second level comprises first memory cells and the fourth level comprises second memory cells;
    • Wherein the first level comprises memory control circuits;
    • Wherein the second memory cells comprise at least four independently controlled memory arrays;
    • Wherein each level comprises a dielectric electrical isolation layer and vias for vertical connection; and
    • Wherein at least one of the second transistors comprises a metal gate.
  • The complaint alleges infringement of "one or more claims" of the patent, suggesting the potential assertion of dependent claims Compl. ¶40

U.S. Patent No. 12,464,734 - Method for Producing 3D Semiconductor Devices and Structures with Transistors and Memory Cells (Issued Nov. 4, 2025)

The Invention Explained

  • Problem Addressed: The patent addresses the manufacturing challenges associated with creating complex, multi-level 3D integrated circuits, noting that prior art methods can suffer from high energy costs and performance-limiting latencies '734 Patent, col. 1:25-2:3
  • The Patented Solution: The invention provides a method for producing a 3D semiconductor device by sequentially forming multiple levels. The method involves providing a first level with memory control circuits, forming at least two additional levels on top, and then performing etch steps, processing steps to form memory cells in the upper levels, and forming vias for vertical connections '734 Patent, abstract '734 Patent, col. 4:26-5:65 A key step disclosed is a "gate replacement" for transistors in an upper level '734 Patent, col. 11:25-12:1
  • Technical Importance: The method provides a pathway for fabricating densely packed 3D memory structures, such as 3D NAND, in a potentially more efficient manner Compl. ¶35

Key Claims at a Glance

  • The complaint asserts at least independent Claim 15 Compl. ¶62
  • The essential elements of Claim 15 include:
    • A method comprising: providing a first level comprising a first single crystal layer;
    • Forming memory control circuits on the first level, comprising first single crystal transistors and at least two interconnection metal layers;
    • Forming at least one second level above the memory control circuits;
    • Performing a first etch step into the second level;
    • Forming at least one third level on top of the second level;
    • Performing additional processing steps to form first memory cells in the second level and second memory cells in the third level;
    • Forming at least one via through the third and second levels to connect to the interconnection metal layers; and
    • A step of gate replacement of at least one third transistor.
  • The complaint alleges infringement of "one or more claims" of the patent, suggesting the potential assertion of dependent claims Compl. ¶61

Multi-Patent Capsule: U.S. Patent No. 12,362,330

  • Patent Identification: U.S. Patent No. 12,362,330, "3D Semiconductor Device and Structure with Connection Paths," issued July 15, 2025 Compl. ¶29
  • Technology Synopsis: The patent describes a 3D semiconductor device with multiple stacked levels of transistors and interconnections. The invention focuses on providing defined electrical connection paths between transistors on different levels and includes specific circuitry, such as a phase-locked loop (PLL) circuit, on the base level to manage clocking and signal integrity in the complex 3D structure '330 Patent, abstract
  • Asserted Claims: The complaint asserts at least independent Claim 8 Compl. ¶79
  • Accused Features: The complaint alleges that SK hynix's HBM products, such as HBM3 memory, infringe by embodying a multi-level structure with connection paths between a base logic die (first level) and overlying DRAM dies (second and third levels), and by including at least one PLL circuit on the logic die Compl. ¶¶80-84

Multi-Patent Capsule: U.S. Patent No. 12,250,830

  • Patent Identification: U.S. Patent No. 12,250,830, "3D Semiconductor Memory Devices and Structures," issued March 11, 2025 Compl. ¶30
  • Technology Synopsis: The patent discloses a 3D semiconductor device with a base level comprising memory control circuits and multiple overlying metal and transistor layers forming a memory array. The invention specifies that the memory control circuit includes a Look Up Table (LUT) circuit, and that an upper level of the structure comprises a mono-crystalline silicon layer, suggesting a focus on high-performance materials and specific control logic for memory repair or redundancy '830 Patent, abstract
  • Asserted Claims: The complaint asserts at least independent Claim 4 Compl. ¶94
  • Accused Features: The complaint alleges that SK hynix's HBM products infringe by comprising a multi-level device with a memory control circuit (on the logic die) that includes an LUT for redundancy mapping, and that the upper DRAM dies constitute an upper level with a mono-crystalline silicon layer Compl. ¶95 Compl. ¶102 Compl. ¶103

Multi-Patent Capsule: U.S. Patent No. 12,400,961

  • Patent Identification: U.S. Patent No. 12,400,961, "3D Semiconductor Device and Structure with Metal Layers," issued August 26, 2025 Compl. ¶31
  • Technology Synopsis: The patent describes a multi-level 3D semiconductor device that includes a temperature sensor. A key aspect is that transistors on one level are "processed independently" of transistors on another level, which points to a fabrication method involving the stacking of separately manufactured layers, a characteristic feature of High Bandwidth Memory (HBM) construction '961 Patent, abstract
  • Asserted Claims: The complaint asserts at least independent Claim 1 Compl. ¶113
  • Accused Features: The complaint alleges that SK hynix's HBM products infringe by including a temperature sensor as required by HBM standards, and because the constituent DRAM dies are manufactured separately before stacking, thereby meeting the "processed independently" limitation Compl. ¶121 Compl. ¶122

III. The Accused Instrumentality

Product Identification

  • The complaint identifies two main categories of accused products:
    1. HBM Accused Products: High Bandwidth Memory including HBM3, HBM3E (e.g., H5UG series), and HBM2E (e.g., H5WR series) Compl. ¶36
    2. 3D NAND Accused Products: Various Solid State Drive (SSD), Universal Flash Storage (UFS), and embedded MultiMediaCard (eMMC) products, such as the PE8000 and Platinum P51 series Compl. ¶36 Compl. ¶61

Functionality and Market Context

  • The accused products are high-performance semiconductor memory modules Compl. ¶7 The HBM products are used in devices requiring high-speed data access, such as artificial intelligence processors and high-performance graphics cards from customers like Nvidia and AMD Compl. ¶19 Compl. ¶20 The 3D NAND products provide high-capacity non-volatile storage for a wide range of consumer electronics, including servers and computers from customers like Dell Compl. ¶14 Compl. ¶¶17-18 The complaint provides a table from a Dell support website showing Dell server products incorporating specific SK hynix drives Compl. p. 6 The complaint alleges that DRAM and NAND products constitute the vast majority of SK hynix's sales Compl. ¶11

IV. Analysis of Infringement Allegations

U.S. Patent No. 12,564,006 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; The accused HBM product's base logic die is alleged to be the first level, with transistors formed in its single crystal silicon substrate. A cross-section of the HBM logic die is provided as evidence Compl. p. 13 ¶42 col. 3:1-7
a second level comprising a plurality of second transistors, said second level overlaying said first level; The first HBM DRAM die stacked on top of the logic die is alleged to be the second level containing second transistors. An annotated diagram shows this stacking Compl. p. 15 ¶44 col. 3:12-14
a third level comprising a plurality of third transistors, said third level overlaying said second level; The second HBM DRAM die in the stack is alleged to be the third level containing third transistors. ¶45 col. 3:15-17
a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, The third HBM DRAM die in the stack is alleged to be the fourth level containing fourth transistors. ¶46 col. 3:17-19
wherein said first level comprises memory control circuits, The logic die at the base of the HBM stack is alleged to contain the memory control circuits for the entire stack. An optical image of a delayered HBM logic die shows control circuitry Compl. p. 20 ¶49 col. 3:32-33
wherein said second memory cells comprise at least four memory arrays, wherein each of said four memory arrays are independently controlled, The accused HBM3 product is alleged to have at least four independently controlled memory arrays, citing a JEDEC standard diagram showing a general overview of a DRAM die stack with channels Compl. p. 21 ¶50 col. 3:36-39
wherein said first level, said second level, said third level, and said fourth level each comprise a dielectric electrical isolation layer disposed in-between and comprise vias and/or thru-layer vias for vertical connection, The accused product allegedly uses through-silicon vias (TSVs) with dielectric liners to connect the vertically stacked dies. A scanning electron microscope (SEM) image details the TSV structure Compl. p. 22 ¶51 col. 3:40-45
and wherein at least one of said second transistors comprises a metal gate. The wordlines in the HBM DRAM die, which act as transistor gates, are alleged to be made of tungsten, a metal. A detailed SEM image of the memory circuitry is provided Compl. p. 23 ¶52 col. 3:46-47

Identified Points of Contention ('006 Patent):

  • Scope Question: A central dispute may arise over the term "level" and the phrase "overlaying said first level". The complaint's theory maps separately manufactured and stacked dies to the claimed "levels" Compl. ¶¶42-46 A court will need to determine if this construction is consistent with the patent's specification, which may describe the levels as being formed monolithically.
  • Technical Question: The infringement allegation relies on reverse engineering and analysis of the accused products. A key technical question will be whether the evidence presented, such as the cross-sectional images, is sufficient to prove that each DRAM die in the stack constitutes a separate "level" with its own distinct "plurality of transistors" as required by the claim language.

U.S. Patent No. 12,464,734 Infringement Allegations

Claim Element (from Independent Claim 15) Alleged Infringing Functionality Complaint Citation Patent Citation
providing a first level, said first level comprising a first single crystal layer; The accused 3D NAND product (P51 SSD) is alleged to be made by a method that provides a first level comprising the CMOS-under-Array (CUA) circuitry on a single crystal silicon substrate. A cross-section SEM image shows the CUA as the first level Compl. p. 28 ¶63 col. 4:26-28
forming memory control circuits in and/or on said first level, wherein said memory control circuits comprise first single crystal transistors, and wherein said memory control circuits comprise at least two interconnection metal layers; The method allegedly forms memory control circuits in the CUA, which contain single crystal transistors and multiple metal layers for interconnection. ¶64 col. 4:29-34
forming at least one second level disposed above or below said memory control circuits; The first deck of the 3D NAND array ("3D NAND Deck 1") is alleged to be the second level formed above the CUA. ¶64 col. 4:35-37
performing a first etch step into said at least one second level; The method allegedly includes a first etch step to define memory slits in the second level (Deck 1). A close-up SEM image shows slits defined by this etch Compl. p. 30 ¶65 col. 4:38-39
forming at least one third level disposed on top of said second level; The second deck of the 3D NAND array ("3D NAND Deck 2") is alleged to be the third level formed on top of the second level. ¶65 col. 4:40-41
performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level, ... The method allegedly includes processing steps (lithography, deposition, fill) to form memory cells in both Deck 1 (second level) and Deck 2 (third level). A diagram illustrates the layers formed in each deck Compl. p. 31 ¶66 col. 4:42-49
forming at least one via, said at least one via is disposed through said third level and through said second level, and connects to at least one of said at least two interconnection metal layers; The method allegedly forms tungsten vias that connect through the third level (Deck 2) and second level (Deck 1) to the metal layers in the underlying CMOS circuitry. A cross-section SEM image shows these vias Compl. p. 34 ¶69 col. 4:50-54
and a step of gate replacement of said at least one third transistor. The method allegedly includes a gate replacement step, where a sacrificial layer (SiN) is removed and replaced with tungsten gate electrodes for the transistors in the third level (Deck 2). A diagram illustrates this process Compl. p. 35 ¶70 col. 4:55-56

Identified Points of Contention ('734 Patent):

  • Evidentiary Question: As this is a method patent, direct infringement occurs during the manufacturing process, which happens in Defendant's facilities, likely overseas Compl. ¶2 Proving infringement will require evidence of the specific manufacturing steps performed by SK hynix. The complaint relies on analysis of the final product to infer the method steps Compl. ¶¶63-70 A key question will be whether this circumstantial evidence is sufficient to prove that the accused products were "made by" the claimed method.
  • Scope Question: The claim recites "a step of gate replacement." The complaint provides a diagram alleging this occurs Compl. ¶70 The defendant may argue that its manufacturing process, while potentially achieving a similar result, does not literally perform the specific "gate replacement" step as defined and described in the '734 patent.

V. Key Claim Terms for Construction

From U.S. Patent No. 12,564,006:

  • The Term: "level" (e.g., "a first level", "a second level")
  • Context and Importance: The infringement theory depends on mapping distinct, separately manufactured DRAM dies to the claimed "first level," "second level," etc. Compl. ¶¶42-46 The definition of "level" is therefore central to determining if a stack of bonded dies can meet the limitations of a device described with multiple overlaying levels.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent claims use general terms like "level" and "overlaying" without explicitly requiring monolithic integration in the claim language itself. A party might argue that if the patentee intended to limit the claims to monolithically formed levels, they would have used more restrictive language.
    • Evidence for a Narrower Interpretation: The '006 patent's detailed description and figures may exclusively depict embodiments where the levels are monolithically fabricated on a single substrate '006 Patent, abstract A party could argue that this consistent depiction limits the term "level" to a monolithically integrated structure, not a stack of pre-fabricated dies.

From U.S. Patent No. 12,464,734:

  • The Term: "a step of gate replacement"
  • Context and Importance: This term describes a specific manufacturing technique. Proving infringement requires demonstrating that the accused products were made using a process that includes this exact step. The complaint alleges this based on analysis of the final product's structure Compl. ¶70
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification may describe gate formation in general terms, and a party could argue that any process that results in a final gate structure similar to the one disclosed should be considered equivalent, even if the exact sequence of removing a sacrificial gate and depositing a final gate differs.
    • Evidence for a Narrower Interpretation: The patent likely contains specific descriptions and figures detailing the "gate replacement" process, which would define the term narrowly '734 Patent, col. 11:25-12:1 A party would argue that only a process following this specific sequence of deposition, etching, and replacement meets the claim limitation, and that other gate-last techniques might not infringe.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement by asserting that SK hynix provides instructions, documentation, technical support, and product manuals that encourage and instruct customers (e.g., Dell, Nvidia, AMD) and end-users to use the accused products in an infringing manner Compl. ¶54 Compl. ¶86 It also alleges contributory infringement, stating the accused products are a material part of the invention, not a staple article of commerce, and are especially made for infringing use Compl. ¶55 Compl. ¶87
  • Willful Infringement: Willfulness is alleged based on SK hynix's purported knowledge of the patent portfolio "at least as of the filing of MonolithIC 3D's first complaints against SK hynix on November 26, 2025" Compl. ¶37 Compl. ¶56 This constitutes an allegation of pre-suit knowledge.

VII. Analyst's Conclusion: Key Questions for the Case

  1. A Definitional Question of Structure: Will the term "level" in the '006 patent be construed broadly enough to read on a stack of separately manufactured and bonded dies, as Plaintiff alleges, or will the court limit the term to monolithically integrated layers, potentially supported by the patent's written description? The outcome of this claim construction will be critical for the infringement analysis of the HBM products.
  2. An Evidentiary Question of Process: Can Plaintiff prove, based on analysis of the final 3D NAND products, that Defendant's overseas manufacturing process infringes the specific sequence of steps in the '734 method patent? This raises the classic challenge of proving infringement of a method claim for an imported product without direct evidence from the factory floor.
  3. A Question of Independent Creation: Central to several patents is the concept of independent processing of different transistor levels (e.g., '961 Patent). While this appears to factually describe HBM construction, a key legal question will be whether this description of a known industry practice is sufficient to establish infringement of a patent claim that recites it as an inventive element.
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