DCT

2:26-cv-00392

Monolithic 3D Inc v. Kioxia Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:26-cv-00392, E.D. Tex., 05/11/2026
  • Venue Allegations: Venue is alleged to be proper on the basis that the Defendant is a foreign company, which may be sued in any judicial district.
  • Core Dispute: Plaintiff alleges that Defendant's 3D NAND memory products infringe five U.S. patents related to the structure and fabrication methods of three-dimensional semiconductor devices.
  • Technical Context: The lawsuit concerns 3D NAND flash memory, a technology that enables high-density data storage by stacking memory cells vertically, which is fundamental to modern solid-state drives (SSDs), smartphones, and data center infrastructure.
  • Key Procedural History: The complaint alleges that Defendant had knowledge of the asserted patent portfolio at least as of November 26, 2025, when Plaintiff filed a prior complaint against Defendant asserting patents from the same family. This prior litigation may be significant for the Plaintiff's allegations of willful infringement.

Case Timeline

Date Event
2010-10-11 U.S. Patent No. 12,464,734 Priority Date
2014-01-28 U.S. Patent No. 12,564,006 Priority Date
2014-01-28 U.S. Patent No. 12,362,330 Priority Date
2014-01-28 U.S. Patent No. 12,400,961 Priority Date
2015-09-21 U.S. Patent No. 12,250,830 Priority Date
2025-03-11 U.S. Patent No. 12,250,830 Issued
2025-07-15 U.S. Patent No. 12,362,330 Issued
2025-08-26 U.S. Patent No. 12,400,961 Issued
2025-11-04 U.S. Patent No. 12,464,734 Issued
2025-11-26 Prior MonolithIC 3D complaint filed against KIOXIA
2026-02-24 U.S. Patent No. 12,564,006 Issued
2026-05-11 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,564,006 - "3D Semiconductor Device and Structure with Memory Cells and Multiple Metal Layers"

  • Patent Identification: U.S. Patent No. 12,564,006, "3D Semiconductor Device and Structure with Memory Cells and Multiple Metal Layers," issued February 24, 2026.

The Invention Explained

  • Problem Addressed: The patent's background section describes the slowdown of traditional two-dimensional scaling in semiconductor memory, which has led to stalled progress in memory capacity and performance, and highlights the performance degradation caused by wire interconnects in modern integrated circuits (ICs) '006 Patent, col. 1:15-50
  • The Patented Solution: The patent discloses a monolithic three-dimensional IC structure to overcome these limitations '006 Patent, col. 1:51-55 The invention proposes stacking multiple layers of transistors and memory cells, with a base "first level" containing memory control circuits fabricated on a high-quality single-crystal layer, and subsequent "levels" of memory cells built on top '006 Patent, abstract '006 Patent, col. 2:5-24 This vertical stacking shortens the interconnect paths between logic and memory, aiming to improve performance.
  • Technical Importance: By enabling the vertical stacking of logic and memory components, the technology aims to continue the trend of increasing IC density and performance beyond the limits of traditional 2D scaling '006 Patent, col. 1:41-50

Key Claims at a Glance

  • The complaint asserts at least Claim 1 of the '006 Patent Compl. ¶34
  • The essential elements of independent Claim 1 include:
    • a first level comprising a first single crystal layer with first transistors (memory control circuits);
    • first and second metal layers;
    • a second level comprising a plurality of second transistors (first memory cells) overlaying the first level;
    • a third level comprising a plurality of third transistors overlaying the second level;
    • a fourth level comprising a plurality of fourth transistors (second memory cells) overlaying the third level;
    • wherein the second memory cells comprise at least four independently controlled memory arrays;
    • wherein at least one of the second transistors comprises a metal gate.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 12,464,734 - "Method for Producing 3D Semiconductor Devices and Structures with Transistors and Memory Cells"

  • Patent Identification: U.S. Patent No. 12,464,734, "Method for Producing 3D Semiconductor Devices and Structures with Transistors and Memory Cells," issued November 4, 2025.

The Invention Explained

  • Problem Addressed: The patent background addresses the challenge of integrating logic and memory, noting that conventional methods suffer from high energy costs and performance limitations due to long interconnects '734 Patent, col. 1:26-30 It also notes the difficulty of fabricating transistors in upper layers without damaging underlying layers due to high-temperature processing '734 Patent, col. 2:31-41
  • The Patented Solution: The patent describes a method for producing a 3D semiconductor device by forming a logic-containing first level (e.g., on a CMOS wafer) and memory-containing upper levels (second and third levels) separately, and then "performing bonding of said first level to said second level" '734 Patent, abstract This layer-transfer approach allows the high-temperature fabrication of memory cells to occur without thermally damaging the pre-fabricated logic transistors on the first level '734 Patent, col. 2:62-67
  • Technical Importance: This fabrication method provides a pathway to create monolithic 3D ICs by combining separately optimized strata, which is a key enabler for heterogeneously integrating different types of device technologies, such as logic and memory '734 Patent, col. 2:5-12

Key Claims at a Glance

  • The complaint asserts at least Claim 1 of the '734 Patent Compl. ¶54
  • The essential elements of independent Claim 1 include:
    • providing a first level comprising a first single crystal layer;
    • forming memory control circuits on the first level;
    • forming at least one second level and at least one third level;
    • performing processing steps to form memory cells within the second and third levels;
    • performing bonding of said first level to said second level;
    • wherein said third level is disposed above said second level.
  • The complaint does not explicitly reserve the right to assert dependent claims.

Multi-Patent Capsules

  • Patent Identification: U.S. Patent No. 12,362,330, "3D Semiconductor Device and Structure with Connection Paths," issued July 15, 2025 Compl. ¶22

  • Technology Synopsis: The patent addresses the challenge of interconnecting different functional layers in a 3D semiconductor device '330 Patent, col. 1:14-20 The solution describes a device structure featuring "a plurality of connection paths" that provide electrical connections between transistors on different strata, specifically from a "first level" containing a voltage regulator to transistors on a "third level" '330 Patent, abstract

  • Asserted Claims: At least Claim 1 Compl. ¶74

  • Accused Features: The complaint alleges that the accused KIOXIA BiCS8 products, which use CMOS-bonded-to-array (CBA) technology, have tungsten vias that serve as "connection paths" between the first-level CMOS logic (which includes voltage regulators) and the upper-level 3D NAND memory transistors Compl. ¶¶75-80

  • Patent Identification: U.S. Patent No. 12,250,830, "3D Semiconductor Memory Devices and Structures," issued March 11, 2025 Compl. ¶23

  • Technology Synopsis: The patent addresses the need for advanced bonding techniques in 3D memory devices '830 Patent, col. 2:51-56 The invention describes a 3D memory device comprising a "hybrid bonding layer" to connect a first level containing memory control circuits (including a Look-Up Table) to an upper level containing a memory array '830 Patent, abstract

  • Asserted Claims: At least Claim 1 Compl. ¶90

  • Accused Features: The complaint alleges KIOXIA's BiCS8 products use a "hybrid bonding layer" comprising a mix of oxide and copper to bond the CMOS control layer to the 3D NAND memory array. It further alleges that the control circuit contains a Look-Up Table for managing bad memory blocks Compl. ¶¶91-97

  • Patent Identification: U.S. Patent No. 12,400,961, "3D Semiconductor Device and Structure with Metal Layers," issued August 26, 2025 Compl. ¶24

  • Technology Synopsis: The patent discloses a 3D semiconductor device architecture where at least one element within a lower level of transistors has been "processed independently" of an upper level of transistors '961 Patent, abstract This suggests a fabrication process involving the joining of separately manufactured device layers, a hallmark of certain monolithic 3D integration techniques. The patent also calls for the inclusion of a temperature sensor.

  • Asserted Claims: At least Claim 1 Compl. ¶107

  • Accused Features: The complaint alleges that KIOXIA's BiCS8 products are made using a "deck stacking" process, where a first deck of memory cells (the "second transistors") is processed independently from a second deck of memory cells (the "third transistors") before they are stacked. This independent processing is alleged to meet the claim limitation. The complaint also asserts that temperature sensors are required for advanced 3D NAND Compl. ¶¶113-114

III. The Accused Instrumentality

  • Product Identification: The complaint identifies "all KIOXIA SSD products comprising 3D NAND," specifically naming the CM, PM, RM, FL, CD, XD, BG, and XG Series SSDs, as well as all KIOXIA NAND storage products including all 3D Flash Memory (e.g., BiCS Flash) Compl. ¶29 The infringement analysis focuses on the KIOXIA part number T2BIGB5A2V, which comprises BiCS8 3D BiCs Flash memory and bears the die marking "FYU6 1T" Compl. ¶33 A product photograph shows this memory chip integrated into a Corsair MP700 ELITE SSD Compl. p. 9
  • Functionality and Market Context: The accused products are high-density non-volatile memory components used in solid-state drives and other consumer electronics Compl. ¶13 The complaint's technical allegations center on the physical construction of the memory chips, specifically the use of CMOS-bonded-to-array (CBA) technology, where a wafer with CMOS logic circuits is bonded to a wafer with 3D NAND memory arrays Compl. ¶¶35; 41 The complaint also highlights the use of "deck stacking," where multiple tiers of memory cells are fabricated on top of each other Compl. ¶¶35; 37 The complaint provides a micrograph showing an eight-die stack within the accused product Compl. p. 9

IV. Analysis of Infringement Allegations

'006 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel The first level is the CMOS Bonded to Array (CBA) layer, which is a single crystal silicon substrate containing the NAND controller circuits (first transistors) (Compl. ¶35). The complaint provides a micrograph labeling the "first level" and "first transistors" (Compl. p. 11). ¶35 col. 4:5-15
a first metal layer...a second metal layer overlaying said first metal layer The CBA layer contains multiple metal interconnect layers, identified in a micrograph as the "first metal layer" and "second metal layer" (Compl. ¶36; Compl. p. 12). ¶36 col. 4:16-20
a second level comprising a plurality of second transistors, said second level overlaying said first level The "second level" is identified as 3D NAND Deck 2, which contains NAND flash memory cell transistors and overlays the first (CBA) level (Compl. ¶36; Compl. p. 12). ¶36 col. 4:21-24
a third level comprising a plurality of third transistors, said third level overlaying said second level A portion of 3D NAND Deck 1 is identified as the "third level," containing horizontally arranged transistors and overlaying the second level (Deck 2) (Compl. ¶37; Compl. p. 13). ¶37 col. 4:25-27
a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level Another portion of 3D NAND Deck 1 is identified as the "fourth level," containing horizontally arranged transistors on a different wordline layer and overlaying the third level (Compl. ¶38; Compl. p. 14). ¶38 col. 4:28-30
wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors The second level (Deck 2) contains a plurality of memory cells, each of which is comprised of one transistor (Compl. ¶39; Compl. p. 15). ¶39 col. 4:31-34
wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors The fourth level (part of Deck 1) contains a plurality of memory cells, each of which is comprised of one transistor (Compl. ¶40; Compl. p. 16). ¶40 col. 4:38-41
wherein said first level comprises memory control circuits The CMOS bonded to array (CBA) circuits in the first level provide access to the bitlines of the 3D NAND array for writing and reading values (Compl. ¶41; Compl. p. 17). ¶41 col. 4:42-43
wherein second memory cells comprise at least four memory arrays, wherein each of said four memory arrays are independently controlled The die is alleged to be split into four independent array sections, visible in a top-down die photograph, which are asserted to be independently controlled (Compl. ¶42; Compl. p. 18). ¶42 col. 4:44-46
wherein at least one of said second transistors comprises a metal gate The wordlines of the 3D NAND, which form the transistor gates for the second transistors, are composed primarily of tungsten, a metal (Compl. ¶44; Compl. p. 20). ¶44 col. 4:65-66
  • Identified Points of Contention:
    • Scope Questions: A central dispute may arise over the definition of a "level." The patent appears to describe vertically stacked, distinct strata, while the complaint maps the "second," "third," and "fourth" levels to different sets of horizontal wordlines within the vertically-formed 3D NAND decks (Compl. ¶¶36-38). The court may need to determine if these horizontal layers within a single monolithically fabricated memory stack constitute distinct "levels" as contemplated by the patent claims.
    • Technical Questions: The claim requires "four memory arrays" that are "independently controlled." The complaint provides a top-down die photograph showing four quadrants and asserts these are independently controlled (Compl. ¶42). The factual basis for this assertion of "independent control" will likely be a point of contention requiring evidence beyond the visual appearance of the die.

'734 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a method for producing a 3D semiconductor device, the method comprising: providing a first level, said first level comprising a first single crystal layer; and forming memory control circuits in and/or on said first level The accused process involves providing a first level (the CBA) comprising a single crystal layer and forming memory control circuits on it (Compl. ¶55; Compl. p. 25). ¶55 col. 10:4-10
wherein said memory control circuits comprise first single crystal transistors, and wherein said memory control circuits comprise at least two interconnection metal layers The memory control circuits in the CBA contain single crystal transistors and multiple metal layers for interconnection (Compl. ¶56; Compl. p. 26). ¶56 col. 10:11-15
forming at least one second level The accused process forms a second level, identified as 3D NAND Deck 2, on a separate wafer before bonding (Compl. ¶56; Compl. p. 26). ¶56 col. 10:16
performing a first etch step into said at least one second level An etch step is performed to define memory tubes in the second level (Compl. ¶57; Compl. p. 27). ¶57 col. 10:17-18
forming at least one third level The accused process forms a third level, identified as 3D NAND Deck 1, on top of the second level (Compl. ¶58; Compl. p. 28). ¶58 col. 10:19
performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level The process involves lithography, depositions, and etching to form the layers and memory cells within each deck (Compl. ¶59; Compl. p. 29). ¶59 col. 10:20-25
wherein said at least one second transistor comprises a metal gate The wordlines of the 3D NAND, which act as transistor gates, are primarily composed of tungsten (Compl. ¶62; Compl. p. 32). ¶62 col. 10:30-31
and performing bonding of said first level to said second level The accused process involves bonding the first level (CMOS wafer) to the second level (3D NAND wafer) as part of the CBA technology (Compl. ¶63; Compl. p. 33). ¶63 col. 10:32-33
wherein said third level is disposed above said second level In the final stacked structure, the third level (Deck 1) is disposed above the second level (Deck 2) (Compl. ¶64; Compl. p. 34). ¶64 col. 10:34-35
and wherein said first level comprises control of power delivery to said at least one third transistor The memory control circuits in the first level provide the necessary voltages to the entire 3D NAND stack, which includes the third transistors (Compl. ¶65; Compl. p. 35). ¶65 col. 10:36-38
  • Identified Points of Contention:
    • Scope Questions: The infringement allegation relies on 35 U.S.C. § 271(g), which requires showing that the accused products were made by the patented process. A key question will be whether the sequence of manufacturing steps used by KIOXIA for its CBA and deck-stacking technology aligns with the specific sequence of "forming," "performing," and "bonding" steps required by Claim 1.
    • Technical Questions: Claim 1 requires "forming at least one third level" and then forming "second memory cells within said third level." The complaint maps this to the formation of 3D NAND Deck 1 (Compl. ¶58). The defense may argue that the "deck stacking" process, where pre-fabricated decks are stacked, is fundamentally different from the in-situ "forming" of levels and cells as described in the patent's specification.

V. Key Claim Terms for Construction

  • For the '006 Patent:

    • The Term: "level" (as in "first level," "second level," etc.)
    • Context and Importance: The infringement theory for the '006 Patent hinges on mapping the claimed "second," "third," and "fourth" levels to different horizontal wordline layers within the same vertically constructed 3D NAND memory decks. Practitioners may focus on this term because its construction will determine whether this mapping is plausible or if a "level" must be a distinct, separately fabricated stratum, which would challenge the infringement allegation.
    • Intrinsic Evidence for a Broader Interpretation: The claims themselves refer to levels "overlaying" other levels, which could be argued to simply mean being in a higher vertical position, a definition that might encompass horizontal layers at different heights '006 Patent, claim 1
    • Intrinsic Evidence for a Narrower Interpretation: The patent's background discusses monolithic 3D ICs as an alternative to TSV technology, suggesting a "level" is a complete, independently functional stratum of transistors and wiring that is stacked '006 Patent, col. 1:51-67 The detailed description likely illustrates embodiments where levels are distinct, vertically stacked integrated circuit layers, not just horizontal rows of transistors.

  • For the '734 Patent:

    • The Term: "performing bonding"
    • Context and Importance: Plaintiff's infringement case for the '734 patent rests on the assertion that KIOXIA's CMOS-bonded-to-array (CBA) manufacturing technique constitutes "performing bonding of said first level to said second level" Compl. ¶63 The precise definition of "bonding" as taught in the patent will be dispositive.
    • Intrinsic Evidence for a Broader Interpretation: The specification may use "bonding" in a general sense to refer to any process that joins two semiconductor wafers or dies, which could encompass the accused CBA process '734 Patent, col. 2:5-12
    • Intrinsic Evidence for a Narrower Interpretation: The '734 patent's detailed description or figures may disclose specific bonding methods (e.g., oxide-to-oxide bonding, hybrid bonding) with particular interface characteristics. If the accused CBA process differs materially from these specific disclosed embodiments, it could support a narrower construction that might not read on the accused process '734 Patent, abstract '734 Patent, col. 10:32-33

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement for all asserted patents. The inducement allegations are based on KIOXIA's affirmative acts of manufacturing, selling, and distributing the accused products, as well as providing technical support, product manuals, advertisements, and other documentation that instruct customers and end-users on how to use the products in an infringing manner Compl. ¶¶46; 53; 82; 99; 116
  • Willful Infringement: The complaint alleges that KIOXIA has willfully infringed the patents-in-suit. This allegation is supported by the claim that KIOXIA had knowledge of Plaintiff's patent portfolio at least as of November 26, 2025, due to a prior infringement complaint asserting related patents. The complaint argues this constitutes knowledge or willful blindness to its ongoing infringement Compl. ¶¶48; 68; 84; 101; 118

VII. Analyst's Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can the term "level," as used in the context of stacking distinct integrated circuit layers, be construed to read on different horizontal wordline layers within a single, vertically-etched 3D NAND memory deck? The resolution of this claim construction dispute may be dispositive for the infringement analysis of the '006 patent.

  • A central question for the method patent ('734) will be one of process equivalence: does KIOXIA's manufacturing process, which involves bonding a CMOS logic wafer to a 3D NAND memory wafer (CBA), practice the specific sequence of forming, etching, and bonding steps required by the asserted claim, or is there a fundamental mismatch in the claimed versus accused processes?

  • A key factual and legal issue will be one of knowledge and intent: did the prior litigation filed in 2025 provide KIOXIA with pre-suit knowledge of the specific patents-in-suit, and if so, was its continued manufacturing and sale of the accused products post-notice an act of willful infringement subjecting it to potential enhanced damages?

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