Lock Semiconductor LLC v. Texas Instruments Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Lock Semiconductor LLC (Texas)
  • Defendant: Texas Instruments Incorporated (Delaware)
  • Plaintiff's Counsel: Fabricant, Rubino & Lambrianakos LLP
• Case Identification: 2:26-cv-00298, E.D. Tex., 04/15/2026
• Venue Allegations: Venue is alleged to be proper in the Eastern District of Texas based on Defendant's regular and established place of business in the District, including a commercial manufacturing facility and construction of a new chip manufacturing facility, as well as Defendant's alleged commission of infringing acts within the District.
• Core Dispute: Plaintiff alleges that Defendant's microcontrollers and processors infringe three patents related to integrated circuit power management, cache coherency, and hardware security.
• Technical Context: The lawsuit involves foundational semiconductor technologies for managing power consumption, data integrity in memory caches, and secure processing, which are critical in a wide range of electronics from industrial controls to automotive systems.
• Key Procedural History: The complaint alleges Defendant had pre-suit knowledge of the patents. It alleges knowledge of the '401 Patent from at least March 2012 due to its hiring of one of the patent's named inventors. It alleges knowledge of the '400 Patent from at least June 19, 2013, when the patent was cited by a USPTO Examiner during the prosecution of one of Defendant's own patent applications.

Case Timeline

Date	Event
2006-10-20	'400 Patent Priority Date
2008-10-24	'401 Patent Priority Date
2010-02-02	'280 Patent Priority Date
2011-05-31	'401 Patent Issue Date
2012-02-14	'400 Patent Issue Date
2012-03-XX	Alleged date of TI's awareness of '401 Patent via hiring of inventor
2013-06-19	Alleged date of TI's awareness of '400 Patent via USPTO office action
2016-05-31	'280 Patent Issue Date
2026-04-15	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,952,401: "Standby Control Circuit and Method" (Issued May 31, 2011)

The Invention Explained

• Problem Addressed: Integrated circuits often use a "reduced power operating mode" where the main system clock is turned off to save power. In this state, conventional circuits that rely on the main clock cannot respond to an asynchronous "standby" signal, potentially leading to data corruption or unpredictable operation when trying to enter a deeper, battery-powered standby mode Compl. ¶13 '401 Patent, col. 1:10-24 '401 Patent, col. 1:57-65
• The Patented Solution: The patent describes a dual-mode control circuit. In "normal operating mode," a first control circuit uses the primary system clock to synchronize the standby signal. In "reduced power mode," when the primary clock is inactive, a second control circuit uses a secondary, always-on clock (like a real-time clock oscillator) to take over and control the first circuit, ensuring the standby signal is generated reliably. This allows the chip to gracefully enter standby mode from either a fully active or a power-saving state '401 Patent, abstract '401 Patent, col. 6:1-21 '401 Patent, FIG. 2
• Technical Importance: This approach provides a robust method for managing power state transitions in complex systems-on-a-chip (SoCs), improving reliability and preventing errors during power-down sequences.

Key Claims at a Glance

• The complaint asserts infringement of at least independent Claim 1 Compl. ¶25
• Essential elements of Claim 1 include:
  • A standby control circuit for an integrated circuit module having a primary clock (active in normal mode, inactive in reduced power mode) and a secondary clock (always active).
  • A "first control circuit" responsive, in normal mode, to an asynchronous standby signal to output a standby mode signal synchronous with the "primary clock signal".
  • A "second control circuit" responsive, in reduced power mode, to the asynchronous standby signal to "control the first control circuit" to output the standby mode signal synchronous with the "secondary clock signal".
  • The first control circuit includes a "first synchronizer circuit" with at least two edge-triggered registers that receive the primary clock as an input.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,117,400: "System and Method for Fetching an Information Unit" (Issued Feb. 14, 2012)

The Invention Explained

• Problem Addressed: The patent addresses a data coherency problem that can arise in processors using both "speculative fetch" (prefetching data that is likely to be needed soon) and a "write-through" cache policy (writing data simultaneously to the cache and main memory). A conflict can occur if the processor writes new data while the cache is prefetching an old version of that same data, potentially causing the stale, prefetched data to overwrite the new data in the cache '400 Patent, col. 1:55-62 '400 Patent, col. 2:5-11
• The Patented Solution: The invention proposes delaying the "hit or miss" determination for a write-through operation until any ongoing speculative fetch operations are complete (i.e., the "fetch unit is empty"). By waiting, the system ensures that if an older, speculatively fetched version of data arrives, the cache logic will correctly identify it as stale in comparison to the newer data from the processor's write operation and handle it appropriately, preventing data corruption '400 Patent, abstract '400 Patent, col. 4:40-52 '400 Patent, FIG. 8
• Technical Importance: This method provides a mechanism to ensure data integrity in high-performance processors that use aggressive prefetching techniques, which is crucial for system stability.

Key Claims at a Glance

• The complaint asserts infringement of at least independent Claim 8 Compl. ¶42
• Essential elements of Claim 8 include:
  • A device adapted to fetch an information unit.
  • A "processor" adapted to generate a request to execute a "write through cacheable operation".
  • A "cache module" adapted to receive an indication that a "fetch unit is empty", and in response, "determine whether the cache module stores an older version" of the information unit and "selectively stores" it in response.
  • An "arbiter" adapted to empty the fetch unit.
  • The fetch unit is coupled to the cache module and to a high level memory.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 9,355,280: "Apparatus and Method for Providing Hardware Security" (Issued May 31, 2016)

Technology Synopsis

The patent describes a Hardware Security Module (HSM) that creates a secure boundary within an integrated circuit to protect cryptographic keys and sensitive operations Compl. ¶15 '280 Patent, abstract All communication with the outside, non-secure world is forced through a single, controlled interface. A security processor inside the boundary can unwrap and use keys to decrypt data, but the unwrapped keys themselves are never exposed externally, ensuring they cannot be copied or stolen '280 Patent, col. 3:26-40 '280 Patent, col. 4:22-31

Asserted Claims

At least independent Claim 1 Compl. ¶58

Accused Features

The complaint alleges that the Hardware Security Module (HSM) in the AM26x Sitara Microcontrollers Family infringes. The accused features include the HSM's "Secure Zone," its use of device-unique keys to decrypt code, its secure key cache, and its interconnect buses that manage data flow between the secure and non-secure parts of the chip Compl. ¶¶59-63 A diagram in the complaint shows the architecture of the accused HSM, including its "Secure Zone" and interconnect infrastructure (Compl. p. 46, p. 53).

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are various families of Texas Instruments microcontrollers (MCUs) and processors Compl. ¶21 Specifically, the complaint identifies the TMS320F28x family for the '401 patent Compl. ¶24, the AM6x Sitara Processor families for the '400 patent Compl. ¶41, and the AM26x Sitara MCU and F29x families for the '280 patent Compl. ¶57

Functionality and Market Context

The complaint alleges these are widely used integrated circuits found in a vast array of applications, including industrial automation, automotive systems, power delivery, and medical devices (Compl. ¶21; Compl. ¶22).

• '401 Patent: The infringement allegations focus on the low-power management features of the TMS320F28x family. The complaint asserts these products have a "normal operating mode" with an active primary clock (e.g., "SYSCLK/CPUCLK") and a "reduced power mode" (e.g., STANDBY mode) where that clock is gated (inactive) Compl. ¶27 It further alleges a secondary, always-on clock (e.g., "WDCLK" from the Watchdog timer) exists and is used to manage wakeup from the low-power state Compl. ¶27 Compl. ¶29 A diagram from a TI technical manual, Figure 3-3, illustrates the accused clocking system architecture Compl. p. 8
• '400 Patent: The allegations target the cache architecture of the AM65x Sitara Processors, which feature Arm Cortex-A53 processor cores with L1 and L2 caches Compl. ¶44 Compl. p. 27 The complaint alleges these processors perform "write through cacheable" operations and have a "Data Cache Unit" (the cache module) and a "load/store pipeline" (the fetch unit) Compl. ¶¶44-45 The infringement theory centers on the device's alleged behavior when a cache error is detected, which is said to involve flushing the line and re-fetching data Compl. ¶45 Compl. p. 30 A functional block diagram, Figure 3-1, shows the overall architecture of the accused AM65x processor Compl. p. 28

IV. Analysis of Infringement Allegations

'401 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a standby control circuit for an integrated circuit module having a primary clock circuit...and a secondary clock circuit...	The Accused Products include a clocking system with a primary clock ("SYSCLK/CPUCLK") active in normal mode and gated in STANDBY mode, and a secondary Watchdog clock ("WDCLK") that is always active.	¶27	col. 6:3-9
a first control circuit responsive, in the normal operating mode, to an asynchronous standby signal...to output...a standby mode signal synchronous with the primary clock signal...	The "ePIE" (Enhanced Peripheral Interrupt Expansion) module is alleged to be the first control circuit, responding to a "WAKEINT" interrupt to generate a standby mode signal ("IDLE" instruction) synchronous with "SYSCLK/CPUCLK".	¶28	col. 6:55-63
a second control circuit responsive, in the reduced power mode, to the asynchronous standby signal...to control the first control circuit to output the standby mode signal synchronous with the secondary clock signal...	The "Low Power Mode (LPM) Logic and Watchdog (WD)" is alleged to be the second control circuit, which responds to the "WAKEINT" signal and controls the "ePIE" to output an interrupt to the CPU synchronous with the "WDCLK".	¶29	col. 6:63-68
wherein the first control circuit includes a first synchronizer circuit comprising at least two edge triggered registers that receive the primary clock signal as a clock input...	The "ePIE" allegedly includes at least two edge-triggered registers (a 16-bit enable register "PIEIERx" and a 16-bit flag register "PIEIFRx") that receive "SYSCLK/CPUCLK" as a clock input.	¶30	col. 7:10-14
the first synchronizer circuit has an input that receives the asynchronous standby signal, and an output for providing the standby mode signal synchronous with the primary clock signal...	The alleged synchronizer circuit ("PIEIERx", "PIEIFRx", "PIEACK") receives the asynchronous "WAKEINT" interrupt as an input and provides a combined interrupt to the CPU as an output, indicating STANDBY.	¶31	col. 8:35-43

• Identified Points of Contention:
  • Structural Scope: A primary question will be whether the accused product's architecture, which comprises general-purpose modules like an interrupt controller ("ePIE") and power management logic ("LPM"), maps onto the specific "first control circuit" and "second control circuit" structure recited in the claim. The defense may argue that these are distinct, multi-function blocks not arranged as the claimed two-part control system.
  • Functional Questions: The analysis will likely focus on whether the accused "LPM Logic and Watchdog" functionally "control[s] the first control circuit" ("ePIE") in the manner required by the claim. The complaint alleges this control happens via an interrupt ("WAKEINT"), raising the question of whether receiving an interrupt constitutes the specific "control" relationship envisioned by the patent.

'400 Patent Infringement Allegations

Claim Element (from Independent Claim 8)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a processor adapted to generate a request to execute a write through cacheable operation of the information unit;	The Arm Cortex-A53 processor cores in the Accused Products are alleged to generate requests for "write through cacheable" operations.	¶44	col. 11:51-54
a cache module adapted to receive an indication that a fetch unit is empty, and in response...determine whether the cache module stores an older version...and selectively stores the information unit...	The Data Cache Unit is alleged to be the cache module. It receives an indication that the load/store pipeline (fetch unit) is empty when an error is detected and the entry is flushed. It then allegedly determines if it stores an older version and selectively stores by re-fetching data from lower-level memory.	¶45	col. 9:56-67
an arbiter adapted to empty the fetch unit;	The cache protection configuration is alleged to be the arbiter, which empties the fetch unit by flushing an entry when an error is detected.	¶46	col. 10:45-50
wherein the fetch unit is coupled to the cache module and to a high level memory.	The load/store pipeline (fetch unit) is allegedly coupled to the Data Cache Unit and to the L2 memory system (high level memory).	¶47	col. 11:59-62

• Identified Points of Contention:
  • Technical Mismatch: A core question is whether the accused functionality-an error correction mechanism that flushes a cache line and re-fetches data upon detecting a parity error-is equivalent to the patent's claimed method for resolving a data coherency conflict between speculative fetching and write-through operations. The purpose and technical context appear different, which may support a non-infringement argument.
  • Scope Questions: The interpretation of "empty the fetch unit" will be critical. The complaint equates this with flushing a cache entry upon an error. The court will need to decide if "emptying" requires a specific operation related to speculative fetches, as described in the patent's background, or if any operation that clears a data pathway, such as an error-induced flush, falls within the claim's scope.

V. Key Claim Terms for Construction

For the '401 Patent:

• The Term: "control the first control circuit"
• Context and Importance: This term is central to the interaction between the two main components of the invention. The infringement theory depends on showing that the accused "LPM Logic" and "Watchdog" exert the claimed "control" over the "ePIE" module. Practitioners may focus on this term because the nature of this "control" is not explicitly defined and the accused implementation relies on standard interrupt signaling rather than a dedicated control line.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification is functional, stating the second circuit is "responsive...to control the first control circuit" '401 Patent, col. 6:63-66, which could be argued to encompass any functional causation, including triggering an interrupt that causes a change in state.
  • Evidence for a Narrower Interpretation: The patent figures show a direct signal line, "CONTRL_EN", from the second control circuit to the first '401 Patent, FIG. 2 '401 Patent, FIG. 3 The specification also describes the "CNTRL_EN" signal being "provided to the asynchronous reset input" of the first circuit's registers '401 Patent, col. 8:40-44 This suggests a specific, direct reset/enable mechanism, which may be narrower than the alleged general interrupt-based interaction.

For the '400 Patent:

• The Term: "fetch unit"
• Context and Importance: The identity and function of the "fetch unit" are fundamental to the claim. The complaint identifies it as a "load/store pipeline" Compl. ¶45 The case may turn on whether this pipeline performs the specific functions, particularly speculative fetching, that the patent attributes to the "fetch unit."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification broadly describes the Data Fetch Unit (DFU) as being "responsible for data fetching and pre-fetching" '400 Patent, col. 3:51-52 This could support an argument that any component performing data retrieval for the cache qualifies.
  • Evidence for a Narrower Interpretation: The patent's problem statement and solution are rooted in the conflict between "speculative fetch operations" and "write-through" policy '400 Patent, col. 2:5-11 This context suggests the claimed "fetch unit" must be one capable of, and engaged in, speculative fetching for the claim to be relevant, a potentially narrower scope than a generic load/store pipeline.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement against all three patents, asserting that Defendant provides technical manuals, datasheets, software development kits (SDKs), and customer support that instruct and encourage customers to use the Accused Products in an infringing manner Compl. ¶32 Compl. ¶48 Compl. ¶64 The complaint also pleads contributory infringement, alleging the accused components are not staple articles of commerce, have no substantial non-infringing uses, and are known by Defendant to be especially adapted for infringement Compl. ¶34 Compl. ¶50 Compl. ¶66
• Willful Infringement: Willfulness is alleged for all three patents. The claims are based on alleged pre-suit knowledge. For the '401 Patent, knowledge is alleged from at least March 2012 due to Defendant's hiring of a named inventor Compl. ¶35 For the '400 Patent, knowledge is alleged from at least June 19, 2013, due to an Examiner citing the patent during prosecution of Defendant's own application Compl. ¶51 For the '280 Patent, knowledge is alleged based on Defendant's status as a direct competitor to the original assignee (Broadcom) and its alleged monitoring of competitor patents Compl. ¶67 The complaint also pleads willful blindness as an alternative theory Compl. ¶36 Compl. ¶52 Compl. ¶68

VII. Analyst's Conclusion: Key Questions for the Case

1. Architectural Equivalence: A central issue for the '401 patent will be one of architectural equivalence. Can the plaintiff demonstrate that the accused products' general-purpose power management logic and interrupt controller are arranged and function as the specific, two-part "standby control circuit" with the claimed "control" relationship, or will the court find a fundamental structural and functional difference between the accused system and the patented design?

2. Contextual Application: The dispute over the '400 patent will likely focus on contextual application. Does the accused products' cache error-correction mechanism-which allegedly flushes a line on a parity error-perform the same function as the patent's specific method for resolving a data coherency conflict between speculative fetches and write-through operations, or is this an attempt to apply a patent to a technically distinct problem and solution?

3. Knowledge and Intent: Given the specific allegations of pre-suit knowledge, a key question will be the evidentiary standard for willfulness. The court will examine whether the alleged hiring of an inventor ('401 patent) and the citation of a patent in an office action ('400 patent) are sufficient to establish the "subjective belief" of a high probability of infringement required for a finding of willful blindness or the deliberate intent required for willful infringement.