Induction Devices LLC v. Bank Of America NA

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Induction Devices LLC (Texas)
  • Defendant: Bank of America, N.A. (Federally Chartered)
  • Plaintiff's Counsel: Shea | Beaty PLLC
• Case Identification: 2:26-cv-00258, E.D. Tex., 03/27/2026
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant maintains a place of business within the district and conducts business there.
• Core Dispute: Plaintiff alleges that Defendant's contactless credit cards infringe seven U.S. patents related to various semiconductor and electronic circuit technologies.
• Technical Context: The asserted patents cover a range of fundamental semiconductor-level technologies, including circuit reset mechanisms, signal multiplexing with reduced jitter, secure memory for Near Field Communication (NFC) transactions, and digital signal processing.
• Key Procedural History: The complaint notes that U.S. Patent No. 7,889,145 was previously litigated in the Western District of Texas but those cases were resolved before any substantive matters were addressed. Additionally, U.S. Patent Nos. 6,868,500 and 6,931,465 have expired, and Plaintiff asserts infringement liability only for a specific period prior to their expiration dates.

Case Timeline

Date	Event
2000-10-26	Priority Date for U.S. Patent No. 6,868,500
2001-03-31	Priority Date for U.S. Patent No. 6,931,465
2005-03-15	U.S. Patent No. 6,868,500 Issued
2005-08-16	U.S. Patent No. 6,931,465 Issued
2006-01-26	Priority Date for U.S. Patent No. 7,449,926
2006-06-01	Priority Date for U.S. Patent No. 7,889,145
2006-12-21	Priority Date for U.S. Patent No. 8,190,885
2007-03-09	Priority Date for U.S. Patent No. 8,370,543
2007-04-17	Priority Date for U.S. Patent No. 8,543,628
2008-11-11	U.S. Patent No. 7,449,926 Issued
2011-03-01	U.S. Patent No. 7,889,145 Issued
2012-05-29	U.S. Patent No. 8,190,885 Issued
2013-02-05	U.S. Patent No. 8,370,543 Issued
2013-09-24	U.S. Patent No. 8,543,628 Issued
2022-06-09	U.S. Patent No. 6,931,465 Expired
2023-01-23	U.S. Patent No. 6,868,500 Expired
2026-03-27	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,449,926 - "Circuit for Asynchronously Resetting Synchronous Circuit"

• Issued: November 11, 2008 Compl. ¶8

The Invention Explained

• Problem Addressed: Synchronous circuits, such as a CPU, need to be reset upon activation or when the power supply decreases Compl. ¶10 '926 Patent, col. 1:19-24 However, using a single type of reset signal can be problematic; an asynchronous reset during normal operation could cause data loss in memory, while a synchronous reset may not be adequate to initialize a circuit that is operating abnormally and should be reset immediately '926 Patent, col. 1:36-45
• The Patented Solution: The patent discloses a reset signal generation circuit that selectively generates either a synchronous or an asynchronous reset signal based on the operational state of the circuit Compl. ¶10 '926 Patent, abstract An operation detection circuit determines if the CPU is "operating normally" or "operating abnormally" '926 Patent, col. 6:58-61 If operating normally, the circuit generates a reset signal synchronous to the internal clock, which allows data in RAM to be preserved; if operating abnormally, it generates an asynchronous reset signal to immediately initialize all synchronous circuits Compl. ¶11 '926 Patent, col. 6:58-7:6
• Technical Importance: This selective approach is designed to enhance circuit reliability by applying the appropriate reset type for a given state, balancing the need for immediate error correction against the need for data preservation during normal resets Compl. ¶11

Key Claims at a Glance

• The complaint asserts infringement of at least independent claim 1 Compl. ¶44
• Claim 1 of the '926 Patent includes the following essential elements:
  • An operation detection circuit for detecting whether a synchronous circuit is operating normally or abnormally and generating an operation detection signal.
  • A signal control circuit for generating a first reset signal based on a system reset signal, a clock signal, and the operation detection signal.
  • The signal control circuit generates a synchronous first reset signal when the synchronous circuit is operating normally.
  • The signal control circuit generates an asynchronous first reset signal when the synchronous circuit is operating abnormally.

U.S. Patent No. 7,889,145 - "Circuit, System, and Method for Multiplexing Signals with Reduced Jitter"

• Issued: March 1, 2011 Compl. ¶13

The Invention Explained

• Problem Addressed: High-performance synchronous systems are sensitive to timing issues like clock skew and jitter, which degrade performance and reliability Compl. ¶16 '145 Patent, col. 1:49-52 While prior art techniques used multiplexers to select between different clock signals (e.g., from multiple PLLs/DLLs), these multiplexer designs themselves could introduce undesirable crosstalk and power supply noise into the clock path '145 Patent, col. 2:56-63 Compl. ¶16
• The Patented Solution: The patent describes an improved multiplexer circuit architecture designed to reduce jitter and noise Compl. ¶15 The solution uses a first logic gate for a first signal, a second for a second signal, and a third gate coupled to their outputs Compl. ¶17 '145 Patent, col. 3:13-20 A static control signal is used to deactivate one of the first two logic gates, ensuring that only one signal is active at a time, which is intended to eliminate crosstalk and noise injection at the gate inputs Compl. ¶17 '145 Patent, col. 3:20-26 The patent further teaches arranging the logic gates in separate power domains to provide additional isolation '145 Patent, col. 3:26-28
• Technical Importance: The described multiplexer design aims to improve the integrity of clock signals in complex synchronous systems by minimizing noise and crosstalk, thereby enhancing overall system performance and reliability Compl. ¶15

Key Claims at a Glance

• The complaint asserts infringement of at least independent claim 10 Compl. ¶54
• Claim 10 of the '145 Patent is a method claim with the following essential steps:
  • Providing a multiplexer circuit with a specific three-logic-gate structure.
  • Deactivating one of two input logic gates with a static control signal so that only one signal is active and supplied to the inputs.
  • Arranging the first and second logic gates within separate power domains.

U.S. Patent No. 8,190,885 - "Non-Volatile Memory Sub-System Integrated with Security for Storing Near Field Transactions"

• Issued: May 29, 2012 Compl. ¶19
• Technology Synopsis: The '885 patent describes a memory module that integrates non-volatile memory, a security processor, and a Near Field Communication (NFC) radio frequency component Compl. ¶21 This integration creates a secure execution environment for processing and storing NFC transaction data, with the security processor enforcing access rights to memory partitions and enabling secure transaction logging to enhance data integrity and traceability Compl. ¶22
• Asserted Claims: Claims 1 and 3 Compl. ¶64
• Accused Features: The complaint accuses Defendant's contactless credit cards of infringement Compl. ¶64

U.S. Patent No. 8,370,543 - "Busy Detection Logic for Asynchronous Communication Port"

• Issued: February 5, 2013 Compl. ¶23
• Technology Synopsis: The '543 patent is directed to synchronizing information access between devices operating in independent time domains, such as a processor and a memory device Compl. ¶25 The invention purports to eliminate conventional restrictions on the pulse width of control signals and the need for high-speed clocks, which in prior systems led to increased complexity, power consumption, and cost Compl. ¶26 Compl. ¶27
• Asserted Claims: Claim 16 Compl. ¶74
• Accused Features: The complaint accuses Defendant's contactless credit cards of infringement Compl. ¶74

U.S. Patent No. 8,543,628 - "Method and System of Digital Signal Processing"

• Issued: September 24, 2013 Compl. ¶28
• Technology Synopsis: The '628 patent discloses a programmable system-on-a-chip featuring a dynamically reconfigurable digital filtering system Compl. ¶30 A microcontroller sends instruction sets to configure a controller and an address-calculation device, which in turn select filter-coefficient addresses. A data path device then uses these coefficients for digital signal processing, an architecture intended to improve resource efficiency and scalability Compl. ¶30 Compl. ¶31
• Asserted Claims: Claim 1 Compl. ¶84
• Accused Features: The complaint accuses Defendant's contactless credit cards of infringement Compl. ¶84

U.S. Patent No. 6,868,500 - "Power on Reset Circuit for a Microcontroller"

• Issued: March 15, 2005 Compl. ¶32
• Technology Synopsis: The '500 patent describes a power-on-reset (POR) circuit for a microcontroller that provides capabilities beyond a single-level reset, including post-boot-up power stability functions Compl. ¶37 The invention addresses shortcomings of prior art systems that either failed to handle post-boot power issues or required additional, expensive resources, by leveraging the existing POR circuitry for these additional power management roles Compl. ¶35 Compl. ¶37
• Asserted Claims: Claim 22 Compl. ¶94
• Accused Features: The complaint accuses Defendant's contactless credit cards of infringement during a period beginning March 27, 2020, and ending at the patent's expiration on January 23, 2023 Compl. ¶96

U.S. Patent No. 6,931,465 - "Intelligent, Extensible SIE Peripheral Device"

• Issued: August 16, 2005 Compl. ¶38
• Technology Synopsis: The '465 patent is directed to a peripheral device with an "intelligent, extensible serial interface engine (SIE)" Compl. ¶40 Unlike conventional SIEs which act as simple conduits requiring an external processor to handle all traffic, this invention's SIE can autonomously process basic protocol requests. It only delegates unrecognized requests to the external processor, thereby aiming to improve performance and reduce the external processor's overhead Compl. ¶40 Compl. ¶41 Compl. ¶42
• Asserted Claims: Claim 13 Compl. ¶99
• Accused Features: The complaint accuses Defendant's contactless credit cards of infringement during a period beginning March 27, 2020, and ending at the patent's expiration on June 9, 2022 Compl. ¶101

III. The Accused Instrumentality

Product Identification

• The complaint identifies the accused instrumentalities as "contactless credit cards" Compl. ¶44 Compl. ¶54 Compl. ¶64

Functionality and Market Context

• The complaint alleges these are contactless credit cards that Defendant makes, uses, sells, imports, provides, or causes to be used Compl. ¶44 These cards are allegedly used in Defendant's "regular course of its business operations for issuing contactless credit cards for use with credit and/or banking accounts maintained by Defendant" Compl. ¶96 The complaint does not provide any specific technical details regarding the internal components, chipsets, architecture, or operation of these cards. No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint alleges that exemplary infringement analyses for each asserted patent are set forth in exhibits (e.g., A-1, B-1), but these exhibits were not provided with the complaint document Compl. ¶45 Compl. ¶55 The complaint's narrative sections for each count do not contain specific factual allegations mapping the features of the accused contactless credit cards to the elements of the asserted claims.

'926 Patent Infringement Allegations

• The complaint alleges direct infringement of at least claim 1 but provides no specific theory as to how a contactless credit card contains an "operation detection circuit" that distinguishes between "normal" and "abnormal" operation to selectively trigger a synchronous or asynchronous reset Compl. ¶44
• Identified Points of Contention: A primary question will be whether the accused cards contain a reset circuit that performs the specific selective functionality required by claim 1. The analysis may turn on what constitutes "abnormal" operation in the context of the patent and whether the accused cards detect such a state to trigger a specific type of reset.

'145 Patent Infringement Allegations

• The complaint alleges direct infringement of at least claim 10 but does not specify how the accused cards practice the claimed method of multiplexing Compl. ¶54 For example, it does not explain how the cards' internal circuitry uses a static control signal to deactivate one of two logic gates or arranges those gates in "separate power domains."
• Identified Points of Contention: The infringement analysis will likely focus on the physical architecture of the integrated circuits within the accused cards. A key technical question will be whether the multiplexing circuits in those chips are arranged in "separate power domains" as required by the claim, a specific design choice that may or may not be present in commodity hardware.

V. Key Claim Terms for Construction

'926 Patent, Claim 1

• The Term: "operating normally or abnormally"
• Context and Importance: This phrase is the central condition that dictates which type of reset signal (synchronous or asynchronous) is generated. The construction of this term will be critical to determining infringement, as it defines the triggering condition for the core functionality of the claim. Practitioners may focus on this term because the case will depend on whether any error-detection or state-monitoring function within the accused cards can be characterized as detecting an "abnormal" operation as contemplated by the patent.
• Intrinsic Evidence for a Broader Interpretation: The specification discusses the CPU operating "erroneously" or "abnormally" in general terms, which could support a construction covering a wide range of fault or error states '926 Patent, col. 1:30-32
• Evidence for a Narrower Interpretation: An embodiment described in the specification detects an abnormal operation using a counter that is periodically cleared by the CPU; an overflow indicates an abnormal state '926 Patent, col. 6:3-11 This suggests the term could be construed more narrowly to relate to this type of "watchdog timer" functionality.

'145 Patent, Claim 10

• The Term: "separate power domains"
• Context and Importance: This term describes a specific physical layout of the claimed multiplexer circuit. Infringement of this method claim hinges on whether the integrated circuits in the accused cards have this specific architecture. Practitioners may focus on this term because it is a concrete technical limitation that requires a specific semiconductor design, which can be verified or disproven through technical analysis of the accused product's hardware.
• Intrinsic Evidence for a Broader Interpretation: The specification states that a "user may arrange the logic gates within separate power domains" '145 Patent, col. 3:26-27, which might be argued to encompass any form of electrical isolation between the gates.
• Evidence for a Narrower Interpretation: The term itself suggests a distinct physical separation of power supplies for the respective logic gates. A defendant may argue this requires physically distinct power supply rails on the semiconductor die, a specific implementation that may not be present in the accused devices.

VI. Other Allegations

• Indirect Infringement: For each asserted patent, the complaint alleges induced infringement under 35 U.S.C. § 271(b) Compl. ¶48 Compl. ¶58 The allegations are based on Defendant allegedly aiding and abetting infringement by partners, customers, and end users through "advertising and distributing the Accused Instrumentalities and providing instruction materials, training, and services" with specific intent or willful blindness Compl. ¶49 Compl. ¶59
• Willful Infringement: The complaint alleges willful infringement for all asserted patents Compl. ¶50 Compl. ¶60 The basis for willfulness is alleged to have begun when Defendant received notice of the patents and the alleged infringement, which the complaint asserts occurred "at least as early as the filing of this Complaint" Compl. ¶47 Compl. ¶57

VII. Analyst's Conclusion: Key Questions for the Case

• A primary issue will be one of evidentiary sufficiency: The complaint broadly accuses "contactless credit cards" but offers no specific technical evidence or analysis mapping the internal circuitry of these cards to the distinct and varied inventions claimed in the seven asserted patents. The viability of the case may depend heavily on what discovery reveals about the actual chipsets and circuit designs used in Defendant's products.
• A second core issue will be one of technical applicability: The case raises the question of whether a portfolio of patents directed to specific, granular solutions in semiconductor design-such as reset signal generation, clock jitter reduction, and digital signal processing architecture-can be construed to cover the operation of standardized components likely used in mass-market contactless credit cards.
• For the expired '500 and '465 patents, a key question will be one of historical proof: can the Plaintiff demonstrate that the specific versions of the accused cards made, used, or sold during the limited statutory damages period (e.g., from March 27, 2020, to the patents' expiration dates) practiced the claimed inventions?