Induction Devices LLC v. Charles Schwab & Co Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Induction Devices LLC (Texas)
  • Defendant: Charles Schwab & Co., Inc. (California); Charles Schwab Bank, N.A. (United States)
  • Plaintiff's Counsel: Shea | Beaty PLLC
• Case Identification: 2:26-cv-00247, E.D. Tex., 03/24/2026
• Venue Allegations: Plaintiff alleges venue is proper because each Defendant has a regular and established place of business within the Eastern District of Texas.
• Core Dispute: Plaintiff alleges that contactless credit cards provided by Defendants infringe seven U.S. patents related to various aspects of semiconductor circuit design and functionality.
• Technical Context: The patents-in-suit address fundamental circuit-level technologies, including power management, signal integrity, secure communications, and digital signal processing, which are foundational to the operation of modern integrated circuits.
• Key Procedural History: The complaint notes that U.S. Patent No. 7,889,145 was previously litigated in the Western District of Texas, but those cases were resolved before any substantive matters were addressed. The complaint also asserts infringement of two expired patents (U.S. Patent Nos. 6,868,500 and 6,931,465) for a specific time period preceding their expiration dates.

Case Timeline

Date	Event
2000-10-26	'500 Patent Priority Date
2001-03-31	'465 Patent Priority Date
2005-03-15	U.S. Patent No. 6,868,500 Issued
2005-08-16	U.S. Patent No. 6,931,465 Issued
2005-06-01	'145 Patent Priority Date
2006-01-26	'926 Patent Priority Date
2006-12-21	'885 Patent Priority Date
2007-03-09	'543 Patent Priority Date
2007-04-17	'628 Patent Priority Date
2008-11-11	U.S. Patent No. 7,449,926 Issued
2011-03-01	U.S. Patent No. 7,889,145 Issued
2012-05-29	U.S. Patent No. 8,190,885 Issued
2013-02-05	U.S. Patent No. 8,370,543 Issued
2013-09-24	U.S. Patent No. 8,543,628 Issued
2020-03-24	Alleged Infringement Period Begins for Expired Patents
2021-01-01	Prior Litigation involving '145 Patent Filed (approximate)
2022-06-09	U.S. Patent No. 6,931,465 Expired
2023-01-23	U.S. Patent No. 6,868,500 Expired
2026-03-24	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,449,926 - Circuit for Asynchronously Resetting Synchronous Circuit

Issued November 11, 2008

The Invention Explained

• Problem Addressed: The patent addresses the need for a circuit to maintain reliability during both normal and abnormal operating states Compl. ¶13 Conventional reset mechanisms may not be optimal for all situations, such as when a CPU operates erroneously versus when it operates as expected.
• The Patented Solution: The invention is a reset signal generation circuit that intelligently chooses between two types of reset signals Compl. ¶12 An "operation detection circuit" determines if the CPU is operating normally or abnormally. For normal operation, it generates a "synchronous" reset signal, which preserves data stored in memory (e.g., RAM) Compl. ¶13 For abnormal operation, it generates an "asynchronous" reset signal to immediately initialize the system Compl. ¶13 '926 Patent, col. 6:58-7:6 The circuit can also make this selection based on the power supply voltage level Compl. ¶14
• Technical Importance: This selective reset approach enhances system stability by applying the appropriate reset strategy for a given operational context, preserving data when possible and ensuring a prompt, full reset when necessary Compl. ¶13

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶46
• Essential elements of Claim 1 include:
  • A reset signal generation circuit for a synchronous circuit.
  • An operation detection circuit for detecting whether the synchronous circuit is operating normally or abnormally.
  • A signal control circuit for generating the first reset signal based on a system reset signal, the clock signal, and the operation detection signal.
  • Wherein the signal control circuit generates a synchronous reset signal when the circuit is operating normally.
  • Wherein the signal control circuit generates an asynchronous reset signal when the circuit is operating abnormally.

U.S. Patent No. 7,889,145 - Circuit, System, and Method for Multiplexing Signals with Reduced Jitter

Issued March 1, 2011

The Invention Explained

• Problem Addressed: The patent describes how prior art multiplexers-circuits that select one of several input signals to pass to an output-can introduce "crosstalk and power supply noise," which degrades the performance and reliability of synchronous systems, particularly in clock networks Compl. ¶18
• The Patented Solution: The patent teaches an improved multiplexer circuit that actively prevents noise by ensuring only one signal path is active at a time Compl. ¶19 A logic block deactivates one of the input signals by supplying a "static control signal" to the logic gates, which eliminates crosstalk and noise injection at the gate inputs '145 Patent, col. 3:20-26 The invention further suggests placing logic gates in separate power domains to provide additional isolation Compl. ¶19
• Technical Importance: By actively managing signal paths to reduce noise and jitter, the invention improves the integrity of signals in high-speed digital systems, which is critical for reliable clock distribution Compl. ¶17 Compl. ¶18

Key Claims at a Glance

• The complaint asserts at least claim 10, which depends from independent method claim 6 Compl. ¶56
• Essential elements of Independent Claim 6 include:
  • A method comprising: deactivating a first signal path to prevent a first signal from propagating through a first logic gate.
  • Activating a second signal path to allow a second signal to propagate through a second logic gate.
  • Wherein the first and second logic gates are coupled to a third logic gate for transmitting one of the first and second signals.

U.S. Patent No. 8,190,885 - Non-Volatile Memory Sub-System Integrated with Security for Storing Near Field Transactions

Issued May 29, 2012

• Technology Synopsis: The '885 Patent is directed to a memory module that integrates a security processor, non-volatile memory, and a Near Field Communication (NFC) radio frequency component Compl. ¶23 This integration creates a secure execution environment for storing and processing NFC transaction data, providing heightened security compared to systems with external-based access control Compl. ¶23 Compl. ¶24
• Asserted Claims: At least claims 1 and 3 are asserted Compl. ¶66 Claim 1 is independent.
• Accused Features: The complaint alleges that contactless credit cards contain the claimed memory module Compl. ¶66

U.S. Patent No. 8,370,543 - Busy Detection Logic for Asynchronous Communication Port

Issued February 5, 2013

• Technology Synopsis: The '543 Patent describes systems and methods for synchronizing access to a device's resources between two independent time domains, for example, between a processor in one clock domain and a memory device in another Compl. ¶27 The invention aims to eliminate prior art restrictions that either required control signal pulses to be wider than the sampling clock period or necessitated complex, power-intensive high-speed clocks to overcome this limitation Compl. ¶28 Compl. ¶29
• Asserted Claims: At least claim 16 is asserted Compl. ¶76 Claim 16 is an independent method claim.
• Accused Features: The complaint alleges that contactless credit cards utilize the claimed synchronization methods Compl. ¶76

U.S. Patent No. 8,543,628 - Method and System of Digital Signal Processing

Issued September 24, 2013

• Technology Synopsis: The '628 Patent is directed to a programmable system-on-a-chip that includes a dynamically reconfigurable digital filtering system Compl. ¶32 Instruction sets from a microcontroller configure a controller and an address-calculation device to select filter-coefficient addresses; a data path device then uses these coefficients to perform digital signal processing on incoming data Compl. ¶32 This architecture is described as providing dynamic reconfiguration, resource efficiency, and a scalable, compact memory architecture Compl. ¶33
• Asserted Claims: At least claim 1 is asserted Compl. ¶86 Claim 1 is an independent system claim.
• Accused Features: The complaint alleges that contactless credit cards contain the claimed programmable system Compl. ¶86

U.S. Patent No. 6,868,500 - Power on Reset Circuit for a Microcontroller

Issued March 15, 2005

• Technology Synopsis: The '500 Patent describes a circuit and system providing Power on Reset (POR) capabilities at multiple levels, as well as post-boot-up power stability functions Compl. ¶36 The invention purports to solve problems with prior art systems that either failed to address post-boot-up power instability or required additional, expensive system resources to do so, by instead utilizing resources already designated for design POR requirements Compl. ¶37 Compl. ¶39
• Asserted Claims: At least claim 22 is asserted Compl. ¶96 Claim 22 is an independent method claim.
• Accused Features: The complaint alleges that contactless credit cards, during the patent's pendency, utilized the claimed methods Compl. ¶96 Compl. ¶98

U.S. Patent No. 6,931,465 - Intelligent, Extensible SIE Peripheral Device

Issued August 16, 2005

• Technology Synopsis: The '465 Patent is directed to a peripheral device with an "intelligent, extensible serial interface engine (SIE)" that autonomously processes basic protocol requests and delegates unrecognized requests to an external processor Compl. ¶42 This approach is contrasted with conventional SIEs, which are described as acting merely as a conduit to an external processor that handles all traffic, thereby reducing performance Compl. ¶43 Compl. ¶44
• Asserted Claims: At least claim 13 is asserted Compl. ¶101 Claim 13 is an independent method claim.
• Accused Features: The complaint alleges that contactless credit cards, during the patent's pendency, utilized the claimed methods Compl. ¶101 Compl. ¶103

III. The Accused Instrumentality

Product Identification

The complaint identifies the accused instrumentalities as "contactless credit cards" made, used, sold, or provided by the Defendants Compl. ¶46 Compl. ¶56

Functionality and Market Context

The complaint alleges that these contactless credit cards incorporate the technologies claimed in the seven patents-in-suit Compl. ¶46 Compl. ¶56 Compl. ¶66 Compl. ¶76 Compl. ¶86 Compl. ¶96 Compl. ¶101 The complaint does not provide specific technical details about the internal circuitry or operation of the accused cards. The infringement theory appears to be that the semiconductor chips embedded within the contactless credit cards contain circuits and/or perform methods covered by the asserted patents, spanning technologies from power-on-reset and clock signal management to secure NFC communication and digital signal processing. No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references preliminary infringement chart exhibits for each asserted patent but does not include them in the filing Compl. ¶47 Compl. ¶57 Accordingly, the narrative infringement theories are summarized below in prose.

'926 Patent Infringement Allegations

The complaint alleges that Defendants' contactless credit cards directly infringe at least claim 1 of the '926 patent Compl. ¶46 The complaint does not provide a specific narrative of how the accused cards meet the limitations of claim 1, which requires a circuit that selectively generates synchronous or asynchronous reset signals based on a CPU's operational state. The central question for infringement will be evidentiary: whether the chips in the accused cards contain a circuit that performs this specific, conditional reset function.

'145 Patent Infringement Allegations

The complaint alleges that Defendants' contactless credit cards directly infringe at least claim 10 of the '145 patent, which claims a method for multiplexing signals Compl. ¶56 The infringement theory rests on the allegation that the chips within the accused cards employ the claimed method of deactivating one signal path while activating another to reduce jitter and noise. An analysis of infringement may focus on whether the multiplexing circuits in the accused devices operate by the specific "deactivating" and "activating" steps recited in the patent's independent claim 6, from which claim 10 depends.

Identified Points of Contention

• Scope Questions: A recurring question may be whether the patented inventions, often described in the context of general-purpose microcontrollers or systems-on-a-chip, apply to the highly specialized Application-Specific Integrated Circuits (ASICs) commonly used in secure payment devices like contactless credit cards.
• Technical Questions: For the '926 patent, a key technical question is what evidence the complaint will rely on to show that the accused card's chip has an "operation detection circuit" that distinguishes between "normal" and "abnormal" CPU operation, as required by the claim, rather than a more generic reset or error-handling mechanism. For the '145 patent, a central question will be whether the accused card's multiplexing method achieves signal selection through the claimed "deactivating a first signal path" or through a different, non-infringing technical approach.

V. Key Claim Terms for Construction

For the '926 Patent (Claim 1)

• The Term: "operation detection circuit"
• Context and Importance: This term defines a core functional element of the invention. Its construction will be critical to determining infringement, as the dispute may center on whether the accused products contain a dedicated circuit for detecting "normal" versus "abnormal" operation, or if they use a different architecture for system monitoring.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification provides a functional description, stating the circuit "generates the operation detection signal OC indicating whether the CPU 11 is operating normally" '926 Patent, col. 6:58-61, which could support an interpretation covering any circuit that achieves this function.
  • Evidence for a Narrower Interpretation: The patent describes a specific embodiment as an "up-counter for counting the internal clock signal CLK" which is periodically cleared by the CPU '926 Patent, col. 4:15-21 A party could argue the term should be limited to or informed by this counter-based implementation.

For the '145 Patent (Claim 6)

• The Term: "deactivating a first signal path"
• Context and Importance: The concept of "deactivating" a path is central to the patent's approach to eliminating crosstalk and noise. The scope of this term will be pivotal; practitioners may focus on whether it requires a specific electrical mechanism (e.g., a physical disconnection) or if it can be satisfied functionally (e.g., holding a signal at a static voltage).
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent's summary suggests a functional goal, where a logic block ensures "only one of the first and second signals is supplied" to downstream gates, which may support a broader construction focused on the result rather than the means '145 Patent, col. 1:15-26
  • Evidence for a Narrower Interpretation: The abstract states deactivation occurs by "supplying a static control signal to the first and second logic gates" '145 Patent, abstract This language could be used to argue that the term requires a specific action directed at the logic gates themselves.

VI. Other Allegations

Indirect Infringement

For all asserted patents, the complaint alleges induced infringement under 35 U.S.C. § 271(b) Compl. ¶50 Compl. ¶60 The alleged inducing acts include "advertising and distributing the Accused Instrumentalities and providing instruction materials, training, and services" Compl. ¶51 Compl. ¶61 The complaint alleges Defendants possessed the requisite intent based on knowledge of the patents and infringement "since at least the date of receiving notice" Compl. ¶51

Willful Infringement

The complaint alleges that infringement has been willful since Defendants first received notice of the patents, which it defines as the filing of the complaint Compl. ¶52 Compl. ¶62 This suggests the willfulness claim is based on alleged post-suit conduct.

VII. Analyst's Conclusion: Key Questions for the Case

This case, involving seven distinct semiconductor patents asserted against a single product category, will likely present several fundamental questions for the court.

• An Evidentiary Question of Implementation: A primary issue will be one of technical proof. Given the high-level nature of the complaint, the case will depend on Plaintiff's ability to demonstrate, likely through complex reverse engineering and technical discovery, that the specific, low-level circuit designs and methods claimed in these seven disparate patents are actually implemented and operate as claimed within the microchips of Defendants' contactless credit cards.
• A Legal Question of Functional Equivalence: A key dispute may be one of functional specificity. Do the general-purpose power, clock, and interface management circuits within the accused chips perform the highly specific, multi-part logical functions required by the asserted claims (e.g., selectively generating synchronous vs. asynchronous resets), or is there a fundamental mismatch between the accused products' actual operation and the narrow requirements of the patent claims?
• A Definitional Question of Scope: The litigation may turn on a question of applicability. Can inventions described in the context of general-purpose semiconductor components be construed to cover the highly integrated, secure, and application-specific circuits typically designed for financial instruments like credit cards, or does the specific context of the accused products place them outside the scope of the patents-in-suit?