2:26-cv-00244
Exactojoin LLC v. Panasonic Corp
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: ExactoJoin LLC (New Mexico)
- Defendant: Panasonic Corporation (Japan)
- Plaintiff's Counsel: Rabicoff Law LLC
- Case Identification: 2:26-cv-00244, E.D. Tex., 03/24/2026
- Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because the defendant is a foreign corporation.
- Core Dispute: Plaintiff alleges that Defendant's unspecified semiconductor products infringe a patent related to compact semiconductor memory device architecture.
- Technical Context: The technology concerns designs for high-density semiconductor memory, aiming to overcome the physical scaling limitations of conventional Dynamic Random-Access Memory (DRAM).
- Key Procedural History: The complaint does not mention any prior litigation, inter partes review proceedings, or licensing history related to the patent-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2009-09-02 | U.S. Patent No. 9,001,581 Earliest Priority Date |
| 2014-02-11 | U.S. Patent No. 9,001,581 Application Filing Date |
| 2015-04-07 | U.S. Patent No. 9,001,581 Issue Date |
| 2026-03-24 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,001,581 - "Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making"
- Patent Identification: U.S. Patent No. 9,001,581 ("the '581 Patent"), "Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making," issued April 7, 2015.
The Invention Explained
- Problem Addressed: The patent's background describes the challenge of scaling down conventional Dynamic Random-Access Memory (DRAM) cells, which typically use a one-transistor, one-capacitor (1T/1C) structure. As transistors shrink, it becomes increasingly difficult to manufacture a capacitor that is small enough yet holds sufficient charge to reliably store data, limiting memory density '581 Patent, col. 1:55-67
- The Patented Solution: The invention proposes a semiconductor memory architecture that eliminates the need for a separate capacitor. Instead, it stores a data state as an electrical charge within an electrically isolated "floating body" of the transistor itself '581 Patent, col. 2:5-9 To further increase density, multiple memory cells are connected in series to form a string, allowing them to share a smaller number of electrical contacts. This "contactless" approach reduces the overall area required for a memory array '581 Patent, abstract '581 Patent, col. 2:9-13
- Technical Importance: This design aims to provide a path for creating denser, more scalable memory arrays compared to traditional DRAM by simplifying the cell structure and reducing the physical overhead associated with electrical contacts.
Key Claims at a Glance
The complaint does not specify which claims of the '581 Patent are asserted, instead referencing "Exemplary '581 Patent Claims" detailed in an external exhibit not provided with the complaint Compl. ¶11 Independent claim 1 is representative of the invention's core structural elements.
- Independent Claim 1:
- A semiconductor memory device comprising: a plurality of semiconductor memory cells;
- at least one contact configured to electrically connect said memory cells to a control line;
- wherein the number of said at least one contact is less than the number of said memory cells;
- and said memory cells being configured to be connected at least in series;
- wherein each of said memory cells comprises a floating body region configured to perform at least one of injecting charge into or extracting charge out of a portion of said at least one of said memory cells to maintain a said state of said at least one memory cells.
III. The Accused Instrumentality
Product Identification
- The complaint does not name any specific accused products Compl. ¶11 It refers only to "Exemplary Defendant Products" that are purportedly identified in "charts incorporated into this Count" via an external Exhibit 2, which was not available for this analysis Compl. ¶11 Compl. ¶16
Functionality and Market Context
- The complaint does not provide sufficient detail for analysis of the functionality or market context of any accused instrumentality. It makes only a conclusory allegation that the unspecified products "practice the technology claimed by the '581 Patent" Compl. ¶16
IV. Analysis of Infringement Allegations
The complaint provides no narrative infringement theory and instead incorporates by reference claim charts from an unprovided "Exhibit 2" Compl. ¶17 The pleading states only that the accused products "satisfy all elements of the Exemplary '581 Patent Claims" Compl. ¶16 Without access to the claim charts or any specific allegations in the body of the complaint, a substantive analysis of the infringement theory is not possible.
No probative visual evidence provided in complaint.
- Identified Points of Contention: Based on the technology of the '581 Patent, several technical and legal questions may arise once the accused products are identified:
- Structural Questions: A primary question will be whether the accused devices feature a memory architecture where multiple memory cells are "connected at least in series" and whether "the number of... contact[s] is less than the number of... memory cells," as required by claim 1. This will require a detailed analysis of the physical layout and circuit design of the accused semiconductor devices.
- Functional Questions: The analysis will likely focus on whether the accused devices use a "floating body region" to store charge. The court may need to determine if the physical mechanism for data storage in the accused products aligns with the patent's description of injecting or extracting charge from this specific region.
V. Key Claim Terms for Construction
The Term: "floating body region"
- Context and Importance: This term is central to the invention, as it defines the physical component where the memory state (a '1' or '0') is stored. The construction of this term will determine whether the patent's scope is limited to specific types of transistor structures or can be read more broadly to cover other forms of capacitor-less memory.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claims themselves describe the region functionally as being "configured to perform at least one of injecting charge into or extracting charge out of" it to maintain a state '581 Patent, col. 48:50-54 This functional language may support an argument that the term covers any electrically isolated semiconductor region that operates in this manner.
- Evidence for a Narrower Interpretation: The specification frequently describes the floating body region in the context of a "semiconductor-on-insulator (SOI) substrate" '581 Patent, col. 11:30-33 An accused infringer may argue that the term should be limited to the specific SOI-based embodiments detailed in the patent, as illustrated in figures such as FIG. 1, which shows floating body (24) positioned above a buried oxide layer (22).
The Term: "the number of said at least one contact is less than the number of said memory cells"
- Context and Importance: This limitation defines the "contactless" or shared-contact architecture that is a key aspect of the patent's claimed density advantage. The entire infringement case for a product could hinge on how a "contact" and a "memory cell" are counted within a complex integrated circuit.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The plain language of the claim sets out a simple mathematical ratio. A patentee may argue that as long as an electrical analysis of the accused device shows fewer contacts than memory cells served by those contacts, the limitation is met, regardless of the specific layout.
- Evidence for a Narrower Interpretation: A defendant may argue that the term must be interpreted in light of the embodiments shown, such as the "string" of memory cells depicted in FIG. 16A, where a group of cells is clearly delineated and connected between two distinct contacts. This could be used to argue against infringement by architectures that do not use such a clearly defined string structure.
VI. Other Allegations
- Indirect Infringement: The complaint alleges induced infringement based on Defendant distributing "product literature and website materials" that allegedly instruct users on how to use the accused products in an infringing manner Compl. ¶14 The knowledge element for inducement is alleged to exist "at least since being served by this Complaint" Compl. ¶15
- Willful Infringement: The complaint alleges that the service of the complaint and its attached claim charts provides Defendant with "actual knowledge of infringement" Compl. ¶13 It further alleges that Defendant's continued infringing activities "despite such actual knowledge" constitute willful infringement Compl. ¶14 No facts supporting pre-suit knowledge are alleged.
VII. Analyst's Conclusion: Key Questions for the Case
- A Threshold Factual Question: The central issue at the outset is the lack of specificity in the complaint. A court will first need to address which specific "Exemplary Defendant Products" are accused and how they allegedly function, details the Plaintiff has deferred to an external exhibit. Without this information, no meaningful analysis of infringement is possible.
- A Core Claim Construction Question: The viability of the infringement claim will likely depend on the definition of "floating body region." The key question for the court will be whether this term is limited to the semiconductor-on-insulator (SOI) structures heavily featured in the patent's detailed description, or if it can be construed more broadly to cover other types of charge-trapping memory technologies.
- An Architectural Interpretation Question: A critical dispute may center on the structural requirement that the "number of... contact[s] is less than the number of... memory cells." The case may turn on how these elements are defined and counted within a modern, highly integrated semiconductor device, raising the question of whether the accused products' architecture falls within the scope of this limitation.